CN112131828B - Data processing method, device and equipment and readable storage medium - Google Patents
Data processing method, device and equipment and readable storage medium Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
Abstract
The application discloses a data processing method, a data processing device, data processing equipment and a readable storage medium. The method disclosed by the application is applied to an FPGA verification platform and comprises the following steps: receiving a data frame to be processed by utilizing at least one data interface; storing the data frame into a memory in the FPGA verification platform according to the storage starting and stopping address; performing matching verification on the data frame, and if the matching verification fails, reserving the storage start-stop address so as to store a new data frame to the memory in an overlay manner according to the storage start-stop address; and counting the residual space of the memory in real time, and if the residual space is smaller than a preset threshold, reading the stored data frame in the memory according to the read start-stop address, and updating the read start-stop address and the storage start-stop address. The data processing device, the data processing equipment and the readable storage medium have the technical effects that the same memory is managed by using the storage starting and stopping address and the reading starting and stopping address, and more storage resources can be prevented from being occupied by data.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a data processing method, apparatus, device, and readable storage medium.
Background
The verification platform can flexibly modify codes for testing based on FPGA (Field Programmable Gate Array). The upper computer sends the test related data to the FPGA verification platform through a data interface on the FPGA verification platform, so that the FPGA verification platform utilizes the data to perform code testing.
Before a processor in the FPGA verification platform processes data, the data can be stored in a cache, after redundant frames or error frames in the data are filtered out, effective data can be stored in another cache, therefore, a secondary cache is arranged in the FPGA verification platform, test related data can be written into different caches, occupied storage resources are more, and the performance of the FPGA verification platform is also reduced.
Therefore, how to avoid the situation that data occupies a large storage space in the FPGA verification platform is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of this, an object of the present application is to provide a data processing method, apparatus, device and readable storage medium, so as to avoid that data occupies a large storage space in an FPGA verification platform. The specific scheme is as follows:
in a first aspect, the present application provides a data processing method applied to an FPGA verification platform, including:
receiving a data frame to be processed by utilizing at least one data interface;
storing the data frame to a memory in the FPGA verification platform according to a storage starting and stopping address;
performing matching check on the data frame, if the data frame matching check is not passed, reserving the storage start-stop address so as to store a new data frame to the memory in an overlay manner according to the storage start-stop address when the data interface is used to receive the new data frame;
and counting the residual space of the memory in real time, and if the residual space is smaller than a preset threshold, updating the read start-stop address and the storage start-stop address after reading the stored data frame in the memory according to the read start-stop address.
Preferably, the performing matching check on the data frame includes:
performing characteristic value matching on the data frame according to a preset matching rule, and performing CRC (cyclic redundancy check) on the data frame;
if the characteristic value matches and the CRC passes, determining that the data frame matches and checks; otherwise, determining that the data frame matching check is not passed.
Preferably, the method further comprises the following steps:
and if the data frame matching check is passed, updating the storage start-stop address to obtain an updated start-stop address, so that the new data frame is stored according to the updated start-stop address when the new data frame is received by using the data interface.
Preferably, the updating the storage start-stop address to obtain an updated start-stop address includes:
and calculating the updating start-stop address according to the storage start-stop address and the address length occupied by the data frame.
Preferably, before reading the stored data frame in the memory according to the read start-stop address, the method further includes:
controlling the data interface to be disabled.
Preferably, after updating the read start-stop address and the storage start-stop address, the method further includes:
controlling the data interface to be enabled.
Preferably, before storing the data frame into the memory in the FPGA verification platform according to the storage start-stop address, the method further includes:
performing bit width conversion on the data frame to adapt to the bus bit width in the FPGA verification platform;
and packaging the data frame according to a preset format.
In a second aspect, the present application provides a data processing apparatus, which is applied to an FPGA verification platform, and includes:
the receiving module is used for receiving a data frame to be processed by utilizing at least one data interface;
the storage module is used for storing the data frame to a memory in the FPGA verification platform according to the storage starting and stopping address;
the matching check module is used for carrying out matching check on the data frame, if the data frame matching check is not passed, the storage starting and stopping address is reserved so that when a new data frame is received by using the data interface, the new data frame is stored to the memory in an overlaying mode according to the storage starting and stopping address;
and the management module is used for counting the residual space of the memory in real time, and updating the read start-stop address and the storage start-stop address after reading the stored data frame in the memory according to the read start-stop address if the residual space is smaller than a preset threshold value.
In a third aspect, the present application provides a data processing apparatus comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the data processing method disclosed in the foregoing.
In a fourth aspect, the present application provides a readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the data processing method disclosed in the foregoing.
According to the scheme, the data processing method is applied to an FPGA verification platform and comprises the following steps: receiving a data frame to be processed by utilizing at least one data interface; storing the data frame to a memory in the FPGA verification platform according to a storage starting and stopping address; performing matching check on the data frame, if the data frame matching check is not passed, reserving the storage start-stop address so as to store a new data frame to the memory in an overlay manner according to the storage start-stop address when the data interface is used to receive the new data frame; and counting the residual space of the memory in real time, and if the residual space is smaller than a preset threshold, updating the read start-stop address and the storage start-stop address after reading the stored data frame in the memory according to the read start-stop address.
It can be seen that, after receiving a data frame to be processed by using at least one data interface, the present application first stores the data frame memory according to the storage start-stop address, where the stored data frame may be valid or invalid. And subsequently, when a new data frame is received by using the data interface, the new data frame is stored into the same memory in an overlay manner according to the storage starting and stopping address, so that the invalid data frame stored in the memory is overlaid. And the method and the device count the residual space of the memory in real time, if the residual space is smaller than a preset threshold, the read start-stop address and the storage start-stop address are updated after the stored data frame in the memory is read according to the read start-stop address, and the new data frame is stored in a covering mode according to the new storage start-stop address, so that the utilization rate of the storage space can be improved. The storage starting and stopping address and the reading starting and stopping address are utilized to effectively manage the same storage space, the utilization rate of the storage is improved, the storage space can be saved during storage, and after the data in the storage starting and stopping address is read, the storage starting and stopping address can be updated in time so that the new data frame can be stored in an overlaying mode when the new data frame is stored next time, and therefore the performance of the FPGA verification platform can be improved. In addition, a plurality of levels of caches do not need to be arranged in the FPGA verification platform, and the implementation can be realized by using one cache space. The hardware circuit layout space of the FPGA verification platform is saved by using one cache space, and convenience is brought to design and implementation of the FPGA verification platform.
Accordingly, the data processing device, the equipment and the readable storage medium provided by the application also have the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a data processing method disclosed herein;
FIG. 2 is a schematic diagram of a data frame structure disclosed in the present application;
FIG. 3 is a block diagram of a data processing scheme disclosed herein;
FIG. 4 is a flow chart of a method of data processing within the framework illustrated in FIG. 3;
FIG. 5 is a schematic diagram of a data processing apparatus according to the present disclosure;
fig. 6 is a schematic diagram of a data processing apparatus disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, before a processor in an FPGA verification platform processes data, the data can be stored in a cache firstly, after redundant frames or error frames in the data are filtered, valid data can be stored in another cache, therefore, in the FPGA verification platform, test related data can be written in for many times, occupied storage resources are more, and the performance of the FPGA verification platform is also reduced. Therefore, the data processing scheme is provided, and the data can be prevented from occupying more storage space of the FPGA verification platform.
Referring to fig. 1, the embodiment of the present application discloses a data processing method applied to an FPGA verification platform, including:
s101, receiving a data frame to be processed by utilizing at least one data interface.
It should be noted that the data interface is a peripheral interface of the FPGA verification platform, and the interface may be an EMAC (Ethernet Media Access Controller ), and the like. A plurality of data interfaces can be arranged in the FPGA verification platform, and each data interface can be regarded as a data channel.
And S102, storing the data frame into a memory in the FPGA verification platform according to the storage start-stop address.
The storage start-stop address comprises a storage start address and a storage end address. The start address is stored for marking a start position of available space in the memory and the end address is stored for marking an end position of the stored data frame in the memory. The memory is specifically a memory in the FPGA verification platform. In the initial state, both the memory start address and the memory end address may be set to 0. In normal use, store the start address + 1.
In a specific embodiment, before storing the data frame into a memory in the FPGA verification platform according to the storage start-stop address, the method further includes: performing bit width conversion on the data frame to adapt to the bus bit width in the FPGA verification platform; and packaging the data frame according to a preset format. The specific bit width conversion method may refer to the prior art, and this description is not repeated herein.
After the data frame is packaged according to the preset format, the packaged data frame is stored, so that a processor can conveniently distinguish different data frames when reading the data frame. Specifically, the preset format can be referred to fig. 2, and the channel number in fig. 2 is a channel identification code, that is, an identification code of the data interface. The frame data is a received valid data frame. The frame length is divided into two types of unit of byte and unit of storage bit width (such as 32 bits) for data extraction and data transmission. The frame header checksum is a 16-bit checksum over the channel number and the two frame lengths. The frame head and the frame tail can be self-defined, and the frame head, the frame tail, the frame structure and the check sum can effectively distinguish different data frames. The end checksum is a 32-bit checksum of the frame data portion, and is generally obtained by adding the first data to the last data of the frame data portion. The preset format can be flexibly modified according to practical application.
S103, matching and checking the data frame, if the matching and checking of the data frame are not passed, reserving the storage starting and stopping address, so that when a new data frame is received by using the data interface, the new data frame is stored into the memory in an overlaying mode according to the storage starting and stopping address.
In one embodiment, the performing the match check on the data frame includes: performing characteristic value matching on the data frame according to a preset matching rule, and performing CRC (cyclic redundancy check) on the data frame; if the characteristic value matching passes and the CRC passes, determining that the data frame matching passes; otherwise, determining that the data frame matching check is not passed.
The preset matching rule may preset feature values to be matched, such as: the header, frame type, frame length, etc. of the received data frame. The characteristic value matching of the data frame can detect whether the data frame comprises data to be processed by a processor in the FPGA verification platform or not, and can also detect whether the data frame is the data frame to be processed by the processor in the FPGA verification platform or not. The CRC check may refer to the prior art, and the description is not repeated herein.
In one embodiment, if the data frame match check passes, it indicates that the data frame is valid, and the storage start-stop address is updated accordingly to obtain an updated start-stop address, so that when a new data frame is received by using the data interface, the new data frame is stored into the memory according to the updated start-stop address. Wherein, updating the storage start-stop address to obtain an updated start-stop address comprises: and calculating and updating the start-stop address according to the storage start-stop address and the address length occupied by the data frame. For example: the storage start address in the storage start-stop address is: 0, the storage end address is: 0, assuming that one data frame occupies 3 address lengths, after the first data frame is stored, the storage start address in the updated start-stop address is: 0+3+1 equals 4, and the storage end address is: 0+3 ═ 3. And if a new data frame is to be stored subsequently, storing from the 4 th address.
If the data frame matching check passes, the storage start-stop address is updated, and the reading start-stop address is also updated at the same time, so that the processor can read the data.
And S104, counting the residual space of the memory in real time, and updating the read start-stop address and the storage start-stop address after reading the stored data frame in the memory according to the read start-stop address if the residual space is smaller than a preset threshold.
It should be noted that the read start/stop address includes a read start address and a read end address. The read start address is used to mark the start position of the first data frame to be read by the processor, and the read end address is used to mark the end position of the stored data frame in the memory. In general, read end address-read start address is the total number of all data frames that are currently to be read by the processor (assuming that the read end address is greater than the read start address).
Updating the read start-stop address may be performed as follows: assuming that the reading end address is 10, the reading start address is 5, and the data frame read by the processor occupies 3 address lengths, after the processor reads the data frame, the reading start address is updated to 5+ 3-8, and the reading end address remains unchanged (assuming that no valid data frame is stored in the process). If there is valid data frame storage in the process, the current reading end address plus the address length occupied by the currently stored data frame is the updated reading end address.
In one embodiment, before reading the stored data frame in the memory according to the read start-stop address, the method further includes: the control data interface is disabled. In one embodiment, after updating the read start-stop address and the store start-stop address, the method further includes: the control data interface is enabled.
In order to avoid memory overflow, the remaining space of the memory in the FPGA verification platform may be counted in real time, and if the remaining space is smaller than a preset threshold, it indicates that the memory is about to be fully written. When the stored data frame in the memory is read according to the read start-stop address, the read start-stop address and the storage start-stop address are updated, and then the data interface can be controlled to be enabled.
After the processor in the FPGA verification platform processes the stored data frame in the memory in time, the read start-stop address and the storage start-stop address can be updated in time, so that convenience is provided for writing in the subsequent data frame. The Memory may be a RAM (Random Access Memory).
It can be seen that, in the embodiment of the present application, after receiving a data frame to be processed by using at least one data interface, a data frame memory is first stored according to a storage start-stop address, where the stored data frame may be valid or invalid. And subsequently, when a new data frame is received by using the data interface, the new data frame is stored into the same memory in an overlay manner according to the storage starting and stopping address, so that the invalid data frame stored in the memory is overlaid. And the method and the device count the residual space of the memory in real time, if the residual space is smaller than a preset threshold value, the read start-stop address and the storage start-stop address are updated after the stored data frame in the memory is read according to the read start-stop address, and then the new data frame is stored in a covering mode according to the new storage start-stop address, so that the utilization rate of the storage space can be improved. The storage starting and stopping address and the reading starting and stopping address are utilized to effectively manage the same storage space, the utilization rate of the storage is improved, the storage space can be saved during storage, and after the data in the storage starting and stopping address is read, the storage starting and stopping address can be updated in time so that the new data frame can be stored in an overlaying mode when the new data frame is stored next time, and therefore the performance of the FPGA verification platform can be improved. In addition, a plurality of levels of caches do not need to be arranged in the FPGA verification platform, and the implementation can be realized by using one cache space. The hardware circuit layout space of the FPGA verification platform is saved by using one cache space, and convenience is brought to design and implementation of the FPGA verification platform.
The embodiment of the application discloses a data processing scheme applied to an FPGA verification platform, and a frame schematic diagram of the scheme is shown in FIG. 3.
Fig. 3 only illustrates one data channel (corresponding to one data interface), and a matching check module, a storage address maintenance module, and a flow control management module may be configured on the data channel, and these modules may directly perform data interaction with the processor.
Of course, a plurality of data channels may also be provided, and a matching check module, a storage address maintenance module, and a flow control management module may be configured on each data channel. Or a plurality of data channels can share the matching check module, the storage address maintenance module and the flow control management module.
The matching check module, the storage address maintenance module and the flow control management module can be packaged into a reusable whole so as to design and realize an FPGA verification platform.
Specifically, the matching and checking module performs characteristic value matching and CRC checking on the received data frame in real time, and the matching and checking result directly controls the storage process of the data frame.
The storage address maintenance module maintains the storage start-stop address and the reading start-stop address of the RAM in the FPGA verification platform in real time, and can manage the storage space of the memory.
The flow control management module can calculate the stored data volume, the space allowance and other information according to the storage starting and stopping address and the reading starting and stopping address, and determines whether to generate interruption or not according to the information so as to control the data transmission flow. Matching rules, storage thresholds, timer interrupt thresholds, data reception enables, etc. may also be configured.
The storage module (namely the RAM memory) is the only storage space in the FPGA verification platform, is a true dual-port RAM, supports asynchronous read-write clock, and has flexible configuration of data bit width and total capacity of the memory along with the bus characteristics and the application environment in the FPGA verification platform.
Referring to fig. 4, the specific process of performing data processing based on the above framework includes:
after the data interface receives the data frame, the data frame is transmitted to the matching checking module, the storage module and the storage address maintenance module, so that the matching checking module, the storage module and the storage address maintenance module can work in parallel as far as possible.
The storage address maintenance module realizes the control of the storage space of the memory by maintaining the storage start-stop address. Initially, the start-stop address (including the start address stt _ addr and the end address end _ addr) is stored as 0, and after receiving the data frame, the data frame is temporarily stored regardless of whether the data frame is valid or not. When the storage is finished, the last RAM _ addr (the RAM storage address in the RAM memory) of the stored data frame is acquired as end _ addr. At this time, if the memory address maintenance module receives a signal that the data frame is valid (the signal is output by the matching check module), the stt _ addr value is updated to end _ addr +1, so as to obtain an updated start-stop address. If the storage address maintenance module receives the signal that the data frame is invalid, stt _ addr and end _ addr are kept unchanged, so that when a new data frame is received, the data frame is stored from the original stt _ addr, and the invalid data frame can be covered. The data frame is received, processed and buffered for standby in the same storage space. Each update of the store start-stop address marks the completion of an entire frame of storage of a valid data frame.
In order to ensure the integrity and accuracy of data frame storage, the flow control management module calculates the space margin (free _ len) of the memory in real time, compares the space margin with a margin threshold (free _ thrhd, which can be set as the maximum frame length of a data frame), and when the free _ len is less than or equal to the margin threshold, the data interface is prohibited from receiving data again after the current frame storage is finished until the free _ len is greater than the margin threshold. If free _ len is greater than the margin threshold, an overflow risk alarm is generated to indicate that there is a risk of frame loss.
At this time, the processor in the FPGA verification platform can be controlled to read and process the data in the memory in time to make up the storage space of the memory. Specifically, the following two data reading mechanisms can be adopted: firstly, the processor reads data in the memory at regular time, and the specific interval time can be set according to actual application; and secondly, configuring a storage threshold (ram _ thrhd), and generating an interrupt to prompt the processor to read the stored data in the memory when the stored data amount in the memory is larger than the storage threshold. Before each time the processor reads data, it first determines the total length (data _ len) of the stored data frame in the memory and reads the data according to the total length. The length of each stored data frame is fixed, so that after the total length of the stored data frames is determined, the number of the data frames required to be read can be calculated according to the total length, and the data frames can be read one by one. After the processor reads and processes the stored data in the memory, the processor can control the data interface to continue receiving data.
It should be noted that, in the process of the processor reading the stored data in the memory, the read start-stop address needs to be updated accordingly. Specifically, when the processor reads data periodically or a memory threshold interrupt occurs, the processor first determines the total length of the stored data frame. Specifically, the read start address (ram _ stt _ addr) is recorded as the start position of the first data frame to be currently read, the read end address (ram _ end _ addr) is the end position of the last data frame that is currently stored, and according to the deviation between ram _ stt _ addr and ram _ end _ addr, the total length of the stored data frame, that is, the total length of data _ len that can be read this time can be calculated (the address cycle condition of the storage unit needs to be considered, and the calculation mode is selected according to the binary size). Then, the ram _ stt _ addr value can be incremented along with the data reading of the processor, or updated to the temporarily stored original ram _ end _ addr value after the reading is finished. Thus, the processor reads the previously stored frame data, shifts ram _ stt _ addr accordingly, waits for the next data reading as the data is received, and so on. The deviation between the occupied address ram _ addr and ram _ stt _ addr when the current data frame is stored can be used for calculating the real-time space occupation (the address cycle condition of the storage unit needs to be considered, and the calculation mode is selected according to the binary value), and the space margin free _ len can be obtained by subtracting the value from the total capacity of the memory.
Since the RAM address is recycled, the address cycle of the memory cell needs to be considered when calculating the length of the stored data frame. For example: the depth of the RAM is 8192 (the total address number), the address range is 0-8191, and the next address circulates to 0 after the data is stored in 8191. Therefore, when calculating data _ len, the sizes of the read start address and the read end address need to be considered.
Specifically, before storing the received data frame, the data frame may be further encapsulated according to a preset format, in the encapsulation process, redundant data in the original received data frame may be discarded, and different received data frames having the same characteristic value may be further fused and then encapsulated in one frame, so as to improve the effective data ratio in one frame.
In this embodiment, the FPGA verification platform can also be used as a verification platform of an asic (application Specific Integrated circuit). The processor may be a BOOM processor, which may be used in conjunction with the RISC-V instruction set, the BSD (Berkeley Software distribution) protocol, and the like.
It can be seen that, in this embodiment, the storage process of data can be managed based on one storage space, processes such as matching, checking, storing, flow control, data statistics and the like of data frames are implemented, and different processes can also be executed in parallel based on actual situations. Meanwhile, the method also supports channel expansion, has high real-time performance, occupies less resources, has a simple use mode, and is suitable for complex data interfaces with large data volume.
In the following, a data processing apparatus provided in an embodiment of the present application is introduced, and a data processing apparatus described below and a data processing method described above may be referred to each other.
Referring to fig. 5, an embodiment of the present application discloses a data processing apparatus, which is applied to an FPGA verification platform, and includes:
a receiving module 501, configured to receive a data frame to be processed by using at least one data interface;
a storage module 502, configured to store the data frame to a memory in the FPGA verification platform according to the storage start-stop address;
the matching check module 503 is configured to perform matching check on the data frame, and if the data frame matching check fails, the storage start-stop address is reserved, so that when a new data frame is received by using the data interface, the new data frame is stored in the memory in an overlay manner according to the storage start-stop address;
the management module 504 is configured to count the remaining space of the memory in real time, and if the remaining space is smaller than a preset threshold, update the read start-stop address and the storage start-stop address after reading the stored data frame in the memory according to the read start-stop address.
In a specific embodiment, the matching check module is specifically configured to:
performing characteristic value matching on the data frame according to a preset matching rule, and performing CRC (cyclic redundancy check) on the data frame; if the characteristic value matching passes and the CRC passes, determining that the data frame matching passes; otherwise, determining that the data frame matching check is not passed.
In a specific embodiment, the method further comprises the following steps:
and the updating module is used for updating the storage starting and stopping address to obtain an updated starting and stopping address if the data frame matching check is passed, so that the new data frame is stored according to the updated starting and stopping address when the new data frame is received by using the data interface.
In a specific embodiment, the update module is specifically configured to:
and calculating the updating start-stop address according to the storage start-stop address and the address length occupied by the data frame.
In a specific embodiment, the method further comprises the following steps:
and the de-enabling module is used for controlling the de-enabling of the data interface.
In a specific embodiment, the method further comprises the following steps:
and the enabling module is used for controlling the enabling of the data interface.
In a specific embodiment, the method further comprises the following steps:
the bit width conversion module is used for performing bit width conversion on the data frame so as to adapt to the bus bit width in the FPGA verification platform;
and the encapsulation module is used for encapsulating the data frame according to a preset format.
For more specific working processes of each module and unit in this embodiment, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not described here again.
Therefore, the embodiment provides a data processing device, which can cover the stored invalid data frame, thereby saving the storage space and resources and improving the performance of the FPGA verification platform. And a multi-level cache is not required to be arranged in the FPGA verification platform, and the method can be realized by using one cache space. The hardware circuit layout space of the FPGA verification platform is saved by using one cache space, and convenience is brought to design and implementation of the FPGA verification platform.
In the following, a data processing device provided in an embodiment of the present application is introduced, and a data processing device described below and a data processing method and apparatus described above may be referred to each other.
Referring to fig. 6, an embodiment of the present application discloses a data processing apparatus, including:
a memory 601 for storing a computer program;
a processor 602 for executing the computer program to implement the method disclosed in any of the embodiments above.
In the following, a readable storage medium provided by an embodiment of the present application is introduced, and a readable storage medium described below and a data processing method, apparatus, and device described above may be referred to each other.
A readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the data processing method disclosed in the foregoing embodiment. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which are not described herein again.
References to "first," "second," "third," "fourth," etc. (if any) in this application are intended to distinguish between similar elements and not necessarily to describe a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, or apparatus.
It should be noted that the descriptions in this application referring to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of readable storage medium known in the art.
The principle and the embodiment of the present application are explained by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (8)
1. A data processing method is applied to an FPGA verification platform and comprises the following steps:
receiving a data frame to be processed by utilizing at least one data interface;
storing the data frame to a memory in the FPGA verification platform according to a storage starting and stopping address;
performing matching check on the data frame, if the data frame matching check is not passed, reserving the storage start-stop address so as to store a new data frame to the memory in an overlay manner according to the storage start-stop address when the data interface is used to receive the new data frame;
counting the residual space of the memory in real time, and if the residual space is smaller than a preset threshold, updating the read start-stop address and the storage start-stop address after reading the stored data frame in the memory according to the read start-stop address;
wherein, still include:
if the data frame matching check is passed, updating the storage starting and stopping address to obtain an updated starting and stopping address, so that when the new data frame is received by using the data interface, the new data frame is stored according to the updated starting and stopping address;
wherein the updating the storage start-stop address to obtain an updated start-stop address includes:
and calculating the updating start-stop address according to the storage start-stop address and the address length occupied by the data frame.
2. The data processing method of claim 1, wherein the performing the match check on the data frame comprises:
performing characteristic value matching on the data frame according to a preset matching rule, and performing CRC (cyclic redundancy check) on the data frame;
if the characteristic value matches and the CRC passes, determining that the data frame matches and checks; otherwise, determining that the data frame matching check is not passed.
3. The data processing method of claim 1, wherein before reading the stored data frame in the memory according to the read start-stop address, further comprising:
controlling the data interface to be disabled.
4. The data processing method according to claim 3, wherein after the updating the read start-stop address and the store start-stop address, further comprising:
controlling the data interface to be enabled.
5. The data processing method according to claim 3, wherein before storing the data frame to the memory in the FPGA verification platform according to the storage start-stop address, the method further comprises:
performing bit width conversion on the data frame to adapt to the bus bit width in the FPGA verification platform;
and packaging the data frame according to a preset format.
6. A data processing device is applied to an FPGA verification platform and comprises:
the receiving module is used for receiving a data frame to be processed by utilizing at least one data interface;
the storage module is used for storing the data frame to a memory in the FPGA verification platform according to the storage starting and stopping address;
the matching check module is used for carrying out matching check on the data frame, and if the matching check of the data frame fails, the storage starting and ending address is reserved so that when a new data frame is received by using the data interface, the new data frame is stored to the memory in an overlapping manner according to the storage starting and ending address;
the management module is used for counting the residual space of the memory in real time, and if the residual space is smaller than a preset threshold, the management module updates the read start-stop address and the storage start-stop address after reading the stored data frame in the memory according to the read start-stop address;
wherein, still include:
the updating module is used for updating the storage starting and stopping address to obtain an updated starting and stopping address if the data frame matching check is passed, so that the new data frame is stored according to the updated starting and stopping address when the new data frame is received by using the data interface;
wherein, the update module is specifically configured to:
and calculating the updating start-stop address according to the storage start-stop address and the address length occupied by the data frame.
7. A data processing apparatus, characterized by comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the data processing method of any one of claims 1 to 5.
8. A readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the data processing method of any one of claims 1 to 5.
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