WO2014115289A1

WO2014115289A1 - Programmable device and electronic syst em device

Info

Publication number: WO2014115289A1
Application number: PCT/JP2013/051517
Authority: WO
Inventors: 鳥羽　忠信; 健一新保; 長崎　文彦; 学牧野; 則貴小杉
Original assignee: 株式会社日立製作所
Priority date: 2013-01-25
Filing date: 2013-01-25
Publication date: 2014-07-31

Abstract

The purpose of the present invention is to provide a programmable device in which the time for detecting a soft error is shortened and reliability is improv ed, and an electronic system device using the same. According to the pre sent invention, a portion in which an error occurred is identified by an error detection signal from a user logic and then converted into a physical address in configuration memory, and only such a portion affected by this operation inside the configuration memory of the programmable de vice to be used in an electronic system product is checked for error. Therefor e, the time for detecting a configuration memory error can be shortened.

Description

Programmable device and electronic system apparatus

The present invention relates to a programmable device and an electronic system apparatus.

As background art in this technical field, there is JP 2005-505827 A (Patent Document 1). In this publication, "An error detection circuit is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module, where checksum calculation is performed. In one embodiment, the check The sum is compared to an expected value, which is pre-computed by a checksum on the data before or during programming into the programmable logic resource.In another embodiment, the expected value is calculated during the checksum calculation. An output is formed indicating whether an error has been detected according to the relationship between the checksum and the expected value, or the numerical value of the checksum itself, which is transmitted to an output terminal accessible by the user logic. It is described.
There is also JP-A-2007-293856 (Patent Document 2). In this publication, “a method for detecting an error in a configuration memory of a programmable device, reading configuration memory data from the configuration memory, and determining whether an error has occurred in the configuration memory data; In response to determining that an error has occurred, reading sensitivity data corresponding to the configuration data that is in error, and analyzing the sensitivity data to determine whether the error can be ignored And initiating a repair activity if the error cannot be ignored, and ignoring the error by not initiating the repair activity if the error can be ignored. Method. "
Moreover, there exists patent 4456552 (patent document 3). In this publication, “a logic integrated circuit having a dynamic replacement function for reconfiguring a circuit that can be reconfigured by a program in response to detection of an error in the fixed circuit into a function of the fixed circuit, each of which includes a plurality of functional circuits. For each of the plurality of functional blocks, a programmable bus that connects between the plurality of fixed circuits divided into blocks, and a plurality of functional block groups in which the functional circuit blocks extracted from the different fixed circuits are grouped A plurality of reconfigurable circuits provided, a memory for storing reconfiguration data of the functional circuit block, and a functional circuit block in which the error is detected in response to detection of an error in the functional circuit block The functional circuit block in which the reconfigurable circuit corresponding to the functional block group is specified and the error is detected from the memory A control circuit that reads the reconfiguration data and reconfigures the identified reconfigurable circuit into the functional circuit block in which the error is detected, and the functional circuit block in which the error is detected is read from the programmable bus A logic integrated circuit having a dynamic replacement function, characterized in that it disconnects and connects the reconfigured circuit to the programmable bus. "

JP 2005-505827 Gazette JP 2007-293856 A Japanese Patent No. 4456552

With the miniaturization of semiconductor devices, the problem of soft errors caused by environmental radiation (cosmic neutrons and α-rays on the ground) and the like has become apparent especially in SRAMs, logic gates, clock systems, and the like. When neutrons with extremely high energy enter the nuclei that make up the device, nucleons (neutrons and protons) in the nucleus repeatedly collide, and nucleons with particularly high energy are emitted outside the nucleus. When the nucleon is unable to have enough kinetic energy to jump out of the nucleus, light particles such as protons, neutrons, deuterons, and alpha particles evaporate from the residual nuclei in the excited state. However, because of the counter-attack energy, all of these secondary particles will fly in the distance device corresponding to the range.

When alpha ions generated from radioactive isotopes contained in a semiconductor package or the like or secondary ions having charges generated as a result of a nuclear reaction pass through the depletion layer of the storage node in the “high” state of the SRAM, electrons are transferred to the nodes. The absorbed holes flow in the opposite direction, and charges are collected in the storage node by a funneling mechanism in which the charge collection region extends along the track of ions. When charges exceeding the critical charge amount are collected, the “high” state changes to the “low” state, and a soft error occurs.

This is a typical mechanism that has been considered as a mechanism of environmental radiation soft error, and is also referred to as SEU (Single Event Upset). A case where a plurality of cells simultaneously cause an error in the SEU of the memory device is called MCU (Multi Cell Upset) and is distinguished from SBU (Single Bit Upset: single bit error). When the MCU occurs in the same word, it is called MBU (Multiple Bit Upset), and normal ECC (Error Correction Code) is difficult to repair.

Unlike hard errors (hardware fixed failures), soft errors including SEU are updated to new data even after an error occurs, and return to normal by restarting etc. There is also a problem. As described above, the influence of the soft error generated in the logic circuit means that the malfunction of the computer processor, ASIC, control digital circuit, etc. is caused, and there is a concern that it may cause malfunction of the electronic system. The

In recent years, programmable devices are frequently used as control logic circuits for various electronic system devices, and the use of FPGA (Field Programmable Gate Array) is increasing among programmable devices. The FPGA stores logic circuit information in a memory inside the device (hereinafter referred to as a configuration memory) to construct an arithmetic circuit and a control circuit. The data stored in the memory is destroyed by a soft error. It is becoming a problem that electronic system devices can malfunction. In general, it is considered that the electronic system is not affected by malfunction, but this causes an increase in power consumption, development, verification man-hours, cost, and the like.

Patent Documents 1 to 3 can be cited as countermeasures against data inversion of the FPGA configuration memory.

In the conventional techniques described in Patent Documents 1 to 3, an environmental radiation error detection method for a configuration memory (a memory for storing circuit information) of a programmable device is a method in which circuit data stored in a configuration memory is a fixed-length data frame. The error is detected by rotating each data frame. However, in this method, in a programmable device whose capacity has been increased, the time required to circulate the entire device becomes longer, and the time until error detection becomes longer. In addition, if the time to error detection is long, it is necessary to completely stop the device, reboot, etc., and the burden on the recovery process in the system product equipped with the programmable device is large, which may impair reliability. The countermeasure cost may increase. In communication devices, the system is mainly duplicated, and the switching time is generally required to be within several tens of ms. It takes 100 ms or more to circulate the configuration memory, and this time is expected to increase as the capacity increases further in the future.

Therefore, it is necessary to shorten the error detection time due to environmental radiation in the configuration memory, and to shorten the device stop and recovery time. In addition to error detection, it is required to correct and recover errors in a short time within the programmable device by providing correction means.

In view of the above, an object of the present invention is to provide a programmable device that shortens the soft error detection time and improves the reliability, and an electronic system apparatus using the programmable device.

In order to solve the above problems, for example, the configuration described in the claims is adopted.
The present application includes a plurality of means for solving the above problems. For example, a programmable device having a configuration memory, which directly reads and writes the configuration memory, and an error in user logic. An error detection signal output means for detecting an error detection signal, an error detection signal output means for outputting an error detection signal, an error part specifying means for acquiring address information for identifying an error occurrence part from the error detection signal output from the error detection signal output means, Storage means for storing address information indicating a physical position in the storage memory, and address information for identifying the error occurrence part specified by the error part specifying means, based on the address information stored in the storage means, Error location on the configuration memory Based on the physical address conversion means for converting the address information indicating the physical position and the physical address of the error occurrence part converted by the physical address conversion unit, the error determination of the data in the configuration memory corresponding to the physical address is performed. And an error determination means.

According to the present invention, it is possible to provide a programmable device having a reduced soft error detection time and improved reliability, and an electronic system apparatus using the programmable device.

It is a lineblock diagram of the programmable device concerning a 1st embodiment of the present invention. It is the figure which showed the data structure of the configuration memory of the programmable device which concerns on the 1st Embodiment of this invention. It is the figure which showed the data structural example in the address storage part in the programmable device which concerns on the 1st Embodiment of this invention. It is a figure of the structural example of the programmable device provided with the error correction means which concerns on 3rd Embodiment by this invention. It is an example of the screen which outputs the setting screen for control of an electronic device carrying the programmable device concerning a 1st embodiment by the present invention, and an error detection result. It is the figure which showed the other example of the error detection unit in the programmable device which concerns on the 1st Embodiment of this invention. It is a structural example of the circuit for error detection in the programmable device which concerns on 2nd Embodiment by this invention. It is a block diagram of LUT in FIG. The restoration processing flow of the electronic system apparatus carrying the programmable device which concerns on this invention is shown. The control method of the recovery process by the duplex system of the communication apparatus carrying the programmable device which concerns on this invention is shown.

Hereinafter, examples will be described with reference to the drawings.

An embodiment of a programmable device and an electronic system apparatus using the same according to the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a programmable device in a soft error tolerance circuit caused by environmental radiation or the like of the present invention. The programmable device 10 of this embodiment includes a configuration memory 7 having a function block 8 that is a circuit for realizing a desired function as user logic, and a configuration control unit that controls access to data in the configuration memory 7. The configuration control unit 1 reads and writes data in the configuration memory 7 and a CRC (for determining whether there is an error in the data in the configuration memory 7 Cyclic Redundancy Code) determination unit 3, error detection signal output means for detecting an error occurring in function block 8 and outputting an error detection signal, and error detection signals (ER 1, ER 2, ER 3. ..ERn Based on the error flag encoder 4 that converts the functional block from which the error detection signal has been output into address information, an address storage unit 6 that stores physical address information in the configuration memory 7, and the error flag encoder 4 The error block output from the error flag encoder 4, that is, the function block that detected the error from the address information indicating the error part output from the address information and the physical address information in the configuration memory stored in the address storage unit 6. And an address conversion unit 5 that converts an address indicating a functional block that detects the error into a physical address on the configuration memory 7.

In this embodiment, the configuration control unit 1 is provided in a part of the configuration memory 7. However, it may be configured as a dedicated circuit other than the configuration memory 7. In addition, although CRC is used for the error detection of the CRC determination part 3 mentioned above, the method for detecting an error is not limited to CRC.

In the operation of the configuration of the programmable device 10 shown in FIG. 1, the error detection signal detected by the functional block 8 is input to the error flag encoder 4, and the error output from the error flag encoder 4 is detected by the address conversion unit 5. The functional block information is converted into a physical address on the configuration memory 7 and passed to the configuration memory R / W control unit 2.

The configuration memory R / W control unit 2 reads the circuit information data at the address in the configuration memory 7 and sends it to the CRC determination unit 3, where it checks whether there is an abnormality in the data in the configuration memory 7 If there is an error, an error signal is output outside the programmable device.

Here, there is a method in which the physical address representing the storage location of the configuration memory 7 is represented by the intersection of the number of rows and the number of columns on the horizontal axis (Col) and the vertical axis (Row). However, the way of expressing the physical address is not limited to this.

FIG. 2 shows a configuration example of circuit information data in the configuration memory 7 in the configuration shown in FIG. Circuit information data is stored in the configuration memory 7, and the circuit information stored therein is a logical expression representing a function as a logical table. For example, in the case of a 4-input 1-output logic table, 16 types of logic states corresponding to 4 inputs are stored, and a logical expression for the 4-input bit string is created.

In FIG. 2, a plurality of such logic tables are combined to form a user logic data frame 12. This data frame 12 is composed of a user logic data area 13 and a cyclic redundancy code (CRC) 14 which is a redundant bit for error detection. By sequentially reading the data frame 12 and determining whether or not there is an error by the CRC code. An error in the configuration memory 7 can be detected. Thereby, it can be detected that the data bits in the data frame 12 are inverted by the environmental radiation. In the present invention, error detection signal output means is provided so that an error occurring in the functional block 8 can be detected and an error detection signal can be output as described above.

FIG. 3 shows an example of the data structure of the address storage unit 6. The data in the left end column is a code indicating an error part that is input by the error detection signal and output by the error flag encoder unit 4. The data on the right side indicates the address of the configuration memory 7 corresponding to the code indicating the error part. In this example, the addresses of the corresponding configuration memory 7 are represented by the horizontal axis (Col) and the vertical axis (Row), and are designated as the start address and end address of the target part.

In this embodiment, the range of the physical error part is represented by a rectangle, and the start address and end address indicate diagonal vertex addresses. For example, the code “0001” in FIG. 3 is represented by (R _S1 , C _S1 ) as a start address and (R _E1 , C _E1 ) as an end address. In addition, even when there are a plurality of error detection signals, coding for each combination makes it possible to deal with a physical error part.

In the example of FIG. 3, the code “0111” represents a combination of the error detection signals (E1) and (E3), and the start address (R _S4 , C _S4 ), the end address (R _E4 , C _E4 ), and (R _S5 ). , C _S5 ) (R _E5 , C _E5 ).

FIG. 5 shows an example of an operation monitor result screen in an electronic system device equipped with a programmable device according to this embodiment. An operation monitor window 42 is displayed on the display screen 41, and an operation monitor result of the apparatus is displayed therein.

The contents of the operation monitor are configured by a window 43 (next to the control FPGA error in the figure) that displays error detection from the programmable device and a window 44 (next to the error occurrence address in the figure) showing the physical address where the error occurred. To do. In addition, although the example which displayed the physical address as an error occurrence address is shown, you may display the name of a functional block, the kind of error detection signal, or either.

FIG. 6 shows another configuration example of the functional block 8. In the example shown in FIG. 2, the function block 8 is defined as a rectangle, but in this configuration example, circuit information is stored in a free shape as shown in FIG. 6 instead of a simple rectangle.

In the example shown in FIG. 2, the delimiter is configured with fixed-length data called frame data. However, in the example shown in FIG. 6, the delimitation is realized with variable-length data without the delimitation of frame data. The fixed-length data frame needs to be collected together with frame data that is not used because it is stored in a rectangular functional block, and it may be difficult to efficiently store circuit information data.

Therefore, the user logic data area 13 that does not store user logic information is also subject to determination of the presence or absence of errors due to environmental radiation. Even if an error is detected in the unstored user logic data area 13, it will be determined as an error although there is no functional problem, and the error rate as a programmable device will be raised. Become.

By using variable-length data, the amount of information for managing the physical address of the functional block increases. However, as described above, there is no need to add a data frame that does not contain user logic information effective for making a rectangle. In addition, it is possible to improve the mounting efficiency in the configuration memory for storing circuit information and to suppress an increase in error rate due to the data frame 12 not storing user logic information.

The programmable device according to the present embodiment can be applied to various electronic system apparatuses, for example, a communication apparatus.
The communication device inputs communication packet data, selects a destination according to destination data added to the packet data, a communication control unit, a diagnosis unit for diagnosing whether the communication control unit is operating normally, It is composed of a control unit that controls unit operations such as operation start and reset of the communication control unit and diagnostic unit, and initialization of installed processors and programmable devices. The programmable device is mounted on all the units described above.

When an error detection signal is output from the error detection circuit network 64 according to this embodiment after the electronic system apparatus using the programmable device of this embodiment is operated, it is confirmed that a part of the data in the configuration memory has changed due to environmental radiation. Regardless of whether an error occurs in the functional operation of the user logic, configuration memory error correction processing, FPGA reset processing, packet discard before and after error detection by device firmware, and recovery processing by retransmission are performed. Can be restarted.

According to this embodiment, information changes due to environmental radiation can be monitored in real time, and in the case of a communication device, the time until detection and recovery can be greatly shortened, and the number of discarded packets can be reduced. Therefore, the influence of the service stop of the communication device can be reduced.

As described above, according to the present invention, it is possible to reduce the detection time of a configuration memory error by performing an error check only on a part that affects the operation in the configuration memory of the programmable device used in the electronic system product.

Also, a product equipped with a programmable device to which the present invention is applied can detect a configuration memory error at high speed, shorten the recovery time of the apparatus, and achieve high reliability and improved availability. As a result, it is possible to provide a programmable device in which the soft error detection time is shortened and the reliability is improved, and an electronic system apparatus using the programmable device.

FIG. 7 is a configuration diagram of a programmable device according to the second embodiment of the present invention. The programmable device of the present embodiment is an example in which a circuit for detecting an error is incorporated instead of detecting an error from the function block 8 and outputting a detection signal as an error detection signal output means.

The programmable device 60 includes a configuration memory 7 that stores circuit information for realizing a desired function, and a configuration control unit 61 that controls access to data in the configuration memory 7.

The configuration control unit 61 reads and writes data in the configuration memory 7, and collects signals from the error detection circuit network 64 and the error detection circuit network 64 in the configuration memory 7. , An error detection signal transmission unit 62 that transmits an error signal to the configuration control unit 61, a mesh information collection unit 65 that collects and encodes the error signal from the error detection signal transmission unit 62, and an encoded error occurrence The address conversion unit 5 is searched from the address storage unit 6 that stores a correspondence table with physical addresses based on the part information and converts it into a physical address.

FIG. 8 shows a detailed circuit example of the programmable device according to the second embodiment. FIG. 8 shows the structure of an FPGA which is a kind of programmable device. The error detection network 64 shown in FIG. 7 includes a storage element such as a flip-flop and a logic table that stores circuit information data. Here, a lookup table (LUT) 71, which is an example of the configuration of the logical table, is provided, and a flip-flop (F / F) 72 is connected to the output thereof. A logic block constituted by the LUT 71 and the F / F 72 is arranged on the tile.

The circuit information of the user for realizing the desired function is also stored on the logic block arranged on this tile to configure the circuit. The error detection circuit network 64 in this embodiment is also realized by using a part of this logic block. That is, the user circuit information and the error detection circuit network 64 are arranged so as to be mixed on the logic block.

The error detection of the present embodiment utilizes the fact that data inversion caused by environmental radiation or the like becomes an MCU (Multi Cell Upset) that covers a plurality of data bits. For example, a single neutron collides with a logic block storing a user circuit, and the influence spreads to a plurality of bits, thereby affecting the error detection circuit network 64 arranged in the vicinity, and the result is an error. The detection signal sending unit 62 reports the error information to the error collecting unit 65.

The error detection circuit network 64 is configured by a plurality of circuit networks so that it can detect in which part an error has occurred. Therefore, it can also be determined whether or not the error position is an area in which user logic information is stored, and an error check can be performed only on the area in which user logic information is stored.

As described above, according to the present invention, it is possible to reduce the detection time of a configuration memory error by performing an error check only on a part that affects the operation in the configuration memory of the programmable device used in the electronic system product. In addition, a product equipped with a programmable device to which the present invention is applied can detect a configuration memory error at high speed, shorten the recovery time of the apparatus, and achieve high reliability and improved availability. As a result, it is possible to provide a programmable device in which the soft error detection time is shortened and the reliability is improved, and an electronic system apparatus using the programmable device.

FIG. 4 shows an embodiment having a configuration for correcting circuit information data of an error occurrence part after receiving an error detection signal.

The configuration control unit 21 includes a redundant bit generation unit 23, a redundant bit storage unit 24, and an error check correction unit 28 in addition to the configuration of the configuration control unit 1 according to the first embodiment illustrated in FIG.

The configuration control unit 21 of this embodiment operates as follows. When an error occurs in the configuration memory 7 (not shown) and the error detection signal ER1 or the like is input to the error flag encoder 4, the error flag encoder 4 converts it into address information for identifying the error part. Is output to the unit 5.

Then, from the address information indicating the error part output from the error flag encoder 4 in the address conversion unit 5 and the physical address information in the configuration memory stored in the address storage unit 6, the error detection part in the functional block That is, it is converted into an address indicating an error part output from the error flag encoder 4, and this physical address 27 is output to the configuration memory R / W control unit 2.

The configuration memory R / W control unit 2 reads circuit information data from the configuration memory 7 based on the address information 27 output from the address conversion unit 5, and sends a physical address 32 indicating an error part to the error check correction unit 28.

The error check correction unit 28 searches the redundant bit storage unit 24 based on the physical address 32, and reads the redundant bit corresponding to the error check target part. In the present embodiment, the redundant bits in the redundant bit storage unit 24 are composed of a correction redundant bit location tag 25 for searching based on a physical address and redundant bit data 26.

The error check correction unit 28 checks the presence / absence of an error based on the redundant bit data 26 that is circuit information data read from the configuration memory 7, and if there is an error, sends a signal 31 to the configuration memory R / W control unit 2, Correct using redundant bits.

However, the code correction method of the error check correction unit 28 may be any method such as an error correcting code (ECC) code, a BCH (Bose-Chauduri-Hocquenhem) code, or a Reed-Solomon code. For example, the CRC code corresponding to the data frame 12 shown in FIG. In this case, the user frame data area 13 alone may be included in the data frame 12.

The error check correction unit 28 corrects the error and outputs an error signal to the outside as an error signal. For example, the error signal is output to an error processing unit or the like of the electronic system device on which the programmable device according to the present embodiment is mounted, and the process corresponding to the error is output to the display device of the electronic system device.

Also, an error signal is output if correction is not possible. A plurality of types of error signals may be provided, and a signal indicating the presence / absence of an error, a signal indicating that the error has been corrected, and a signal indicating that the error cannot be corrected may be provided.

Redundant bits stored in the redundant bit storage unit 24 are generated and stored by the redundant bit generation unit 23 when circuit information data is written in the configuration memory 7.
Note that when it is determined that there is an error after the error check correction unit 28 determines whether there is an error, the circuit information data may be read from the external ROM and written back to the configuration memory 7 for correction.

In this case, the redundant bit generation unit 23 and the redundant bit storage unit 24 are not necessary. In the present embodiment, the error determination is made based on the error detection signal from the configuration memory 7, but the present invention is not limited to this. For example, the structure described in the second embodiment may be adopted.

FIG. 9 shows an example of a control method when an error occurs in the electronic system apparatus equipped with the programmable device according to this embodiment. In the present embodiment, a communication device will be described as an example of an electronic system device. FIG. 9 shows an example in which an FPGA is used as a programmable device.

The communication device inputs communication packet data, selects a destination according to destination data added to the packet data, a communication control unit, a diagnosis unit for diagnosing whether the communication control unit is operating normally, It is composed of a control unit that controls unit operations such as operation start and reset of the communication control unit and diagnostic unit, and initialization of installed processors and programmable devices. The programmable device is mounted on all the units described above.

The control method of FIG. 9 shows an example in which the processes of S83 and S86 are performed by the programmable device mounted on the communication control unit, S82 and S85 are processed by the diagnostic unit, and S84, S87 and S88 are processed by the control unit. ing.

After the operation of the electronic system apparatus using the programmable device of this embodiment (S81), the configuration memory error signal from the programmable device according to this embodiment is monitored (S82). When an error is detected (S83), a temporary stop process is performed on the in-device unit related to the FPGA that has generated the error in the device (S84). The error information is displayed on the operation monitor screen. At this time, it is also possible to output to a log file. (S85). Thereafter, error correction processing of the configuration memory (S86), reset processing of the FPGA (S87), packet discarding before and after error detection by the firmware of the device, recovery processing by retransmission are performed (S88), and the system is restarted (S89).

When the communication device is configured using the programmable device according to the present embodiment, it is possible to reduce the time for detecting a configuration memory error that has conventionally spent much of the main recovery processing time, and it is possible to reduce the device recovery processing time.

For example, in the case of a communication apparatus having a standby system as shown in FIG. 10, when an execution system, usually called system 1, stops due to some event, it is necessary to switch the system in a time that does not affect the user who uses the apparatus. In this case, if switching to the second system is performed in a short time, it is possible to prevent the user who uses the apparatus from being affected.

In addition, a failure of the standby system that is normally stopped may occur immediately after switching, and in the case of a so-called soft error failure such as a failure due to environmental radiation, the system 1 is restored within the system switching time as in the present invention. Thus, preparing for the occurrence of a failure in the standby system is effective in a device that requires reliability and availability such as a communication device.

In addition, for the purpose of reducing power consumption, the standby system clock may be stopped in a state where it can be operated immediately, such as by stopping the standby system. In this case, the standby system programmable device executes from standby. It is conceivable that the data inversion of the configuration memory in the programmable device is detected immediately after the mode is shifted, and in this case, the recovery can be performed within the time allowed as the system switching time.

As described above, according to the present invention, the error detection time of the programmable device can be shortened, and the recovery time of the apparatus can be shortened. In addition, according to the present embodiment, it is possible to shorten the detection time of the soft error due to the environmental radiation of the programmable device used in the electronic system product, and to recover the apparatus in a short time, such as communication equipment The reliability of the electronic system apparatus can be improved.

10, 60

Programmable devices

1, 21, 61 Configuration control unit 2 Configuration memory R / W control unit 3 CRC determination unit 4 Error flag encoder 5 Address conversion unit 6 Address storage unit 7 Configuration memory 8 Functional block (realization of desired function) User circuit block)
9 Configuration Control Unit 12 on Configuration Memory 12 Data Frame 13 User Logic Data Area 14 Cyclic Redundancy Code (CRC)
23 Redundant bit generation unit 24 Redundant bit storage unit 25 Redundant bit location tag for correction 26 Redundant bit data 27 Read address 28 Error check correction unit 29 Error correction frame address 30 Read / write frame address 31 Error correction frame address 41 Display screen 42 Operation Monitor window 43 Window for displaying error detection 44 Window indicating physical address 51 Vertex address 62 Error detection signal transmission unit 63 FIG. 64 is an enlarged view of a part of the configuration memory. Error detection circuit network 65 Mesh information collection unit 66 Error transmission flip-flop 67 Error detection lookup table (LUT)
71 Look-up table (LUT)
72 Flip-flop (F / F)
73 Circuit Operation Path 91 Electronic System Device (Example of Communication Device)
92 Communication Device Main System 93 Communication Device Backup System 94 Programmable Device Installed in Main System 95 Programmable Device Installed in Backup System

Claims

A programmable device having a configuration memory,
Means for directly reading and writing the configuration memory;
An error detection signal output means for detecting an error in the user logic and outputting an error detection signal;
Error part specifying means for acquiring address information for identifying an error occurrence part by an error detection signal output from the error detection signal output means;
Storage means for storing address information indicating a physical location in the configuration memory;
The address information for identifying the error occurrence part specified by the error part specifying means is converted into address information indicating the physical position of the error occurrence part on the configuration memory based on the address information stored in the storage means. Physical address translation means for
A programmable device comprising: error determination means for performing error determination on data in the configuration memory corresponding to the physical address based on the physical address of the error occurrence part converted by the physical address conversion unit.
The programmable device according to claim 1,
The programmable device is characterized in that the circuit information data of the configuration memory has a configuration in which a cyclic redundancy code is added to each logic data.
A programmable device according to claim 2,
A programmable device comprising: calculation means for sequentially reading logic data of a configuration memory and calculating an error bit using a cyclic redundancy code added to each logic data.
The programmable device according to claim 1,
The error detection signal output means includes an error detection circuit network arranged on a configuration memory, and an error detection signal transmission unit that receives an error signal from the error detection circuit network and transmits an error signal,
The error part specifying means is a mesh information collecting unit that receives an error signal transmitted from the error detection signal transmitting unit,
A programmable device, wherein physical address information of an error part is converted by the physical address conversion unit based on error occurrence part information encoded by the mesh information collection unit.
The programmable device according to any one of claims 1 to 4,
A programmable device comprising error correction means for correcting an error in a portion of the configuration memory in which the error is determined by the error determination means.
The programmable device according to claim 5,
Having storage means for storing circuit information without error;
When an error is determined by the error determination unit, the error correction unit reads out error-free circuit information stored in the storage unit corresponding to the error part, and rewrites and corrects the error part into correct circuit information. A programmable device.
An electronic system device equipped with a programmable device having a configuration memory,
The programmable device is:
Means for directly reading and writing the configuration memory;
When,
Error part specifying means for acquiring address information for identifying an error occurrence part by an error detection signal output from the error detection signal output means;
Storage means for storing address information indicating a physical location in the configuration memory;
The address information for identifying the error occurrence part specified by the error part specifying means is converted into address information indicating the physical position of the error occurrence part on the configuration memory based on the address information stored in the storage means. Physical address translation means for
An electronic system apparatus comprising: an error determination unit configured to determine an error of data in the configuration memory corresponding to the physical address based on the physical address of the error occurrence portion converted by the physical address conversion unit.
The electronic system device according to claim 7,
The circuit information data of the configuration memory has a configuration in which a cyclic redundancy code is added to each logic data.
The electronic system device according to claim 8, comprising:
An electronic system apparatus comprising: calculation means for sequentially reading logic data of a configuration memory and calculating an error bit using a cyclic redundancy code added to each logic data.
The electronic system device according to claim 7,
The error detection signal output means includes an error detection circuit network arranged on a configuration memory, and an error detection signal transmission unit that receives an error signal from the error detection circuit network and transmits an error signal,
The error part specifying means is a mesh information collecting unit for encoding to receive an error signal transmitted from the error detection signal transmitting unit,
An electronic system apparatus, wherein the physical address conversion means converts physical address information of an error part based on error occurrence part information encoded by the mesh information collection unit.
The electronic system device according to any one of claims 7 to 10,
An electronic system apparatus comprising: an error correction unit that corrects an error in a portion of the configuration memory in which the error is determined by the error determination unit.
The electronic system device according to claim 11,
Having storage means for storing circuit information without error;
When an error is determined by the error determination unit, the error correction unit reads out error-free circuit information stored in the storage unit corresponding to the error part, and rewrites and corrects the error part into correct circuit information. Electronic system device.