CN110931074B - Optional bit width error correction and detection circuit for single event upset resistant memory - Google Patents
Optional bit width error correction and detection circuit for single event upset resistant memory Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
Abstract
A selectable bit width error detection and correction circuit for a single event upset resistant memory comprises an error detection and correction coding module and an error detection and correction decoding module; the error correction and detection coding module can perform check code coding operation on input data with the bit width of 11-64, generate 8-bit check codes for performing error correction and detection on the data, and output the 8-bit check codes and the input data to the error correction and detection decoding module; the error correction and detection decoding module is used for decoding and checking the data signal, outputting a one-bit error prompt and an error position when one-bit errors exist in the data signal, correcting the errors and outputting a two-bit error prompt when two-bit errors exist in the data signal. The invention can use less circuit area, realize the check and error correction and detection of 11-64 bit data on the premise of not occupying too much data bit width, realize the improvement of the single-event upset resistance index of the memory by matching with a memory structure resistant to multi-bit single-event upset, and can select to start the error correction and detection functions or only start one of the functions according to the requirements of users, thereby realizing better flexibility.
Description
Technical Field
The invention relates to a selectable bit width error correction and detection circuit for a single event upset resistant memory, in particular to an error correction and detection circuit for performing Hamming code encoding operation on 64-bit data and performing parity check on encoded 72-bit data, and belongs to the field of integrated circuits.
Background
The memory resource is an important resource in an electronic system, and the system needs the memory to perform operations such as input data buffering, intermediate data temporary storage, output result storage and access and the like. Usually, a large number of memory circuits are arranged in a programmable logic device, an on-chip integrated system and a high-speed analog-to-digital converter, so as to ensure that the device can smoothly perform high-speed and large-scale data processing tasks, and the memory circuit is the most important circuit module for ensuring high-performance operation of the device.
Devices applied to space equipment are generally affected by space single event effect, so that data in a memory can be subjected to single event upset, and user data errors are caused. Currently, in the memory consolidation design, the mainstream method is to use a quad-cross dual-mode redundancy structure. The method can effectively prevent a plurality of data bit upsets caused by single event effect, but in single read-write operation, the probability of single data bit upsets is still large and difficult to avoid, so that the error correction and detection circuit is necessary to be adopted to verify the data of the memory, and the reliability and stability of the operation of the device are realized.
Conventional checking methods include parity checking, CRC checking, etc., which check whether an error occurs in data through a specific algorithm. However, the parity check can only determine whether the data has errors, and cannot determine information such as the number of bits and the position of the errors in the data; the CRC check can accurately know the error bit number in the data, but the algorithm is complex, and a large amount of area is occupied by adopting a circuit for realization. In addition, both of the two verification methods can only detect errors in data, the found errors cannot be corrected, and the data can only be refreshed after single event upset occurs in a space radiation environment, so that the execution efficiency and the transmission performance of the device are influenced. Therefore, a circuit capable of verifying and correcting the memory data is required to be designed, so that the error detection and correction of the memory transmission data are realized, the stable operation of the memory applied to the space environment is ensured, and the radiation-resistant index of the device is improved.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the configurable error correction and detection circuit for the single event upset resistant memory can realize check bit encoding and decoding check operation of 11-64 bit data, prompt and correct one bit error in the data or prompt two bit error in the data according to a check result, ensure stable operation of the memory, improve radiation resistance of the device and meet the requirement of a space application device on radiation resistance reinforcement of the memory.
The solution of the invention is as follows:
a selectable bit width error detection and correction circuit for a single event upset resistant memory comprises an error detection and correction coding module and an error detection and correction decoding module;
error correction and detection coding module: the method can carry out check code encoding operation on input data with the bit width of 11-64, generate 8-bit check codes for carrying out error correction and detection on the data, and output the check codes and the input data to an error correction and detection decoding module;
and the error correction and detection decoding module: the error correction coding module can decode and check the data signal from the error correction coding module, output a bit error prompt and an error position when a bit error exists in the data signal, correct the error, and output a two-bit error prompt when a two-bit error exists in the data signal.
The error detection and correction coding module is provided with 64 data input ports DI <63:0> and 4 control ports CLK, EN, S <1:0> and 8 data output ports DIP <7:0>, the control ports S <1:0> are bit width selection ports, and input data with 11-64 bit widths are coded by setting the value of S <1:0 >;
the control port CLK is used for providing a clock for an output register in the error correction and detection coding module, the control port EN is used for providing an enabling signal for the output register in the error correction and detection coding module, when EN is 1 and CLK is square wave, the error correction and detection coding module is enabled, all ports are effective, when EN is 0 and CLK is constant 0 or constant 1, the error correction and detection coding module is disabled, and all ports are invalid.
The specific way of encoding the input data with 11-64 bit width by setting the value of S <1:0> is as follows:
when S <1> and S <0> are both 1, the error correction and detection coding module can code data with a bit width of 58-64, DI <63:0> is valid at the moment, and DIP <7:0> outputs 8-bit check codes; when S <1> is 1 and S <0> is 0, the error correction and detection coding module can code data with the bit width of 27-57, and at the moment, DI <56:0> is valid, DI <63:57> is invalid, DIP <5:0> outputs the valid bit of the check code, and DIP <7:6> is set to be 0; when S <1> is 0 and S <0> is 1, the error correction and detection coding module can code data with 12-26 bit width, at the moment, DI <25:0> is valid, DI <63:26> is invalid, DIP <4:0> outputs the valid bit of the check code, and DIP <7:5> is set to be 0; when S <1> and S <0> are both 0, the error correction and detection coding module can code data within 11 bit width, at the moment, DI <10:0> is valid, DI <63:11> is invalid, DIP <4:0> outputs the valid bit of the check code, and DIP <7:5> is set to be 0.
The error correction and detection coding module comprises a first coding and decoding module K15, a second coding and decoding module K16, a third coding and decoding module K17, a fourth coding and decoding module K18, a fifth coding and decoding module K19, a sixth coding and decoding module K20, a seventh coding and decoding module K21, an eighth coding and decoding module K22, eight output registers, nine AND gates and one OR gate K39;
the eight output registers are respectively an output register K23, an output register K24, an output register K25, an output register K26, an output register K27, an output register K28, an output register K29 and an output register K30;
the nine AND gates are respectively an AND gate K31, an AND gate K32, an AND gate K33, an AND gate K34, an AND gate K35, an AND gate K36, an AND gate K37, an AND gate K38 and an AND gate K40;
the input terminals A <35:0> are connected to the input terminals DI <63:0> according to different coding orders;
the connection relationship is as follows:
the 36 input interfaces of the input terminals A <35:0> of the first codec module K15 are respectively connected to DI <0>, DI <1>, DI <3>, DI <4>, DI <6>, DI <8>, DI <10>, DI <11>, DI <13>, DI <15>, DI <17>, DI <19>, DI <21>, DI <23>, DI <25>, DI <26>, DI <28>, DI <30>, DI <32>, DI <34>, DI <36>, DI <38>, DI <40>, DI <42>, DI <44>, DI <46>, DI <48>, DI <50>, DI <52>, DI <54>, DI <56>, DI <57>, DI <59>, DI <61>, DI <63>, and GND;
the 36 input interfaces of the input terminals A <35:0> of the second codec module K16 are respectively connected to DI <0>, DI <2>, DI <3>, DI <5>, DI <6>, DI <9>, DI <10>, DI <12>, DI <13>, DI <16>, DI <17>, DI <20>, DI <21>, DI <24>, DI <25>, DI <27>, DI <28>, DI <31>, DI <32>, DI <35>, DI <36>, DI <39>, DI <40>, DI <43>, DI <44>, DI <47>, DI <48>, DI <51>, DI <52>, DI <55>, DI <56>, DI <58>, DI <59>, DI <62>, DI <63>, and GND;
the 36 input interfaces of the input terminals A <35:0> of the third codec module K17 are respectively connected to DI <1>, DI <2>, DI <3>, DI <7>, DI <8>, DI <9>, DI <10>, DI <14>, DI <15>, DI <16>, DI <17>, DI <22>, DI <23>, DI <24>, DI <25>, DI <29>, DI <30>, DI <31>, DI <32>, DI <37>, DI <38>, DI <39>, DI <40>, DI <45>, DI <46>, DI <47>, DI <48>, DI <53>, DI <54>, DI <55>, DI <66>, DI <60>, DI <61>, DI <62>, DI <63>, and GND;
the 36 input interfaces of the input terminals A <35:0> of the fourth codec module K18 are respectively connected to DI <4>, DI <5>, DI <6>, DI <7>, DI <8>, DI <9>, DI <10>, DI <18>, DI <19>, DI <20>, DI <21>, DI <22>, DI <23>, DI <24>, DI <25>, DI <33>, DI <34>, DI <35>, DI <36>, DI <37>, DI <38>, DI <39>, DI <40>, DI <49>, DI <50>, DI <51>, DI <52>, DI <53>, DI <54>, DI <55>, DI <56>, GND;
the 36 input interfaces of the input terminals A <35:0> of the fifth codec module K19 are respectively connected to DI <11>, DI <12>, DI <13>, DI <14>, DI <15>, DI <16>, DI <17>, DI <18>, DI <19>, DI <20>, DI <21>, DI <22>, DI <23>, DI <24>, DI <25>, DI <41>, DI <42>, DI <43>, DI <44>, DI <45>, DI <46>, DI <47>, DI <48>, DI <49>, DI <50>, DI <51>, DI <52>, DI <53>, DI <54>, DI <55>, DI <56>, GND;
the 36 input interfaces of the input terminals A <35:0> of the sixth codec module K20 are respectively connected to DI <26>, DI <27>, DI <28>, DI <29>, DI <30>, DI <31>, DI <32>, DI <33>, DI <34>, DI <35>, DI <36>, DI <37>, DI <38>, DI <39>, DI <40>, DI <41>, DI <42>, DI <43>, DI <44>, DI <45>, DI <46>, DI <47>, DI <48>, DI <49>, DI <50>, DI <51>, DI <52>, DI <53>, DI <54>, DI <55>, DI <56>, GND;
36 input interfaces of input ends A <35:0> of the seventh codec module K21 are respectively connected with DI <57>, DI <58>, DI <59>, DI <60>, DI <61>, DI <62>, DI <63>, GND;
the eight codec module K22 has 36 input ports for input terminals A <35:0> respectively connected to DI <0>, DI <1>, DI <2>, DI <4>, DI <5>, DI <7>, DI <10>, DI <11>, DI <12>, DI <14>, DI <17>, DI <18>, DI <21>, DI <23>, DI <24>, DI <26>, DI <27>, DI <29>, DI <32>, DI <33>, DI <36>, DI <38>, DI <39>, DI <41>, DI <44>, DI <46>, DI <47>, DI <50>, DI <51>, DI <53>, DI <56>, DI <57>, DI <58>, DI <60>, DI <63>, and GND;
the data input ends D of the eight output registers are correspondingly connected with the output ends ZN of the eight encoding and decoding modules one by one, the control ends CLK of the eight output registers are all connected to the control ports CLK of the error correction and detection encoding modules, the control ends EN of the eight output registers are all connected to the control ports EN of the error correction and detection encoding modules, the eight output registers are in one-to-one correspondence with the eight AND gates, the output end Q of each output register is connected to one input end of the corresponding AND gate, the other input ends of the AND gate K31, the AND gate K32, the AND gate K33 and the AND gate K34 are all connected with VCC, the other input end of the AND gate K35 is connected with the output end of the OR gate K39, or the two input ends of the OR gate K39 are respectively connected with the control ports S <1:0 >; the other input end of the AND gate K36 is connected with a control port S <1>, the other input ends of the AND gate K37 and the AND gate K38 are connected with the output end of the AND gate K40, the two input ends of the AND gate K40 are respectively connected with control ends S <1:0>, and the output ends of the AND gates K31 to K38 are used as DIP <7:0 >.
The first codec module K15, the second codec module K16, the third codec module K17, the fourth codec module K18, the fifth codec module K19, the sixth codec module K20, the seventh codec module K21 and the eighth codec module K22 in the error detection and correction coding module have the same circuit structure, and are all codec modules formed by exclusive or gates.
The error detection and correction decoding module comprises 72 data input ports of DI1<63:0>, DIP1<7:0> and 2 control ports of CLK1 and EN1, 7 error correction signal output ports of DCHECK <6:0> and 2 error flag bit ports of SBITERR and DBITERR;
the control port CLK1 is used for providing a clock for an output register in the error detection and correction decoding module, the EN1 is used for providing an enabling signal for the output register in the error detection and correction decoding module, the error flag bit ports SBITERR and DBITERR are both valid when EN1 is 1 and CLK1 is square wave, and the error flag bit ports SBITERR and DBITERR are both invalid when EN1 is 0 and CLK1 is constant 0 or constant 1; the input port DI1<63:0> is used for inputting data, the DIP1<7:0> is used for inputting check bits, when the error correction detection decoding module finds a bit error in the input data, DCHECK <6:0> outputs the error position in the form of BCD code, SBITERR is set and output, and when two bit errors are found, DBITERR is set and output.
The error detection and correction decoding module comprises nine coding and decoding modules, a seven-input OR gate K50, a NAND gate K51, an XOR gate K52, an output register K53 and an output register K54; the nine codec modules are respectively a ninth codec module K41, a tenth codec module K42, an eleventh codec module K43, a twelfth codec module K44, a thirteenth codec module K45, a fourteenth codec module K46, a fifteenth codec module K47, a sixteenth codec module K48 and a seventeenth codec module K49;
the input terminals A <35:0> of the nine codec modules are connected to the input terminals DI1<63:0> and DIP1<7:0> according to different coding orders, and the connection relationship is as follows:
the ninth codec module K has 36 input ports at input terminals A <35:0> respectively connected to DI <0>, DI <1>, DI <3>, DI <4>, DI <6>, DI <8>, DI <10>, DI <11>, DI <13>, DI <15>, DI <17>, DI <19>, DI <21>, DI <23>, DI <25>, DI <26>, DI <28>, DI <30>, DI <32>, DI <34>, DI <36>, DI <38>, DI <40>, DI <42>, DI <44>, DI <46>, DI <48>, DI <50>, DI <52>, DI <54>, DI <56>, DI <57>, DI <59>, DI <61>, DI <63>, DIP <0 >;
the 36 input interfaces of the input terminals A <35:0> of the tenth codec module K are connected to DI <0>, DI <2>, DI <3>, DI <5>, DI <6>, DI <9>, DI <10>, DI <12>, DI <13>, DI <16>, DI <17>, DI <20>, DI <21>, DI <24>, DI <25>, DI <27>, DI <28>, DI <31>, DI <32>, DI <35>, DI <36>, DI <39>, DI <40>, DI <43>, DI <44>, DI <47>, DI <48>, DI <51>, DI <52>, DI <55>, DI <56>, DI <58>, DI <59>, DI <62>, DI <63>, DIP <1>, respectively;
the eleventh codec module K has 36 input ports at input terminals A <35:0> respectively connected to DI <1>, DI <2>, DI <3>, DI <7>, DI <8>, DI <9>, DI <10>, DI <14>, DI <15>, DI <16>, DI <17>, DI <22>, DI <23>, DI <24>, DI <25>, DI <29>, DI <30>, DI <31>, DI <32>, DI <37>, DI <38>, DI <39>, DI <40>, DI <45>, DI <46>, DI <47>, DI <48>, DI <53>, DI <54>, DI <55>, DI <66>, DI <60>, DI <61>, DI <62>, DI <63>, DIP <2 >;
the 36 input interfaces of the input terminals a <35:0> of the twelfth codec module K44 are respectively connected to DI 44 <4>, DI 44 <5>, DI 44 <6>, DI 44 <7>, DI 44 <8>, DI 44 <9>, DI 44 <10>, DI 44 <18>, DI 44 <19>, DI 44 <20>, DI 44 <21>, DI 44 <22>, DI 44 <23>, DI 44 <24>, DI 44 <25>, DI 44 <33>, DI 44 <34>, DI 44 <35>, DI 44 <36>, DI 44 <37>, DI 44 <38>, DI 44 <39>, DI 44 <40>, DI 44 <49>, DI 44 <50>, DI 44 <52>, DI 44 <53>, DI 44 <54>, DI 44 < 72 >, DI 44 < 72 > and DI GND, DI 3 < 72 > respectively;
the 36 input interfaces of the inputs A <35:0> of the thirteenth codec module K45 are respectively connected to DI 45 <11>, DI 45 <12>, DI 45 <13>, DI 45 <14>, DI 45 <15>, DI 45 <16>, DI 45 <17>, DI 45 <18>, DI 45 <19>, DI 45 <20>, DI 45 <21>, DI 45 <22>, DI 45 <23>, DI 45 <24>, DI 45 <25>, DI 45 <41>, DI 45 <42>, DI 45 <43>, DI 45 <44>, DI 45 <45>, DI 45 <46>, DI 45 <47>, DI 45 <48>, DI 45 <49>, DI 45 <50>, DI 45 <52>, DI 45 <53>, DI <45>, DI < 72 >, DI <45>, DI 45 < 72 >, DI <45>, DI < 72 >, GND >, DI 45 <45>, GND, DI < 72 >, GND >, DI 45 < 72 > and GND <55> and GND < 72 > 45;
the 36 input interfaces of the input terminals a <35:0> of the fourteenth codec module K46 are respectively connected to DI 46 <26>, DI 46 <27>, DI 46 <28>, DI 46 <29>, DI 46 <30>, DI 46 <31>, DI 46 <32>, DI 46 <33>, DI 46 <34>, DI 46 <35>, DI 46 <36>, DI 46 <37>, DI 46 <38>, DI 46 <39>, DI 46 <40>, DI 46 <41>, DI 46 <42>, DI 46 <43>, DI 46 <44>, DI 46 <45>, DI 46 <46>, DI 46 <47>, DI 46 <48>, DI 46 <49>, DI 46 <50>, DI 46 <52>, DI 46 <53>, DI 46 < 72 >, DI 46 < 72 > and DI GND, DI 46 < 72 > respectively;
36 input interfaces of input ends A <35:0> of the fifteenth codec module K47 are respectively connected with DI1<57>, DI1<58>, DI1<59>, DI1<60>, DI1<61>, DI1<62>, DI1<63>, DIP1<6>, GND;
the sixteenth codec module K has 36 input interfaces at input terminals A <35:0> respectively connected to DI <0>, DI <2>, DI <4>, DI <6>, DI <8>, DI <10>, DI <12>, DI <14>, DI <16>, DI <18>, DI <20>, DI <22>, DI <24>, DI <26>, DI <28>, DI <30>, DI <32>, DI <34>, DI <36>, DI <38>, DI <40>, DI <42>, DI <44>, DI <46>, DI <48>, DI <50>, DI <52>, DI <54>, DI <56>, DI <58>, DI <60>, DI <62>, DIP <0>, DIP <2>, DIP <4> and DIP <6 >;
36 input interfaces of the input terminals A <35:0> of the seventeenth codec module K are connected to DI <1>, DI <3>, DI <5>, DI <7>, DI <9>, DI <11>, DI <13>, DI <15>, DI <17>, DI <19>, DI <21>, DI <23>, DI <25>, DI <27>, DI <29>, DI <31>, DI <33>, DI <35>, DI <37>, DI <39>, DI <41>, DI <43>, DI <45>, DI <47>, DI <49>, DI <51>, DI <53>, DI <55>, DI <57>, DI <59>, DI <61>, DI <63>, DIP <1>, DIP <3>, DIP <5> and DIP <7>, respectively;
the output ends ZN of the ninth codec module K41, the tenth codec module K42, the eleventh codec module K43, the twelfth codec module K44, the thirteenth codec module K45, the fourteenth codec module K46 and the fifteenth codec module K47 are used as output ends DCHECK <0:6> and are simultaneously connected to the input ends of a seven-input OR gate K50, the output end of the seven-input OR gate K50 is connected to one input end of a NAND gate K51, two input ends of an XOR gate K52 are respectively connected to the output end of the sixteenth codec module K48 and the output end of the seventeenth codec module K49, the output end of the XOR gate K52 is simultaneously connected to the other input end of the NAND gate K51 and the data input end D of the output register K54, the output end of the NAND gate K51 is connected to the data input end D of the output register K53, the control ends of the output registers K53 and K54 are connected to the control ports CLK1 of the error detection and detection modules, the control terminals EN of the output registers K53 and K54 are all connected to a control port EN1 of the error correction and detection decoding module, the output terminal of the output register K53 is used as an error flag bit port SBITERR of the error correction and detection decoding module, and the output terminal of the output register K54 is used as an error flag bit port DBITERR of the error correction and detection decoding module.
The ninth codec module K41, the tenth codec module K42, the eleventh codec module K43, the twelfth codec module K44, the thirteenth codec module K45, the fourteenth codec module K46, the fifteenth codec module K47, the sixteenth codec module K48, and the seventeenth codec module K49 in the error detection and correction decoding modules have the same circuit structure, and are all codec modules formed by exclusive or gates.
The encoding and decoding module formed by the exclusive-OR gates comprises three input exclusive-OR gates K55, K56, K57, K58, K59, K60, K61, K62, K63, K64, K65, K66, K67, K68, K69 and K70, a four input exclusive-OR gate K71 and an inverter K72;
three input ends of three-input exclusive-or gates K55, K56, K57, K59, K60, K61, K63, K64, K65, K67, K68 and K69 are sequentially connected with an input end A <0:35> of the module, outputs of three-input exclusive-or gates K55, K56 and K57 are used as three inputs of a three-input exclusive-or gate K58, outputs of three-input exclusive-or gates K59, K60 and K61 are used as three inputs of a three-input exclusive-or gate K62, outputs of three-input exclusive-or gates K63, K64 and K65 are used as three inputs of a three-input exclusive-or gate K66, outputs of three-input exclusive-or gates K67, K68 and K69 are used as three inputs of a three-input exclusive-or gate K70, outputs of three-input exclusive-or gates K70, K70 and K70 are used as four-input and output ends of a four-input or gate ZN 70 and an output of a four-input output of the module 70.
Compared with the prior art, the invention has the advantages that:
(1) the error correction and detection circuit can carry out coding and decoding verification on 11-64 bit data on the premise of occupying less bit width, can prompt and correct one-bit errors in the data or two-bit errors in the prompt data according to a verification result, and can effectively improve the radiation-resistant reinforcement index of the memory by matching with a memory structure resistant to multi-bit upset.
(2) The invention can realize the selection of the coding bit width through the bit width selection port, can effectively avoid occupying excessive bit width when the data bit width is small, improves the utilization efficiency of system bandwidth, and reduces the size of the coded data.
(3) The invention has simple algorithm, can be realized by only adopting a logic gate circuit, has small circuit area and is suitable for space application.
Drawings
FIG. 1 is a schematic diagram of an optional bit width error correction and detection circuit according to the present invention;
FIG. 2 is a circuit diagram of an error correction and detection encoding module of the present invention;
FIG. 3 is a circuit diagram of an error detection and correction decoding module of the present invention;
fig. 4 is a circuit diagram of a codec module formed by an xor gate according to the present invention.
Detailed Description
The invention provides a selectable bit width error detection and correction circuit for a single event upset resistant memory, which is divided into an error detection and correction coding module K1 and an error detection and correction decoding module K7 as shown in FIG. 1.
The error detection and correction coding module K1 comprises 64 data input ports DI <63:0> and 4 control ports CLK, EN, S <1:0> and 8 data output ports DIP <7:0>, wherein the control ports S <1:0> are bit width selection ports, and input data with 11-64 bit widths are coded by setting the value of S <1:0 >.
The specific way of encoding the input data with 11-64 bit width by setting the value of S <1:0> is as follows:
when S <1> and S <0> are both 1, the error correction and detection coding module can code data with a bit width of 58-64, DI <63:0> is valid at the moment, and DIP <7:0> outputs 8-bit check codes; when S <1> is 1 and S <0> is 0, the error correction and detection coding module can code data with the bit width of 27-57, and at the moment, DI <56:0> is valid, DI <63:57> is invalid, DIP <5:0> outputs the valid bit of the check code, and DIP <7:6> is set to be 0; when S <1> is 0 and S <0> is 1, the error correction and detection coding module can code data with 12-26 bit width, at the moment, DI <25:0> is valid, DI <63:26> is invalid, DIP <4:0> outputs the valid bit of the check code, and DIP <7:5> is set to be 0; when S <1> and S <0> are both 0, the error correction and detection coding module can code data within 11 bit width, at the moment, DI <10:0> is valid, DI <63:11> is invalid, DIP <4:0> outputs the valid bit of the check code, and DIP <7:5> is set to be 0.
The control port CLK is used for providing a clock for an output register in the error correction and detection coding module, the control port EN is used for providing an enabling signal for the output register in the error correction and detection coding module, when EN is 1 and CLK is square wave, the error correction and detection coding module is enabled, all ports are effective, when EN is 0 and CLK is constant 0 or constant 1, the error correction and detection coding module is disabled, and all ports are invalid.
Error correction and detection decoding module K7 has 72 data input ports DI1<63:0>, DIP1<7:0> and 2 control ports CLK1 and EN1, 7 error correction signal output ports DCHECK <6:0> and 2 error flag bit ports SBITERR and DBITERR;
the control port CLK1 is used for providing a clock for an output register in the error detection and correction decoding module, the EN1 is used for providing an enabling signal for the output register in the error detection and correction decoding module, the error flag bit ports SBITERR and DBITERR are both valid when EN1 is 1 and CLK1 is square wave, and the error flag bit ports SBITERR and DBITERR are both invalid when EN1 is 0 and CLK1 is constant 0 or constant 1; the input port DI1<63:0> is used for inputting data, the DIP1<7:0> is used for inputting check bits, when the error correction and detection decoding module finds a bit error in the input data according to the check code, DCHECK <6:0> outputs the error position in the form of BCD code, SBITERR is set and output, and when two bit errors are found, DBITERR is set and output.
As shown in fig. 2, the error detection and correction coding module K1 includes a first codec module K15, a second codec module K16, a third codec module K17, a fourth codec module K18, a fifth codec module K19, a sixth codec module K20, a seventh codec module K21, an eighth codec module K22, eight output registers, nine and gates and one or gate K39;
the eight output registers are respectively an output register K23, an output register K24, an output register K25, an output register K26, an output register K27, an output register K28, an output register K29 and an output register K30;
the nine AND gates are respectively an AND gate K31, an AND gate K32, an AND gate K33, an AND gate K34, an AND gate K35, an AND gate K36, an AND gate K37, an AND gate K38 and an AND gate K40;
the inputs A <35:0> are connected to the inputs DI <63:0> according to different coding orders, so that corresponding coding logic is implemented.
The connection relationship is as follows:
the 36 input interfaces of the input terminals A <35:0> of the first codec module K15 are respectively connected to DI <0>, DI <1>, DI <3>, DI <4>, DI <6>, DI <8>, DI <10>, DI <11>, DI <13>, DI <15>, DI <17>, DI <19>, DI <21>, DI <23>, DI <25>, DI <26>, DI <28>, DI <30>, DI <32>, DI <34>, DI <36>, DI <38>, DI <40>, DI <42>, DI <44>, DI <46>, DI <48>, DI <50>, DI <52>, DI <54>, DI <56>, DI <57>, DI <59>, DI <61>, DI <63>, and GND;
the 36 input interfaces of the input terminals A <35:0> of the second codec module K16 are respectively connected to DI <0>, DI <2>, DI <3>, DI <5>, DI <6>, DI <9>, DI <10>, DI <12>, DI <13>, DI <16>, DI <17>, DI <20>, DI <21>, DI <24>, DI <25>, DI <27>, DI <28>, DI <31>, DI <32>, DI <35>, DI <36>, DI <39>, DI <40>, DI <43>, DI <44>, DI <47>, DI <48>, DI <51>, DI <52>, DI <55>, DI <56>, DI <58>, DI <59>, DI <62>, DI <63>, and GND;
the 36 input interfaces of the input terminals A <35:0> of the third codec module K17 are respectively connected to DI <1>, DI <2>, DI <3>, DI <7>, DI <8>, DI <9>, DI <10>, DI <14>, DI <15>, DI <16>, DI <17>, DI <22>, DI <23>, DI <24>, DI <25>, DI <29>, DI <30>, DI <31>, DI <32>, DI <37>, DI <38>, DI <39>, DI <40>, DI <45>, DI <46>, DI <47>, DI <48>, DI <53>, DI <54>, DI <55>, DI <66>, DI <60>, DI <61>, DI <62>, DI <63>, and GND;
the 36 input interfaces of the input terminals A <35:0> of the fourth codec module K18 are respectively connected to DI <4>, DI <5>, DI <6>, DI <7>, DI <8>, DI <9>, DI <10>, DI <18>, DI <19>, DI <20>, DI <21>, DI <22>, DI <23>, DI <24>, DI <25>, DI <33>, DI <34>, DI <35>, DI <36>, DI <37>, DI <38>, DI <39>, DI <40>, DI <49>, DI <50>, DI <51>, DI <52>, DI <53>, DI <54>, DI <55>, DI <56>, GND;
the 36 input interfaces of the input terminals A <35:0> of the fifth codec module K19 are respectively connected to DI <11>, DI <12>, DI <13>, DI <14>, DI <15>, DI <16>, DI <17>, DI <18>, DI <19>, DI <20>, DI <21>, DI <22>, DI <23>, DI <24>, DI <25>, DI <41>, DI <42>, DI <43>, DI <44>, DI <45>, DI <46>, DI <47>, DI <48>, DI <49>, DI <50>, DI <51>, DI <52>, DI <53>, DI <54>, DI <55>, DI <56>, GND;
the 36 input interfaces of the input terminals A <35:0> of the sixth codec module K20 are respectively connected to DI <26>, DI <27>, DI <28>, DI <29>, DI <30>, DI <31>, DI <32>, DI <33>, DI <34>, DI <35>, DI <36>, DI <37>, DI <38>, DI <39>, DI <40>, DI <41>, DI <42>, DI <43>, DI <44>, DI <45>, DI <46>, DI <47>, DI <48>, DI <49>, DI <50>, DI <51>, DI <52>, DI <53>, DI <54>, DI <55>, DI <56>, GND;
36 input interfaces of input ends A <35:0> of the seventh codec module K21 are respectively connected with DI <57>, DI <58>, DI <59>, DI <60>, DI <61>, DI <62>, DI <63>, GND;
the eight codec module K22 has 36 input ports for input terminals A <35:0> respectively connected to DI <0>, DI <1>, DI <2>, DI <4>, DI <5>, DI <7>, DI <10>, DI <11>, DI <12>, DI <14>, DI <17>, DI <18>, DI <21>, DI <23>, DI <24>, DI <26>, DI <27>, DI <29>, DI <32>, DI <33>, DI <36>, DI <38>, DI <39>, DI <41>, DI <44>, DI <46>, DI <47>, DI <50>, DI <51>, DI <53>, DI <56>, DI <57>, DI <58>, DI <60>, DI <63>, and GND;
the data input ends D of the eight output registers are correspondingly connected with the output ends ZN of the eight encoding and decoding modules one by one, the control ends CLK of the eight output registers are all connected to the control ports CLK of the error correction and detection encoding modules, the control ends EN of the eight output registers are all connected to the control ports EN of the error correction and detection encoding modules, the eight output registers are in one-to-one correspondence with the eight AND gates, the output end Q of each output register is connected to one input end of the corresponding AND gate, the other input ends of the AND gate K31, the AND gate K32, the AND gate K33 and the AND gate K34 are all connected with VCC, the other input end of the AND gate K35 is connected with the output end of the OR gate K39, or the two input ends of the OR gate K39 are respectively connected with the control ports S <1:0 >; the other input end of the AND gate K36 is connected with a control port S <1>, the other input ends of the AND gate K37 and the AND gate K38 are connected with the output end of the AND gate K40, the two input ends of the AND gate K40 are respectively connected with control ends S <1:0>, and the output ends of the AND gates K31 to K38 are used as DIP <7:0 >.
The first codec module K15, the second codec module K16, the third codec module K17, the fourth codec module K18, the fifth codec module K19, the sixth codec module K20, the seventh codec module K21 and the eighth codec module K22 in the error detection and correction coding module have the same circuit structure, and are all codec modules formed by exclusive or gates.
As shown in fig. 3, the error detection and correction decoding module K7 includes nine codec modules, seven input or gates K50, a nand gate K51, an xor gate K52, an output register K53 and an output register K54; the nine codec modules are respectively a ninth codec module K41, a tenth codec module K42, an eleventh codec module K43, a twelfth codec module K44, a thirteenth codec module K45, a fourteenth codec module K46, a fifteenth codec module K47, a sixteenth codec module K48 and a seventeenth codec module K49. The inputs A <35:0> of the nine codec modules are connected to the inputs DI1<63:0> and DIP1<7:0> according to different coding orders, thereby forming corresponding decoding logic.
The connection relationship is as follows:
the ninth codec module K has 36 input ports at input terminals A <35:0> respectively connected to DI <0>, DI <1>, DI <3>, DI <4>, DI <6>, DI <8>, DI <10>, DI <11>, DI <13>, DI <15>, DI <17>, DI <19>, DI <21>, DI <23>, DI <25>, DI <26>, DI <28>, DI <30>, DI <32>, DI <34>, DI <36>, DI <38>, DI <40>, DI <42>, DI <44>, DI <46>, DI <48>, DI <50>, DI <52>, DI <54>, DI <56>, DI <57>, DI <59>, DI <61>, DI <63>, DIP <0 >;
the 36 input interfaces of the input terminals A <35:0> of the tenth codec module K are connected to DI <0>, DI <2>, DI <3>, DI <5>, DI <6>, DI <9>, DI <10>, DI <12>, DI <13>, DI <16>, DI <17>, DI <20>, DI <21>, DI <24>, DI <25>, DI <27>, DI <28>, DI <31>, DI <32>, DI <35>, DI <36>, DI <39>, DI <40>, DI <43>, DI <44>, DI <47>, DI <48>, DI <51>, DI <52>, DI <55>, DI <56>, DI <58>, DI <59>, DI <62>, DI <63>, DIP <1>, respectively;
the eleventh codec module K has 36 input ports at input terminals A <35:0> respectively connected to DI <1>, DI <2>, DI <3>, DI <7>, DI <8>, DI <9>, DI <10>, DI <14>, DI <15>, DI <16>, DI <17>, DI <22>, DI <23>, DI <24>, DI <25>, DI <29>, DI <30>, DI <31>, DI <32>, DI <37>, DI <38>, DI <39>, DI <40>, DI <45>, DI <46>, DI <47>, DI <48>, DI <53>, DI <54>, DI <55>, DI <66>, DI <60>, DI <61>, DI <62>, DI <63>, DIP <2 >;
the 36 input interfaces of the input terminals a <35:0> of the twelfth codec module K44 are respectively connected to DI 44 <4>, DI 44 <5>, DI 44 <6>, DI 44 <7>, DI 44 <8>, DI 44 <9>, DI 44 <10>, DI 44 <18>, DI 44 <19>, DI 44 <20>, DI 44 <21>, DI 44 <22>, DI 44 <23>, DI 44 <24>, DI 44 <25>, DI 44 <33>, DI 44 <34>, DI 44 <35>, DI 44 <36>, DI 44 <37>, DI 44 <38>, DI 44 <39>, DI 44 <40>, DI 44 <49>, DI 44 <50>, DI 44 <52>, DI 44 <53>, DI 44 <54>, DI 44 < 72 >, DI 44 < 72 > and DI GND, DI 3 < 72 > respectively;
the 36 input interfaces of the inputs A <35:0> of the thirteenth codec module K45 are respectively connected to DI 45 <11>, DI 45 <12>, DI 45 <13>, DI 45 <14>, DI 45 <15>, DI 45 <16>, DI 45 <17>, DI 45 <18>, DI 45 <19>, DI 45 <20>, DI 45 <21>, DI 45 <22>, DI 45 <23>, DI 45 <24>, DI 45 <25>, DI 45 <41>, DI 45 <42>, DI 45 <43>, DI 45 <44>, DI 45 <45>, DI 45 <46>, DI 45 <47>, DI 45 <48>, DI 45 <49>, DI 45 <50>, DI 45 <52>, DI 45 <53>, DI <45>, DI < 72 >, DI <45>, DI 45 < 72 >, DI <45>, DI < 72 >, GND >, DI 45 <45>, GND, DI < 72 >, GND >, DI 45 < 72 > and GND <55> and GND < 72 > 45;
the 36 input interfaces of the input terminals a <35:0> of the fourteenth codec module K46 are respectively connected to DI 46 <26>, DI 46 <27>, DI 46 <28>, DI 46 <29>, DI 46 <30>, DI 46 <31>, DI 46 <32>, DI 46 <33>, DI 46 <34>, DI 46 <35>, DI 46 <36>, DI 46 <37>, DI 46 <38>, DI 46 <39>, DI 46 <40>, DI 46 <41>, DI 46 <42>, DI 46 <43>, DI 46 <44>, DI 46 <45>, DI 46 <46>, DI 46 <47>, DI 46 <48>, DI 46 <49>, DI 46 <50>, DI 46 <52>, DI 46 <53>, DI 46 < 72 >, DI 46 < 72 > and DI GND, DI 46 < 72 > respectively;
36 input interfaces of input ends A <35:0> of the fifteenth codec module K47 are respectively connected with DI1<57>, DI1<58>, DI1<59>, DI1<60>, DI1<61>, DI1<62>, DI1<63>, DIP1<6>, GND;
the sixteenth codec module K has 36 input interfaces at input terminals A <35:0> respectively connected to DI <0>, DI <2>, DI <4>, DI <6>, DI <8>, DI <10>, DI <12>, DI <14>, DI <16>, DI <18>, DI <20>, DI <22>, DI <24>, DI <26>, DI <28>, DI <30>, DI <32>, DI <34>, DI <36>, DI <38>, DI <40>, DI <42>, DI <44>, DI <46>, DI <48>, DI <50>, DI <52>, DI <54>, DI <56>, DI <58>, DI <60>, DI <62>, DIP <0>, DIP <2>, DIP <4> and DIP <6 >;
36 input interfaces of the input terminals A <35:0> of the seventeenth codec module K are connected to DI <1>, DI <3>, DI <5>, DI <7>, DI <9>, DI <11>, DI <13>, DI <15>, DI <17>, DI <19>, DI <21>, DI <23>, DI <25>, DI <27>, DI <29>, DI <31>, DI <33>, DI <35>, DI <37>, DI <39>, DI <41>, DI <43>, DI <45>, DI <47>, DI <49>, DI <51>, DI <53>, DI <55>, DI <57>, DI <59>, DI <61>, DI <63>, DIP <1>, DIP <3>, DIP <5> and DIP <7>, respectively;
the output ends ZN of the ninth codec module K41, the tenth codec module K42, the eleventh codec module K43, the twelfth codec module K44, the thirteenth codec module K45, the fourteenth codec module K46 and the fifteenth codec module K47 are used as DCHECK <0:6> and are simultaneously connected to the input end of a seven-input OR gate K50, the output end of the seven-input OR gate K50 is connected to one input end of a NAND gate K51, two input ends of the XOR gate K52 are respectively connected to the output end of the sixteenth codec module K48 and the output end of the seventeenth codec module K49, the output end of the XOR gate K52 is simultaneously connected to the other input end of the NAND gate K51 and the data input end D of the output register K54, the output end of the NAND gate K51 is connected to the data input end D of the output register K53, the control ends CLK of the output registers K53 and 539K 54 are connected to the control ports CLK1 of all error detection decoding modules, the control terminals EN of the output registers K53 and K54 are all connected to a control port EN1 of the error correction and detection decoding module, the output terminal of the output register K53 is used as an error flag bit port SBITERR of the error correction and detection decoding module, and the output terminal of the output register K54 is used as an error flag bit port DBITERR of the error correction and detection decoding module.
The ninth codec module K41, the tenth codec module K42, the eleventh codec module K43, the twelfth codec module K44, the thirteenth codec module K45, the fourteenth codec module K46, the fifteenth codec module K47, the sixteenth codec module K48, and the seventeenth codec module K49 in the error detection and correction decoding modules have the same circuit structure, and are all codec modules formed by exclusive or gates.
As shown in fig. 4, the codec module formed by the xor gates includes three input xor gates K55, K56, K57, K58, K59, K60, K61, K62, K63, K64, K65, K66, K67, K68, K69, K70, a four input xor gate K71, and an inverter K72. The input ends of three-input exclusive-or gates K55, K56, K57, K59, K60, K61, K63, K64, K65, K67, K68 and K69 are sequentially connected with the input end A <0:35>, the output ends of three-input exclusive-or gates K55, K56 and K57 are respectively connected with the input end of a three-input exclusive-or gate K58, the output ends of three-input exclusive-or gates K59, K60 and K61 are respectively connected with the input end of a three-input exclusive-or gate K62, the output ends of three-input exclusive-or gates K63, K64 and K65 are respectively connected with the input end of a three-input exclusive-or gate K66, the output ends of three-input exclusive-or gates K67, K68 and K69 are respectively connected with the input end of a three-input exclusive-or gate K70, the output ends of three-input exclusive-or gates K70, K70 and K70 are respectively connected with the input end of a four-input-exclusive-or gate K70 and an output end of a four-input-output end of a module K70.
Error correction and detection coding module eight coding and decoding module input ends A <35:0> are connected to input ends DI <63:0> according to the coding sequence designed by the invention, thereby realizing the following coding logic:
the coding logic is as follows:
DIP<0>＝DI<0>⊕DI<1>⊕DI<3>⊕DI<4>⊕DI<6>⊕DI<8>⊕DI<10>⊕DI<11>⊕DI<13>⊕DI<15>⊕DI<17>⊕DI<19>⊕DI<21>⊕DI<23>⊕DI<25>⊕DI<26>⊕DI<28>⊕DI<30>⊕DI<32>⊕DI<34>⊕DI<36>⊕DI<38>⊕DI<40>⊕DI<42>⊕DI<44>⊕DI<46>⊕DI<48>⊕DI<50>⊕DI<52>⊕DI<54>⊕DI<56>⊕DI<57>⊕DI<59>⊕DI<61>⊕DI<63>
DIP<1>＝DI<0>⊕DI<2>⊕DI<3>⊕DI<5>⊕DI<6>⊕DI<9>⊕DI<10>⊕DI<12>⊕DI<13>⊕DI<16>⊕DI<17>⊕DI<20>⊕DI<21>⊕DI<24>⊕DI<25>⊕DI<27>⊕DI<28>⊕DI<31>⊕DI<32>⊕DI<35>⊕DI<36>⊕DI<39>⊕DI<40>⊕DI<43>⊕DI<44>⊕DI<47>⊕DI<48>⊕DI<51>⊕DI<52>⊕DI<55>⊕DI<56>⊕DI<58>⊕DI<59>⊕DI<62>⊕DI<63>
DIP<2>＝DI<1>⊕DI<2>⊕DI<3>⊕DI<7>⊕DI<8>⊕DI<9>⊕DI<10>⊕DI<14>⊕DI<15>⊕DI<16>⊕DI<17>⊕DI<22>⊕DI<23>⊕DI<24>⊕DI<25>⊕DI<29>⊕DI<30>⊕DI<31>⊕DI<32>⊕DI<37>⊕DI<38>⊕DI<39>⊕DI<40>⊕DI<45>⊕DI<46>⊕DI<47>⊕DI<48>⊕DI<53>⊕DI<54>⊕DI<55>⊕DI<56>⊕DI<60>⊕DI<61>⊕DI<62>⊕DI<63>
DIP<3>＝DI<4>⊕DI<5>⊕DI<6>⊕DI<7>⊕DI<8>⊕DI<9>⊕DI<10>⊕DI<18>⊕DI<19>⊕DI<20>⊕DI<21>⊕DI<22>⊕DI<23>⊕DI<24>⊕DI<25>⊕DI<33>⊕DI<34>⊕DI<35>⊕DI<36>⊕DI<37>⊕DI<38>⊕DI<39>⊕DI<40>⊕DI<49>⊕DI<50>⊕DI<51>⊕DI<52>⊕DI<53>⊕DI<54>⊕DI<55>⊕DI<56>
DIP<4>＝DI<11>⊕DI<12>⊕DI<13>⊕DI<14>⊕DI<15>⊕DI<16>⊕DI<17>⊕DI<18>⊕DI<19>⊕DI<20>⊕DI<21>⊕DI<22>⊕DI<23>⊕DI<24>⊕DI<25>⊕DI<41>⊕DI<42>⊕DI<43>⊕DI<44>⊕DI<45>⊕DI<46>⊕DI<47>⊕DI<48>⊕DI<49>⊕DI<50>⊕DI<51>⊕DI<52>⊕DI<53>⊕DI<54>⊕DI<55>⊕DI<56>
DIP<5>＝DI<26>⊕DI<27>⊕DI<28>⊕DI<29>⊕DI<30>⊕DI<31>⊕DI<32>⊕DI<33>⊕DI<34>⊕DI<35>⊕DI<36>⊕DI<37>⊕DI<38>⊕DI<39>⊕DI<40>⊕DI<41>⊕DI<42>⊕DI<43>⊕DI<44>⊕DI<45>⊕DI<46>⊕DI<47>⊕DI<48>⊕DI<49>⊕DI<50>⊕DI<51>⊕DI<52>⊕DI<53>⊕DI<54>⊕DI<55>⊕DI<56>
DIP<6>＝DI<57>⊕DI<58>⊕DI<59>⊕DI<60>⊕DI<61>⊕DI<62>⊕DI<63>
DIP<7>＝DI<0>⊕DI<1>⊕DI<2>⊕DI<4>⊕DI<5>⊕DI<7>⊕DI<10>⊕DI<11>⊕DI<12>⊕DI<14>⊕DI<17>⊕DI<18>⊕DI<21>⊕DI<23>⊕DI<24>⊕DI<26>⊕DI<27>⊕DI<29>⊕DI<32>⊕DI<33>⊕DI<36>⊕DI<38>⊕DI<39>⊕DI<41>⊕DI<44>⊕DI<46>⊕DI<47>⊕DI<50>⊕DI<51>⊕DI<53>⊕DI<56>⊕DI<57>⊕DI<58>⊕DI<60>⊕DI<63>。
error correction and detection decoding module the inputs a <35:0> of the nine codec modules are connected to the inputs DI1<63:0> and DIP1<7:0> in the coding order according to the invention, thus forming the following decoding logic:
as follows:
DCHECK<0>＝DI1<0>⊕DI1<1>⊕DI1<3>⊕DI1<4>⊕DI1<6>⊕DI1<8>⊕DI1<10>⊕DI1<11>⊕DI1<13>⊕DI1<15>⊕DI1<17>⊕DI1<19>⊕DI1<21>⊕DI1<23>⊕DI1<25>⊕DI1<26>⊕DI1<28>⊕DI1<30>⊕DI1<32>⊕DI1<34>⊕DI1<36>⊕DI1<38>⊕DI1<40>⊕DI1<42>⊕DI1<44>⊕DI1<46>⊕DI1<48>⊕DI1<50>⊕DI1<52>⊕DI1<54>⊕DI1<56>⊕DI1<57>⊕DI1<59>⊕DI1<61>⊕DI1<63>⊕DIP1<0>
DCHECK<1>＝DI1<0>⊕DI1<2>⊕DI1<3>⊕DI1<5>⊕DI1<6>⊕DI1<9>⊕DI1<10>⊕DI1<12>⊕DI1<13>⊕DI1<16>⊕DI1<17>⊕DI1<20>⊕DI1<21>⊕DI1<24>⊕DI1<25>⊕DI1<27>⊕DI1<28>⊕DI1<31>⊕DI1<32>⊕DI1<35>⊕DI1<36>⊕DI1<39>⊕DI1<40>⊕DI1<43>⊕DI1<44>⊕DI1<47>⊕DI1<48>⊕DI1<51>⊕DI1<52>⊕DI1<55>⊕DI1<56>⊕DI1<58>⊕DI1<59>⊕DI1<62>⊕DI1<63>⊕DIP1<1>
DCHECK<2>＝DI1<1>⊕DI1<2>⊕DI1<3>⊕DI1<7>⊕DI1<8>⊕DI1<9>⊕DI1<10>⊕DI1<14>⊕DI1<15>⊕DI1<16>⊕DI1<17>⊕DI1<22>⊕DI1<23>⊕DI1<24>⊕DI1<25>⊕DI1<29>⊕DI1<30>⊕DI1<31>⊕DI1<32>⊕DI1<37>⊕DI1<38>⊕DI1<39>⊕DI1<40>⊕DI1<45>⊕DI1<46>⊕DI1<47>⊕DI1<48>⊕DI1<53>⊕DI1<54>⊕DI1<55>⊕DI1<66>⊕DI1<60>⊕DI1<61>⊕DI1<62>⊕DI1<63>⊕DIP1<2>
DCHECK<3>＝DI1<4>⊕DI1<5>⊕DI1<6>⊕DI1<7>⊕DI1<8>⊕DI1<9>⊕DI1<10>⊕DI1<18>⊕DI1<19>⊕DI1<20>⊕DI1<21>⊕DI1<22>⊕DI1<23>⊕DI1<24>⊕DI1<25>⊕DI1<33>⊕DI1<34>⊕DI1<35>⊕DI1<36>⊕DI1<37>⊕DI1<38>⊕DI1<39>⊕DI1<40>⊕DI1<49>⊕DI1<50>⊕DI1<51>⊕DI1<52>⊕DI1<53>⊕DI1<54>⊕DI1<55>⊕DI1<56>⊕DIP1<3>
DCHECK<4>＝DI1<11>⊕DI1<12>⊕DI1<13>⊕DI1<14>⊕DI1<15>⊕DI1<16>⊕DI1<17>⊕DI1<18>⊕DI1<19>⊕DI1<20>⊕DI1<21>⊕DI1<22>⊕DI1<23>⊕DI1<24>⊕DI1<25>⊕DI1<41>⊕DI1<42>⊕DI1<43>⊕DI1<44>⊕DI1<45>⊕DI1<46>⊕DI1<47>⊕DI1<48>⊕DI1<49>⊕DI1<50>⊕DI1<51>⊕DI1<52>⊕DI1<53>⊕DI1<54>⊕DI1<55>⊕DI1<56>⊕DIP1<4>
DCHECK<5>＝DI1<26>⊕DI1<27>⊕DI1<28>⊕DI1<29>⊕DI1<30>⊕DI1<31>⊕DI1<32>⊕DI1<33>⊕DI1<34>⊕DI1<35>⊕DI1<36>⊕DI1<37>⊕DI1<38>⊕DI1<39>⊕DI1<40>⊕DI1<41>⊕DI1<42>⊕DI1<43>⊕DI1<44>⊕DI1<45>⊕DI1<46>⊕DI1<47>⊕DI1<48>⊕DI1<49>⊕DI1<50>⊕DI1<51>⊕DI1<52>⊕DI1<53>⊕DI1<54>⊕DI1<55>⊕DI1<56>⊕DIP1<5>
DCHECK<6>＝DI1<57>⊕DI1<58>⊕DI1<59>⊕DI1<60>⊕DI1<61>⊕DI1<62>⊕DI1<63>⊕DIP1<6>
DBITERR＝DI1<0>⊕DI1<2>⊕DI1<4>⊕DI1<6>⊕DI1<8>⊕DI1<10>⊕DI1<12>⊕DI1<14>⊕DI1<16>⊕DI1<18>⊕DI1<20>⊕DI1<22>⊕DI1<24>⊕DI1<26>⊕DI1<28>⊕DI1<30>⊕DI1<32>⊕DI1<34>⊕DI1<36>⊕DI1<38>⊕DI1<40>⊕DI1<42>⊕DI1<44>⊕DI1<46>⊕DI1<48>⊕DI1<50>⊕DI1<52>⊕DI1<54>⊕DI1<56>⊕DI1<58>⊕DI1<60>⊕DI1<62>⊕DIP1<0>⊕DIP1<2>⊕DIP1<4>⊕DIP1<6>⊕DI1<1>⊕DI1<3>⊕DI1<5>⊕DI1<7>⊕DI1<9>⊕DI1<11>⊕DI1<13>⊕DI1<15>⊕DI1<17>⊕DI1<19>⊕DI1<21>⊕DI1<23>⊕DI1<25>⊕DI1<27>⊕DI1<29>⊕DI1<31>⊕DI1<33>⊕DI1<35>⊕DI1<37>⊕DI1<39>⊕DI1<41>⊕DI1<43>⊕DI1<45>⊕DI1<47>⊕DI1<49>⊕DI1<51>⊕DI1<53>⊕DI1<55>⊕DI1<57>⊕DI1<59>⊕DI1<61>⊕DI1<63>⊕DIP1<1>⊕DIP1<3>⊕DIP1<5>⊕DIP1<7>。
when there is a bit error in the input data, according to the logic above, SBITERR output 1, DCHECK <6:0> outputs the error location in BCD code form, e.g., DCHECK <6:0> outputs 0000011, indicating the fourth bit of the input data, i.e., DI1<3> error.
When there is a two-bit error in the input data, DBITERR outputs 1.
The error detection and correction circuit can be configured to only use the error detection and correction decoding module or only use the error detection and correction coding module according to the needs of users, or can be fully used, so that better flexibility is realized.
Claims (7)
1. An optional bit width error correction and detection circuit for a single event upset resistant memory is characterized in that: the device comprises an error correction and detection coding module and an error correction and detection decoding module;
error correction and detection coding module: the method can carry out check code encoding operation on input data with the bit width of 11-64, generate 8-bit check codes for carrying out error correction and detection on the data, and output the check codes and the input data to an error correction and detection decoding module;
and the error correction and detection decoding module: the error correction coding module can decode and check the data signal from the error correction coding module, output a one-bit error prompt and an error position when one-bit error exists in the data signal, correct the error and output a two-bit error prompt when two-bit error exists in the data signal;
the error detection and correction coding module is provided with 64 data input ports DI <63:0> and 4 control ports CLK, EN, S <1:0> and 8 data output ports DIP <7:0>, the control ports S <1:0> are bit width selection ports, and input data with 11-64 bit widths are coded by setting the value of S <1:0 >;
the control port CLK is used for providing a clock for an output register in the error correction and detection coding module, the control port EN is used for providing an enabling signal for the output register in the error correction and detection coding module, when EN is 1 and CLK is square wave, the error correction and detection coding module is enabled, all ports are effective, when EN is 0 and CLK is constant 0 or constant 1, the error correction and detection coding module is disabled, and all ports are invalid;
the specific way of encoding the input data with 11-64 bit width by setting the value of S <1:0> is as follows:
when S <1> and S <0> are both 1, the error correction and detection coding module can code data with a bit width of 58-64, DI <63:0> is valid at the moment, and DIP <7:0> outputs 8-bit check codes; when S <1> is 1 and S <0> is 0, the error correction and detection coding module can code data with the bit width of 27-57, and at the moment, DI <56:0> is valid, DI <63:57> is invalid, DIP <5:0> outputs the valid bit of the check code, and DIP <7:6> is set to be 0; when S <1> is 0 and S <0> is 1, the error correction and detection coding module can code data with 12-26 bit width, at the moment, DI <25:0> is valid, DI <63:26> is invalid, DIP <4:0> outputs the valid bit of the check code, and DIP <7:5> is set to be 0; when S <1> and S <0> are both 0, the error correction and detection coding module can code data within 11 bit width, at the moment, DI <10:0> is valid, DI <63:11> is invalid, DIP <4:0> outputs the valid bit of the check code, and DIP <7:5> is set to be 0.
2. The optional bit width error detection and correction circuit for the single event upset resistant memory according to claim 1, wherein:
the error correction and detection coding module comprises a first coding and decoding module K15, a second coding and decoding module K16, a third coding and decoding module K17, a fourth coding and decoding module K18, a fifth coding and decoding module K19, a sixth coding and decoding module K20, a seventh coding and decoding module K21, an eighth coding and decoding module K22, eight output registers, nine AND gates and one OR gate K39;
the eight output registers are respectively an output register K23, an output register K24, an output register K25, an output register K26, an output register K27, an output register K28, an output register K29 and an output register K30;
the nine AND gates are respectively an AND gate K31, an AND gate K32, an AND gate K33, an AND gate K34, an AND gate K35, an AND gate K36, an AND gate K37, an AND gate K38 and an AND gate K40;
the input terminals A <35:0> are connected to the input terminals DI <63:0> according to different coding orders;
the connection relationship is as follows:
the 36 input interfaces of the input terminals A <35:0> of the first codec module K15 are respectively connected to DI <0>, DI <1>, DI <3>, DI <4>, DI <6>, DI <8>, DI <10>, DI <11>, DI <13>, DI <15>, DI <17>, DI <19>, DI <21>, DI <23>, DI <25>, DI <26>, DI <28>, DI <30>, DI <32>, DI <34>, DI <36>, DI <38>, DI <40>, DI <42>, DI <44>, DI <46>, DI <48>, DI <50>, DI <52>, DI <54>, DI <56>, DI <57>, DI <59>, DI <61>, DI <63>, and GND;
the 36 input interfaces of the input terminals A <35:0> of the second codec module K16 are respectively connected to DI <0>, DI <2>, DI <3>, DI <5>, DI <6>, DI <9>, DI <10>, DI <12>, DI <13>, DI <16>, DI <17>, DI <20>, DI <21>, DI <24>, DI <25>, DI <27>, DI <28>, DI <31>, DI <32>, DI <35>, DI <36>, DI <39>, DI <40>, DI <43>, DI <44>, DI <47>, DI <48>, DI <51>, DI <52>, DI <55>, DI <56>, DI <58>, DI <59>, DI <62>, DI <63>, and GND;
the 36 input interfaces of the input terminals A <35:0> of the third codec module K17 are respectively connected to DI <1>, DI <2>, DI <3>, DI <7>, DI <8>, DI <9>, DI <10>, DI <14>, DI <15>, DI <16>, DI <17>, DI <22>, DI <23>, DI <24>, DI <25>, DI <29>, DI <30>, DI <31>, DI <32>, DI <37>, DI <38>, DI <39>, DI <40>, DI <45>, DI <46>, DI <47>, DI <48>, DI <53>, DI <54>, DI <55>, DI <66>, DI <60>, DI <61>, DI <62>, DI <63>, and GND;
the 36 input interfaces of the input terminals A <35:0> of the fourth codec module K18 are respectively connected to DI <4>, DI <5>, DI <6>, DI <7>, DI <8>, DI <9>, DI <10>, DI <18>, DI <19>, DI <20>, DI <21>, DI <22>, DI <23>, DI <24>, DI <25>, DI <33>, DI <34>, DI <35>, DI <36>, DI <37>, DI <38>, DI <39>, DI <40>, DI <49>, DI <50>, DI <51>, DI <52>, DI <53>, DI <54>, DI <55>, DI <56>, GND;
the 36 input interfaces of the input terminals A <35:0> of the fifth codec module K19 are respectively connected to DI <11>, DI <12>, DI <13>, DI <14>, DI <15>, DI <16>, DI <17>, DI <18>, DI <19>, DI <20>, DI <21>, DI <22>, DI <23>, DI <24>, DI <25>, DI <41>, DI <42>, DI <43>, DI <44>, DI <45>, DI <46>, DI <47>, DI <48>, DI <49>, DI <50>, DI <51>, DI <52>, DI <53>, DI <54>, DI <55>, DI <56>, GND;
the 36 input interfaces of the input terminals A <35:0> of the sixth codec module K20 are respectively connected to DI <26>, DI <27>, DI <28>, DI <29>, DI <30>, DI <31>, DI <32>, DI <33>, DI <34>, DI <35>, DI <36>, DI <37>, DI <38>, DI <39>, DI <40>, DI <41>, DI <42>, DI <43>, DI <44>, DI <45>, DI <46>, DI <47>, DI <48>, DI <49>, DI <50>, DI <51>, DI <52>, DI <53>, DI <54>, DI <55>, DI <56>, GND;
36 input interfaces of input ends A <35:0> of the seventh codec module K21 are respectively connected with DI <57>, DI <58>, DI <59>, DI <60>, DI <61>, DI <62>, DI <63>, GND;
the eight codec module K22 has 36 input ports for input terminals A <35:0> respectively connected to DI <0>, DI <1>, DI <2>, DI <4>, DI <5>, DI <7>, DI <10>, DI <11>, DI <12>, DI <14>, DI <17>, DI <18>, DI <21>, DI <23>, DI <24>, DI <26>, DI <27>, DI <29>, DI <32>, DI <33>, DI <36>, DI <38>, DI <39>, DI <41>, DI <44>, DI <46>, DI <47>, DI <50>, DI <51>, DI <53>, DI <56>, DI <57>, DI <58>, DI <60>, DI <63>, and GND;
the data input ends D of the eight output registers are correspondingly connected with the output ends ZN of the eight encoding and decoding modules one by one, the control ends CLK of the eight output registers are all connected to the control ports CLK of the error correction and detection encoding modules, the control ends EN of the eight output registers are all connected to the control ports EN of the error correction and detection encoding modules, the eight output registers are in one-to-one correspondence with the eight AND gates, the output end Q of each output register is connected to one input end of the corresponding AND gate, the other input ends of the AND gate K31, the AND gate K32, the AND gate K33 and the AND gate K34 are all connected with VCC, the other input end of the AND gate K35 is connected with the output end of the OR gate K39, or the two input ends of the OR gate K39 are respectively connected with the control ports S <1:0 >; the other input end of the AND gate K36 is connected with a control port S <1>, the other input ends of the AND gate K37 and the AND gate K38 are connected with the output end of the AND gate K40, the two input ends of the AND gate K40 are respectively connected with control ends S <1:0>, and the output ends of the AND gates K31 to K38 are used as DIP <7:0 >.
3. The optional bit width error detection and correction circuit for the single event upset resistant memory according to claim 2, wherein: the first codec module K15, the second codec module K16, the third codec module K17, the fourth codec module K18, the fifth codec module K19, the sixth codec module K20, the seventh codec module K21 and the eighth codec module K22 in the error detection and correction coding module have the same circuit structure, and are all codec modules formed by exclusive or gates.
4. The optional bit width error detection and correction circuit for the single event upset resistant memory according to claim 1, wherein: the error detection and correction decoding module comprises 72 data input ports of DI1<63:0>, DIP1<7:0> and 2 control ports of CLK1 and EN1, 7 error correction signal output ports of DCHECK <6:0> and 2 error flag bit ports of SBITERR and DBITERR;
the control port CLK1 is used for providing a clock for an output register in the error detection and correction decoding module, the EN1 is used for providing an enabling signal for the output register in the error detection and correction decoding module, the error flag bit ports SBITERR and DBITERR are both valid when EN1 is 1 and CLK1 is square wave, and the error flag bit ports SBITERR and DBITERR are both invalid when EN1 is 0 and CLK1 is constant 0 or constant 1; the input port DI1<63:0> is used for inputting data, the DIP1<7:0> is used for inputting check bits, when the error correction detection decoding module finds a bit error in the input data, DCHECK <6:0> outputs the error position in the form of BCD code, SBITERR is set and output, and when two bit errors are found, DBITERR is set and output.
5. The optional bit width error detection and correction circuit for the single event upset resistant memory according to claim 4, wherein: the error detection and correction decoding module comprises nine coding and decoding modules, a seven-input OR gate K50, a NAND gate K51, an XOR gate K52, an output register K53 and an output register K54; the nine codec modules are respectively a ninth codec module K41, a tenth codec module K42, an eleventh codec module K43, a twelfth codec module K44, a thirteenth codec module K45, a fourteenth codec module K46, a fifteenth codec module K47, a sixteenth codec module K48 and a seventeenth codec module K49;
the input terminals A <35:0> of the nine codec modules are connected to the input terminals DI1<63:0> and DIP1<7:0> according to different coding orders, and the connection relationship is as follows:
the ninth codec module K has 36 input ports at input terminals A <35:0> respectively connected to DI <0>, DI <1>, DI <3>, DI <4>, DI <6>, DI <8>, DI <10>, DI <11>, DI <13>, DI <15>, DI <17>, DI <19>, DI <21>, DI <23>, DI <25>, DI <26>, DI <28>, DI <30>, DI <32>, DI <34>, DI <36>, DI <38>, DI <40>, DI <42>, DI <44>, DI <46>, DI <48>, DI <50>, DI <52>, DI <54>, DI <56>, DI <57>, DI <59>, DI <61>, DI <63>, DIP <0 >;
the 36 input interfaces of the input terminals A <35:0> of the tenth codec module K are connected to DI <0>, DI <2>, DI <3>, DI <5>, DI <6>, DI <9>, DI <10>, DI <12>, DI <13>, DI <16>, DI <17>, DI <20>, DI <21>, DI <24>, DI <25>, DI <27>, DI <28>, DI <31>, DI <32>, DI <35>, DI <36>, DI <39>, DI <40>, DI <43>, DI <44>, DI <47>, DI <48>, DI <51>, DI <52>, DI <55>, DI <56>, DI <58>, DI <59>, DI <62>, DI <63>, DIP <1>, respectively;
the eleventh codec module K has 36 input ports at input terminals A <35:0> respectively connected to DI <1>, DI <2>, DI <3>, DI <7>, DI <8>, DI <9>, DI <10>, DI <14>, DI <15>, DI <16>, DI <17>, DI <22>, DI <23>, DI <24>, DI <25>, DI <29>, DI <30>, DI <31>, DI <32>, DI <37>, DI <38>, DI <39>, DI <40>, DI <45>, DI <46>, DI <47>, DI <48>, DI <53>, DI <54>, DI <55>, DI <66>, DI <60>, DI <61>, DI <62>, DI <63>, DIP <2 >;
the 36 input interfaces of the input terminals a <35:0> of the twelfth codec module K44 are respectively connected to DI 44 <4>, DI 44 <5>, DI 44 <6>, DI 44 <7>, DI 44 <8>, DI 44 <9>, DI 44 <10>, DI 44 <18>, DI 44 <19>, DI 44 <20>, DI 44 <21>, DI 44 <22>, DI 44 <23>, DI 44 <24>, DI 44 <25>, DI 44 <33>, DI 44 <34>, DI 44 <35>, DI 44 <36>, DI 44 <37>, DI 44 <38>, DI 44 <39>, DI 44 <40>, DI 44 <49>, DI 44 <50>, DI 44 <52>, DI 44 <53>, DI 44 <54>, DI 44 < 72 >, DI 44 < 72 > and DI GND, DI 3 < 72 > respectively;
the 36 input interfaces of the inputs A <35:0> of the thirteenth codec module K45 are respectively connected to DI 45 <11>, DI 45 <12>, DI 45 <13>, DI 45 <14>, DI 45 <15>, DI 45 <16>, DI 45 <17>, DI 45 <18>, DI 45 <19>, DI 45 <20>, DI 45 <21>, DI 45 <22>, DI 45 <23>, DI 45 <24>, DI 45 <25>, DI 45 <41>, DI 45 <42>, DI 45 <43>, DI 45 <44>, DI 45 <45>, DI 45 <46>, DI 45 <47>, DI 45 <48>, DI 45 <49>, DI 45 <50>, DI 45 <52>, DI 45 <53>, DI <45>, DI < 72 >, DI <45>, DI 45 < 72 >, DI <45>, DI < 72 >, GND >, DI 45 <45>, GND, DI < 72 >, GND >, DI 45 < 72 > and GND <55> and GND < 72 > 45;
the 36 input interfaces of the input terminals a <35:0> of the fourteenth codec module K46 are respectively connected to DI 46 <26>, DI 46 <27>, DI 46 <28>, DI 46 <29>, DI 46 <30>, DI 46 <31>, DI 46 <32>, DI 46 <33>, DI 46 <34>, DI 46 <35>, DI 46 <36>, DI 46 <37>, DI 46 <38>, DI 46 <39>, DI 46 <40>, DI 46 <41>, DI 46 <42>, DI 46 <43>, DI 46 <44>, DI 46 <45>, DI 46 <46>, DI 46 <47>, DI 46 <48>, DI 46 <49>, DI 46 <50>, DI 46 <52>, DI 46 <53>, DI 46 < 72 >, DI 46 < 72 > and DI GND, DI 46 < 72 > respectively;
36 input interfaces of input ends A <35:0> of the fifteenth codec module K47 are respectively connected with DI1<57>, DI1<58>, DI1<59>, DI1<60>, DI1<61>, DI1<62>, DI1<63>, DIP1<6>, GND;
the sixteenth codec module K has 36 input interfaces at input terminals A <35:0> respectively connected to DI <0>, DI <2>, DI <4>, DI <6>, DI <8>, DI <10>, DI <12>, DI <14>, DI <16>, DI <18>, DI <20>, DI <22>, DI <24>, DI <26>, DI <28>, DI <30>, DI <32>, DI <34>, DI <36>, DI <38>, DI <40>, DI <42>, DI <44>, DI <46>, DI <48>, DI <50>, DI <52>, DI <54>, DI <56>, DI <58>, DI <60>, DI <62>, DIP <0>, DIP <2>, DIP <4> and DIP <6 >;
36 input interfaces of the input terminals A <35:0> of the seventeenth codec module K are connected to DI <1>, DI <3>, DI <5>, DI <7>, DI <9>, DI <11>, DI <13>, DI <15>, DI <17>, DI <19>, DI <21>, DI <23>, DI <25>, DI <27>, DI <29>, DI <31>, DI <33>, DI <35>, DI <37>, DI <39>, DI <41>, DI <43>, DI <45>, DI <47>, DI <49>, DI <51>, DI <53>, DI <55>, DI <57>, DI <59>, DI <61>, DI <63>, DIP <1>, DIP <3>, DIP <5> and DIP <7>, respectively;
the output ends ZN of the ninth codec module K41, the tenth codec module K42, the eleventh codec module K43, the twelfth codec module K44, the thirteenth codec module K45, the fourteenth codec module K46 and the fifteenth codec module K47 are used as output ends DCHECK <0:6> and are simultaneously connected to the input ends of a seven-input OR gate K50, the output end of the seven-input OR gate K50 is connected to one input end of a NAND gate K51, two input ends of an XOR gate K52 are respectively connected to the output end of the sixteenth codec module K48 and the output end of the seventeenth codec module K49, the output end of the XOR gate K52 is simultaneously connected to the other input end of the NAND gate K51 and the data input end D of the output register K54, the output end of the NAND gate K51 is connected to the data input end D of the output register K53, the control ends of the output registers K53 and K54 are connected to the control ports CLK1 of the error detection and detection modules, the control terminals EN of the output registers K53 and K54 are all connected to a control port EN1 of the error correction and detection decoding module, the output terminal of the output register K53 is used as an error flag bit port SBITERR of the error correction and detection decoding module, and the output terminal of the output register K54 is used as an error flag bit port DBITERR of the error correction and detection decoding module.
6. The optional bit width error detection and correction circuit for the single event upset resistant memory according to claim 5, wherein: the ninth codec module K41, the tenth codec module K42, the eleventh codec module K43, the twelfth codec module K44, the thirteenth codec module K45, the fourteenth codec module K46, the fifteenth codec module K47, the sixteenth codec module K48, and the seventeenth codec module K49 in the error detection and correction decoding modules have the same circuit structure, and are all codec modules formed by exclusive or gates.
7. The optional bit width error correction and detection circuit for the single event upset resistant memory according to claim 3 or 6, wherein: the encoding and decoding module formed by the exclusive-OR gates comprises three input exclusive-OR gates K55, K56, K57, K58, K59, K60, K61, K62, K63, K64, K65, K66, K67, K68, K69 and K70, a four input exclusive-OR gate K71 and an inverter K72;
three input ends of three-input exclusive-or gates K55, K56, K57, K59, K60, K61, K63, K64, K65, K67, K68 and K69 are sequentially connected with an input end A <0:35> of the encoding and decoding module, outputs of three-input exclusive-or gates K55, K56 and K57 are used as three inputs of a three-input exclusive-or gate K58, outputs of three-input exclusive-or gates K59, K60 and K61 are used as three inputs of a three-input exclusive-or gate K62, outputs of three-input exclusive-or gates K63, K64 and K65 are used as three inputs of a three-input exclusive-or gate K66, outputs of three-input exclusive-or gates K67, K68 and K69 are used as three inputs of a three-input exclusive-or gate K70, outputs of a four-input exclusive-or gate K70, a four-input output of an exclusive-or gate ZN 70 and a four-input output of the encoding and decoding module 70.
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| WO2014115289A1 (en) * | 2013-01-25 | 2014-07-31 | 株式会社日立製作所 | Programmable device and electronic syst em device |
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