CN104409103A - Novel two-dimensional coding reinforcing method and circuit arrangement for aerospace memory - Google Patents
Novel two-dimensional coding reinforcing method and circuit arrangement for aerospace memory Download PDFInfo
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Abstract
A two-dimensional coding reinforcing method for aerospace memories. Low-complexity multiple bit error detection and correction method is introduced into the reinforcing method, and the multiple bit error detection and correction method can carry out detection and correction on arbitrary multiple bit error. The reinforcing method comprises the following steps: 1, reading the word width of the memory, and logically converting a word with width N into a (k1, k2) two-dimensional matrix form; 2, determining the line number k1 and the column number k2 of the two-dimensional matrix; 3, adding a horizontal error detection code in each line, adding a vertical parity check code in each column; 4, when a word in the memory occurs multiple bit upsets, indicating the row and column the error respectively by the horizontal error detection code and the vertical parity check code; and when the interval of discontinuous multiple bit errors is less than L, giving a wrong signal by the horizontal error detection code; and 5, according to the amendment information bit, amending the information bits, and completing the amendment.
Description
Technical field
The present invention relates to the two-dimensional encoded reinforcement means of a kind of aerospace storer and circuit arrangement.
Background technology
Along with the reduction of integrated circuit technology size and supply voltage, the soft error that storer produces space radiation environment and surface noise environment is more responsive than ever.Storer occupies the chip area of integrated circuit (IC) system more than 60%, and in system, the inefficacy of the overwhelming majority is caused by storer, is therefore improve one of integrated circuit (IC) system reliability of paramount importance approach to the research of storer reinforcement technique.Charged high energy particle, proton and neutron in space environment, and the α particle in ground environment may produce single-particle inversion (single event upsets) and Multiple-bit upsets (multiple bit upsets) to storer, thus impact stores the correctness of data
].When integrated circuit technology size is reduced to below deep-submicron (<0.18 μm), storer can not increase significantly by the impact of single-particle inversion, but trends towards saturated.But after process reduces, same semiconductor crystal wafer can place more storage unit, and the distance between adjacent cells constantly reduces.Therefore the probability that storer is subject to Multiple-bit upsets substantially increases.
Hamming code is a kind of reinforcement technique the most conventional in storer.But Hamming code can only be revised one, detect two bit-errors, cannot revise the Multiple-bit upsets occurred in storer.
Domain bit interleave technology can reduce the Multiple-bit upsets in storer, and it is that the bit location on different word is distributed into unit adjacent in physical layout structure, thus avoids the multiple bit locations on a word to overturn simultaneously.But there is certain restriction and defect in domain bit interleave technology: bit interleave technology makes the word of storer and column selection connect up elongated, passive impact is caused on area, data time and power consumption, and when staggered figure place increases, the problems referred to above can be more obvious.
Another kind can suppress the method for Multiple-bit upsets to be multi-bit error correcting code technology.BCH code, RS code and hybrid code etc., can revise the Multiple-bit upsets occurred in storer.The usual defect of these methods needs a large amount of delays, power consumption and area overhead.In addition, their coding&decoding circuit is more complicated, needs with the multiplying of the mode process higher-order domain of look-up table.
Built-in current probe (Built in current sensors) coordinates the method for Hamming code or parity check code also can revise Multiple-bit upsets in storer.But this method needs all to add a built-in current probe to each row of storer, and built-in current probe itself is also responsive to soft error, may introduce extra mistake.In addition, the method also needs multiple cycle to complete location and the correction of mistake, and is not suitable for the practical application of high-speed memory.
Two dimension correcting code can suppress the Multiple-bit upsets in storer effectively, thus improves the reliability of storer.Two dimension correcting code, by adding the error code of level to every a line of storer, arranges to each of storer the mode adding vertical error code simultaneously and constructs.In prior art, when a word needs write storage array, first must read corresponding position from every a line, upgrade vertical error code, which significantly increases access delay and power consumption.In prior art, the scheme of proposition can only be revised two bit-errors.When emittance increases further, they cannot revise more mistake.
Summary of the invention
In order to overcome the deficiencies in the prior art, the present invention proposes a kind of two-dimentional correcting code of novelty, and devise effective storer Multiple-bit upsets Scheme of Strengthening, it, by lower hardware spending, achieves the correction to any given width Multiple-bit upsets.
Technical solution of the present invention is:
The two-dimensional encoded reinforcement means of a kind of aerospace storer, described reinforcement means introduces a kind of multi-bit error detection and modification method of low complex degree, and described multi-bit error detection and modification method can detect any multi-bit error and revise.
Described reinforcement means step is as follows:
Step 1, reads in the width of memory word, on logic connects a bit wide is
nword be converted into one (
k1,
k2) two-dimensional matrix form,
k1represent line number,
k2represent columns.
Step 2, determines the line number of two-dimensional matrix
k1and columns
k2.
Step 3, inserts horizontal error acquisition code and vertical check code.Every a line adds horizontal error acquisition code, and each row adds vertical parity effect code;
Step 4, after a word generation Multiple-bit upsets of storer, the row and column that described horizontal error acquisition code and vertical check code difference misdirection occur, when the interval of discontinuous multi-bit error is less than
ltime, although the number judging mistake that described horizontal error acquisition code can not be correct, a rub-out signal still can be provided.The column position of the line position utilizing this rub-out signal to indicate and parity check code instruction, no matter be that continuous mistake or discontinuous mistake can be located, and is revised by the value overturning self.
Step 5, according to the information bit revised
revise the information bit at place
, revise complete.
The invention allows for a kind of two-dimentional correcting code of the two-dimensional encoded reinforcement means of above-mentioned aerospace storer that adopts and reinforce memory circuitry, as shown in Figure 6, it comprises scrambler, code translator, storer and MUX,
As shown in Figure 4, described scrambler writes Verilog codes implement by the calculating formula of the data of the storage of each detecting position described and check bit, 8 groups of XOR are for generating the acquisition code of horizontal error acquisition code in the encoder, 16 groups of buffer are for strengthening the driving force of data input pin to memory module, and other 8 groups of XOR are for generating the check bit of vertical check code.
As shown in Figure 5, described code translator is by writing Verilog codes implement, detecting position
d i 'and check bit
c i 'generated by 8 groups of XOR respectively, through decision logic, export correct data finally by 16 groups of XOR.
Described MUX has 16 data test ports and a test enable port, can reinforce memory circuitry and carry out correction test, be specially: first, in the normal mode of operation to storer write data by described MUX to two-dimentional correcting code; Subsequently, test enable end is set to effectively, enters test pattern, and input test data are modified to the data stored under normal mode of operation; Finally, read the data of write, compare Output rusults whether consistent with the data write under normal mode of operation.If export data and write data consistent, then show that described two-dimentional correcting code reinforces memory circuitry effective.
Described storer adopts domain split plot design to design, described figure split plot design considers the physical sequential of storage unit domain, avoid the data bit of operation relation too close with redundant digit when logic inputs, carry out segmentation to it to put, as shown in Figure 2, be specially: utilize information bit to cut horizontal error acquisition code and vertical check code; Information bit and should have mutually the check bit sum of operation relation detect the distance of positions be greater than from needs
l, with guarantee information position and have the redundant digit of operation relation to make a mistake simultaneously.
The present invention's beneficial effect is compared with prior art:
First, in order to avoid the problem of vertical codes continuous updating, the present invention splits into the form of a two-dimensional matrix the word of storer.Secondly, in order to reduce the hardware spending of Scheme of Strengthening, employ multi-bit error detection and the modification method of low complex degree, it can detect arbitrary mistake continuously.By the mode combined with vertical check code, the two-dimentional correcting code of proposition both can revise continuous print multi-bit error, can revise discontinuous multi-bit error again.Subsequently, the correction algorithm of storer Multiple-bit upsets is given.Finally, circuit and layout design has been carried out to the scheme proposed, and propose one " domain split plot design ", utilize the domain structure of storage unit to restrained effectively the Multiple-bit upsets that may occur in the redundant digit of two-dimentional correcting code, further increase the reliability of storer.Therefore, relative to other multi-bit error correction code, the storer Multiple-bit upsets of proposition is reinforced circuit and is obviously had higher reliability and lower hardware spending.
Accompanying drawing explanation
Fig. 1 is the two-dimentional correcting code of data width 16;
Fig. 2 is several type of errors occurred in storer;
Fig. 3 is the two-dimensional encoded reinforcement means process flow diagram of aerospace storer of the application;
Fig. 4 is the design of two-dimentional correcting code encoder circuit;
Fig. 5 is the design of two-dimentional correcting code decoder circuit;
Fig. 6 is the anti-Multiple-bit upsets accumulator system with test function;
Fig. 7 is the domain structure of 16 bit width words.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is further illustrated.
The present invention proposes the two-dimensional encoded reinforcement means of a kind of aerospace storer, described reinforcement means introduces a kind of multi-bit error detection and modification method of low complex degree, and described multi-bit error detection and modification method can detect any multi-bit error and revise.
The detection of described multi-bit error and modification method are specially: the maximum error number of the Multiple-bit upsets that radiation event causes is
l, then need in accumulator system use detectivity be
lvertical wrong acquisition code.One is had
nthe word of position, the detection position of horizontal error acquisition code
d i can be obtained by following detection position calculating formula:
Wherein,
symbology XOR,
i,
lwith
kget positive integer, and
kvalue meet
,
b i represent corresponding information bit in storer, cataloged procedure is that information bit is input in scrambler according to the relation of detection position calculating formula, and detectivity is
lhorizontal error acquisition code need
lindividual detection position, each detection position performs corresponding odd even XOR and calculates.
Such as, for one
l=4,
nthe storer of=8, the detection position of horizontal error acquisition code can be expressed as
,
,
with
.From
d i relation in can know, if 1 arrives
lafter individual continuous mistake occurs, only having one to detect position can be affected.Therefore, by monitoring detection position
d i the mode of change, can realize no more than in a word
lindividual continuous print mistake detects.In decode procedure, if there is mistake in the code word received, then utilize detection position
d i the parity calculations produced, produces a rub-out signal.
Described multi-bit error detection and modification method only need the XOR of level encoder and decoding just can realize the detection of multi-bit error, therefore have very low transmission delay and hardware spending.
Described reinforcement means step is as follows:
Step 1, reads in the width of memory word, on logic connects a bit wide is
nword be converted into one (
k1,
k2) two-dimensional matrix form,
k1represent line number,
k2represent columns.
Traditional method is directly encoded to whole storage array, when often accessing the data of a word, vertical check code all needs the data calculating whole storage array, and the redundancy figure place of vertical check code is identical with the data width in storer, therefore brings larger hardware redundancy.
Step 2, determines the line number of two-dimensional matrix
k1and columns
k2.
Different
k1with
k2value can bring different redundancy overhead, minimum for target with redundant digit, choose reasonable line number
k1and columns
k2value,
Described redundant digit refers to the figure place sum of the figure place of the detection position of horizontal error acquisition code and the check digit of vertical check code.
When the bit wide of a word of storer
n=16, the maximum error number of the Multiple-bit upsets that radiation event causes
l=4time, the word of 16 bit wides is converted into the form of a matrix, then accordingly (
k1,
k2) value is (1,16), (4,4), (2,8), namely
,
or
matrix, according to the detection of described multi-bit error and modification method, often row has L and detects position, and often arranges and should have a check bit, then can draw
the detection position of matrix and the figure place of check digit are 4 and 16, then its redundant digit is 20,
the detection position of matrix and the figure place of check digit are 8 and 8, then its redundant digit is 16,
the detection position of matrix and the figure place of check digit are 16 and 4, then its redundant digit is 20, are so that redundant digit is minimum according to target, then select
k1=2,
k2=8.
Step 3, inserts horizontal error acquisition code and vertical check code.Every a line adds horizontal error acquisition code, and each row adds vertical parity effect code;
Determine according to above-mentioned steps 2
matrix, inserts corresponding detecting position and check bit, wherein D
1, D
2, D
3and D
4for the detecting position of the horizontal error acquisition code of the first row, D
5, D
6, D
7and D
8be the detecting position of the horizontal error acquisition code of the second row, the data of the storage of each detecting position can be obtained by following equalities.
i=(1,2,3,4)
i=(5,6,7,8)
C
1-C
8be check bit, the data of the storage of each check bit can be obtained by following equalities.
i=(1,2,3,…,8) ；
The scrambler of the two-dimentional correcting code that the present invention proposes can utilize the calculating formula of the data of the storage of detecting position described in each and check bit to be realized by XOR.
Step 4, after a word generation Multiple-bit upsets of storer, the row and column that described horizontal error acquisition code and vertical check code difference misdirection occur, when the interval of discontinuous multi-bit error is less than
ltime, although the number judging mistake that described horizontal error acquisition code can not be correct, a rub-out signal still can be provided.The column position of the line position utilizing this rub-out signal to indicate and parity check code instruction, no matter be that continuous mistake or discontinuous mistake can be located, and is revised by the value overturning self.
The described concrete steps being undertaken revising by the value overturning self are:
Step 4.1, produces decoding detecting position by the data received
d i 'with decoding check bit
c i '; ;
Step 4.2, calculated level syndrome
s di with vertical correction
s ci :
i=(1,2,3,…,8)
i=(1,2,3,…,8)
Step 4.3, when the horizontal syndromes of any
s di effectively, then represent and occur mistake, and revised by following equalities, wherein
it is the information bit that decoding information position draws correction
.
Step 5, according to the information bit at the information bit correction place revised, revises complete.
The two-dimentional correcting code that the present invention proposes not only can revise continuous print mistake, can also revise discontinuous mistake.Fig. 2 shows dissimilar Multiple-bit upsets, below by the error correcting capability of analysis of two-dimensional correcting code under different type of error.In Class1 and 2, no matter mistake occurs in colleague or different rows mutually, and continuous print mistake can be detected by respective horizontal error acquisition code.Once horizontal detection signal
d i 'effectively, mistake just can be revised by vertical parity check code.In type 3, mistake is discontinuous, thus some mistake (b
1and b
5) can not be distinguished by horizontal error acquisition code.But in this case, horizontal error acquisition code can according to b
3and b
4information, statement D
3' and D
4' effectively.Therefore in conjunction with vertical check position C
1' and C
5' result, all mistakes can be corrected.In type 4, if the spacing of mistake is greater than
l, so the mistake of this type to revise.But the result of radiation test shows, one time radiation event produces the interval of multi-bit error hardly more than 3.Therefore, the mistake occurred in type 4 can not exist in a radiation event, has departed from the research range of single irradiation stale event.Just likely occur in the radiation event of above-mentioned mistake only more than twice, and can be revised it by scrub techniques.
As shown in Figure 3, described reinforcement means, can also carry out Design of Reinforcement for the word of the data widths such as normally used 32,64 and 128 in storer.
The invention allows for a kind of two-dimentional correcting code of the two-dimensional encoded reinforcement means of above-mentioned aerospace storer that adopts and reinforce memory circuitry, as shown in Figure 6, it comprises scrambler, code translator, storer and MUX,
As shown in Figure 4, described scrambler writes Verilog codes implement by the calculating formula of the data of the storage of each detecting position described and check bit, 8 groups of XOR are for generating the acquisition code of horizontal error acquisition code in the encoder, 16 groups of buffer are for strengthening the driving force of data input pin to memory module, and other 8 groups of XOR are for generating the check bit of vertical check code.
As shown in Figure 5, described code translator is by writing Verilog codes implement, detecting position
d i 'and check bit
c i 'generated by 8 groups of XOR respectively, through decision logic, export correct data finally by 16 groups of XOR.
Described MUX has 16 data test ports and a test enable port, can reinforce memory circuitry and carry out correction test, be specially: first, in the normal mode of operation to storer write data by described MUX to two-dimentional correcting code; Subsequently, test enable end is set to effectively, enters test pattern, and input test data are modified to the data stored under normal mode of operation; Finally, read the data of write, compare Output rusults whether consistent with the data write under normal mode of operation.If export data and write data consistent, then show that described two-dimentional correcting code reinforces memory circuitry effective.
Reinforcing accumulator system after making flow during the test setting of described MUX has measurability to fault.
Two dimension correcting code can revise the mistake that in storer, data bit occurs effectively, but when mistake appears in the redundant digit that two-dimentional correcting code is introduced, can affect the correctness revising data, this problem is insurmountable in research in the past.The profiling error position that may occur below, total following four kinds may: the first, mistake all occurs in horizontal error acquisition code; The second, mistake all occurs in vertical check code; 3rd, mistake occurs in horizontal error acquisition code (original text is multi-bit error code) and vertical check code simultaneously; 4th, mistake occurs in information bit and corresponding check bit.
Described storer adopts domain split plot design to design, described figure split plot design considers the physical sequential of storage unit domain, avoid the data bit of operation relation too close with redundant digit when logic inputs, carry out segmentation to it to put, as shown in Figure 2, be specially: utilize information bit to cut horizontal error acquisition code and vertical check code; Information bit and should have mutually the check bit sum of operation relation detect the distance of positions be greater than from needs
l, with guarantee information position and have the redundant digit of operation relation to make a mistake simultaneously.
Domain split plot design of the present invention, it takes full advantage of the layout distribution structure of storage unit, suppresses the mistake that redundant digit occurs.
Described storer is a data width 16, number of words 4096, and capacity is the radiation hardening storer of 64K.Described two-dimentional correcting code reinforces the design of memory circuitry and domain thereof by realizing with warship (HJ) 0.18 μm of standard block technology library.The function that described two-dimentional correcting code reinforces memory circuitry uses ModelSim to verify, performance parameter and gate level netlist are obtained by Synopsys Design Compiler, crosses Cadence SOC Encounter and carries out laying out pattern's wiring.
The two-dimentional correction circuit proposed and the area of other correction circuits, power consumption and delay parameter as shown in table 1.With Hamming code as a reference, the result from table 1 is known, and the performance parameter of two-dimentional correction circuit is obviously better than other correction circuits.Error correcting capability is the area of the two-dimentional correction circuit of 4, delay and power consumption are 51%, 50% and 113% of Hamming code respectively.Can find from table 1, error correcting capability is the two-dimentional correction circuit that the delay of the two-dimentional correction circuit of 4 is less than that error correcting capability is 2 on the contrary.This is because error correcting capability be 4 the correction circuit codimg logic degree of depth lower, bring less delay.Therefore, after the two-dimentional amendment scheme using the present invention to propose, the increase of error correcting capability affects the performance of correction circuit hardly, only needs to increase corresponding redundant digit.
Table 1: the area of correction circuit, the list of power consumption delay parameter
In sum, the present invention proposes a kind of efficient 2-d correction circuit, it reaches the object suppressing storer Multiple-bit upsets with lower hardware spending.The two-dimentional amendment scheme proposed can revise the mistake of any given width, simultaneously in conjunction with the domain split plot design of proposition, can guarantee that storer obtains higher reliability.The result of reliability and performance evaluation shows, Rad Hard Memory of the present invention can well meet the application requirement under high energy space radiation environment, and the performance of correction circuit is better than multi-bit error correction code circuit known at present.
The above embodiment only have expressed embodiments of the present invention, but therefore can not be interpreted as limitation of the scope of the invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.
Claims (10)
1. the two-dimensional encoded reinforcement means of aerospace storer, it is characterized in that: described reinforcement means introduces a kind of multi-bit error detection and modification method of low complex degree, described multi-bit error detection and modification method can detect any multi-bit error and revise, and described reinforcement means step is as follows:
Step 1, reads in the width of memory word, on logic connects a bit wide is
nword be converted into one (
k1,
k2) two-dimensional matrix form,
k1represent line number,
k2represent columns;
Step 2, determines the line number of two-dimensional matrix
k1and columns
k2,
Different
k1with
k2value can bring different redundancy overhead, minimum for target with redundant digit, choose reasonable line number
k1and columns
k2value,
Described redundant digit refers to the figure place sum of the figure place of the detection position of horizontal error acquisition code and the check digit of vertical check code;
Step 3, insert horizontal error acquisition code and vertical check code, every a line adds horizontal error acquisition code, and each row adds vertical parity effect code;
Step 4, after a word generation Multiple-bit upsets of storer, the row and column that described horizontal error acquisition code and vertical check code difference misdirection occur, when the interval of discontinuous multi-bit error is less than
ltime, although what described horizontal error acquisition code can not be correct judges wrong number, but still can provide a rub-out signal, the column position of the line position utilizing this rub-out signal to indicate and parity check code instruction, no matter be that continuous mistake or discontinuous mistake can be located, and revised by the value overturning self;
Step 5, according to the information bit revised
revise
the information bit at place, revises complete.
2. the two-dimensional encoded reinforcement means of a kind of aerospace storer according to claim 1, is characterized in that: the detection of described multi-bit error and modification method are specially, and the maximum error number of the Multiple-bit upsets that radiation event causes is
l, then need in accumulator system use detectivity be
lvertical wrong acquisition code, one is had
nthe word of position, the detection position of horizontal error acquisition code
d i can be obtained by following detection position calculating formula:
，
Wherein, symbol
represent XOR,
i,
lwith
kget positive integer, and
kvalue meet,
b i represent corresponding information bit in storer, cataloged procedure is that information bit is input in scrambler according to the relation of detection position calculating formula, and detectivity is
lhorizontal error acquisition code need
lindividual detection position, each detection position performs corresponding odd even XOR and calculates;
Described multi-bit error detection and modification method only need the XOR of level encoder and decoding just can realize the detection of multi-bit error, have very low transmission delay and hardware spending.
3. the two-dimensional encoded reinforcement means of a kind of aerospace storer according to claim 2, is characterized in that: in described step 2,
When the bit wide of a word of storer
n=16, the maximum error number of the Multiple-bit upsets that radiation event causes
l=4time, the word of 16 bit wides is converted into the form of a matrix, then accordingly (
k1,
k2) value is (1,16), (4,4), (2,8), namely
,
or
matrix, according to the detection of described multi-bit error and modification method, often row has L and detects position, and often arranges and should have a check bit, then can draw
the detection position of matrix and the figure place of check digit are 4 and 16, then its redundant digit is 20,
the detection position of matrix and the figure place of check digit are 8 and 8, then its redundant digit is 16,
the detection position of matrix and the figure place of check digit are 16 and 4, then its redundant digit is 20, are so that redundant digit is minimum according to target, then select
k1=2,
k2=8.
4. the two-dimensional encoded reinforcement means of a kind of aerospace storer according to claim 3, is characterized in that: in described step 3,
Determine according to described step 2
matrix, inserts corresponding detecting position and check bit, wherein D
1, D
2, D
3and D
4for the detecting position of the horizontal error acquisition code of the first row, D
5, D
6, D
7and D
8be the detecting position of the horizontal error acquisition code of the second row, the data of the storage of each detecting position can be obtained by following equalities:
，
i=(1,2,3,4)，
，
i=(5,6,7,8) ，
C
1-C
8be check bit, the data of the storage of each check bit can be obtained by following equalities:
i=(1,2,3,…,8)。
5. the two-dimensional encoded reinforcement means of a kind of aerospace storer according to claim 4, is characterized in that: in described step 4, and the described concrete steps being undertaken revising by the value overturning self are:
Step 4.1, produces decoding detecting position by the data received
d i 'with decoding check bit
c i ';
Step 4.2, calculated level syndrome
s di with vertical correction
s ci :
，
i=(1,2,3,…,8)，
，
i=(1,2,3,…,8) ；
Step 4.3, when the horizontal syndromes of any
s di effectively, then represent and occur mistake, and revised by following equalities, wherein
it is the information bit that decoding information position draws correction
:
。
6. the two-dimensional encoded reinforcement means of a kind of aerospace storer according to claim 1-5 any one, it is characterized in that: described two-dimensional encoded reinforcement means, Design of Reinforcement can also be carried out for the word of the data widths such as normally used 32,64 and 128 in storer.
7. adopt the two-dimentional correcting code of the two-dimensional encoded reinforcement means of a kind of aerospace storer described in the claims 1-6 any one to reinforce a memory circuitry, it is characterized in that: it comprises scrambler, code translator, storer and MUX,
Described scrambler writes Verilog codes implement by the calculating formula of the data of the storage of each detecting position described and check bit, 8 groups of XOR are for generating the acquisition code of horizontal error acquisition code in the encoder, 16 groups of buffer are for strengthening the driving force of data input pin to memory module, and other 8 groups of XOR are for generating the check bit of vertical check code;
Described code translator is by writing Verilog codes implement, detecting position
d i 'and check bit
c i 'generated by 8 groups of XOR respectively, through decision logic, export correct data finally by 16 groups of XOR;
Described MUX has 16 data test ports and a test enable port, can reinforce memory circuitry to two-dimentional correcting code by described MUX carry out corrections and test, the reinforcing accumulator system after making flow during the test setting of described MUX has measurability to fault;
Described storer adopts domain split plot design to design, and described figure split plot design considers the physical sequential of storage unit domain, avoids the data bit of operation relation too close with redundant digit, carry out segmentation put it when logic inputs.
8. the two-dimentional correcting code of one according to claim 7 reinforces storer electricity, and it is characterized in that, the correction test process of described MUX is specially:
First, in the normal mode of operation to storer write data;
Subsequently, test enable end is set to effectively, enters test pattern, and input test data are modified to the data stored under normal mode of operation;
Finally, read the data of write, compare Output rusults whether consistent with the data write under normal mode of operation;
If export data and write data consistent, then show that described two-dimentional correcting code reinforces memory circuitry effective.
9. the two-dimentional correcting code of one according to claim 7 reinforces storer electricity, it is characterized in that:
Described domain split plot design is specially: utilize information bit to cut horizontal error acquisition code and vertical check code; Information bit and should have mutually the check bit sum of operation relation detect the distance of positions be greater than from needs
l, with guarantee information position and have the redundant digit of operation relation to make a mistake simultaneously.
10. the two-dimentional correcting code of one according to claim 7 reinforces storer electricity, and it is characterized in that, described storer is a data width 16, number of words 4096, and capacity is the radiation hardening storer of 64K; Described two-dimentional correcting code reinforces the design of memory circuitry and domain thereof by realizing with warship (HJ) 0.18 μm of standard block technology library; The function that described two-dimentional correcting code reinforces memory circuitry uses ModelSim to verify, performance parameter and gate level netlist are obtained by Synopsys Design Compiler, crosses Cadence SOC Encounter and carries out laying out pattern's wiring.
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| CN104796157A (en) * | 2015-04-24 | 2015-07-22 | 哈尔滨工业大学 | Anti-radiation multibit-flip partitioned-matrix-code strengthening method for storers |
| CN104851467A (en) * | 2015-05-20 | 2015-08-19 | 中国空间技术研究院 | Function verification method for SRAM with EDAC function for use in space navigation |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104796157A (en) * | 2015-04-24 | 2015-07-22 | 哈尔滨工业大学 | Anti-radiation multibit-flip partitioned-matrix-code strengthening method for storers |
| CN104932984A (en) * | 2015-05-12 | 2015-09-23 | 工业和信息化部电子第五研究所 | Multi-bit flipping detection method and system |
| CN106169312A (en) * | 2015-05-18 | 2016-11-30 | 爱思开海力士有限公司 | Generalised product code for flash |
| CN104851467A (en) * | 2015-05-20 | 2015-08-19 | 中国空间技术研究院 | Function verification method for SRAM with EDAC function for use in space navigation |
| CN104851467B (en) * | 2015-05-20 | 2017-12-22 | 中国空间技术研究院 | A kind of aerospace band EDAC function SRAM memory function verification methods |
| CN107680629A (en) * | 2017-10-30 | 2018-02-09 | 中北大学 | A kind of low redundant matrices code based on Latin square matrix construction carries out reinforcement means to memory |
| CN107845404A (en) * | 2017-10-30 | 2018-03-27 | 中北大学 | A kind of new low redundancy two-dimensional matrix code carries out reinforcement means to memory |
| CN107680629B (en) * | 2017-10-30 | 2020-08-25 | 中北大学 | Method for reinforcing memory by using low-redundancy matrix code based on Latin square matrix construction |
| CN110931074A (en) * | 2019-11-25 | 2020-03-27 | 北京时代民芯科技有限公司 | Optional bit width error correction and detection circuit for single event upset resistant memory |
| CN110931074B (en) * | 2019-11-25 | 2021-09-28 | 北京时代民芯科技有限公司 | Optional bit width error correction and detection circuit for single event upset resistant memory |
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