CN104851467A - Function verification method for SRAM with EDAC function for use in space navigation - Google Patents
Function verification method for SRAM with EDAC function for use in space navigation Download PDFInfo
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Abstract
The present invention discloses a function verification method for an SRAM with an EDAC function for use in space navigation. The comprehensive function and performance verification is performed on the SRAM with the EDAC function to verify whether the SRAM with the EDAC function satisfies the application requirements for space navigation, the verification content comprises the March C algorithm verification, the 1 bit wrong-injection verification and the 2 bit wrong-injection verification, which are performed on the SRAM with the EDAC function under the situation that the EDAC is started or closed. According to the function verification method, the data background of the March C algorithm is extended to the directed algorithm of 32 bits, and besides, the verification of hold-over faults of data is added; and the EDAC test program of fault injection is adopted.
Description
Technical field
The present invention relates to a kind of aerospace band EDAC function SRAM memory function verification method, belong to aerospace components and parts application verification technical field.
Background technology
By the impact of radiation in cosmic space, may there is Single event upset effecf (Signal Event Upset, SEU) in spaceborne static RAM (Static RandomAccess Memory, SRAM).SEU may cause the data of a certain position of storer to change to another stable state from a stable state, and the data variation of storer can make instruction or the corrupt data of board computer system, may cause the collapse of whole board computer system time serious.Therefore, need to find a kind of way and carry out error correction or fault-tolerant.Realizing spaceborne computer SRAM way that is fault-tolerant or error correction has a lot, and the SRAM memory adopting band EDAC function is the most direct way.
Along with constantly reducing of process, the continuous expansion of memory capacity, the testing complex degree of SRAM memory is increasing, for providing qualified memory product, must for various fault, optimal inspection vector, improves the test coverage of product.
SRAM memory with EDAC function is a kind of novel storer, and current existing function verification method is all design for the SRAM memory not with EDAC function.The present invention namely in this context, in order to realize verifying comprehensively and effectively the SRAM memory of band EDAC function, proposes corresponding function verification method.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provides a kind of aerospace band EDAC function SRAM memory function verification method.
Technical solution of the present invention is:
A kind of aerospace band EDAC function SRAM memory function verification method, step is as follows:
(1) the EDAC error correction mode of SRAM memory is opened, carry out the checking of March C-algorithm function, and the result of each test vector is sent to host computer by serial ports, if the result of all test vectors is 0, make the value of total count device remain unchanged; Otherwise, make the value of total count device add 1; The initial value of total count device is 0;
(2) the EDAC error correction mode of SRAM memory is closed, again carry out the checking of March C-algorithm function, and the result of each test vector is sent to host computer by serial ports, if the result of all test vectors is 0, make the value of total count device remain unchanged; Otherwise, make the value of total count device add 1;
(3) the 1bit note mistake of carrying out of SRAM memory is tested, and test result is uploaded to host computer, test result comprises the value of the soft counter of multiple SBE and the value of multiple SBE hardware counter, if the soft Counter Value of all SBE is 0 and all SBE hardware counter values are 512K, then the value of total count device is made to remain unchanged; Otherwise, make the value of total count device add 1;
(4) the 2bit note mistake of carrying out of SRAM memory is tested; And test result is uploaded to host computer, test result comprises the value of the soft counter of multiple MBE and the value of multiple MBE hardware counter, if the soft Counter Value of all MBE is 0 and all MBE hardware counter values are 512K, then the value of total count device is made to remain unchanged; Otherwise, make the value of total count device add 1; Enter step (5) afterwards;
(5) judge the value of total count device, if the value of total count device is 0, then the SRAM memory functional verification of described band EDAC function is passed through, otherwise shows SRAM memory dysfunction.
Carry out the checking of March C-algorithm function in described step (1) and step (2) to carry out all in the following way:
(2.1) press incremental order from first address 0x00000, addresses all in SRAM memory are all initialized as 0x00000000, error counter are set, and are initialized as 0;
(2.2) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFFFFFF; If different, then make error counter add 1, also this address date is written as 0xFFFFFFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.3) afterwards;
(2.3) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xFFFFFFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0x00000000; If different, then make error counter add 1, also this address date is written as 0x00000000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.4) afterwards;
(2.4) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFFFFFF; If different, then make error counter add 1, also this address date is written as 0xFFFFFFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.5) afterwards;
(2.5) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xFFFFFFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0x0000000; If different, then make error counter add 1, also this address date is written as 0x0000000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.6) afterwards;
(2.6) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is correct, and this address date is written as 0x55555555; If different, then make error counter add 1, also this address date is written as 0x55555555 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.7) afterwards;
(2.7) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x55555555 are compared, if identical, then show that this address date is correct, and this address date is written as 0xAAAAAAAA; If different, then make error counter add 1, also this address date is written as 0xAAAAAAAA simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.8) afterwards;
(2.8) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xAAAAAAAA are compared, if identical, then show that this address date is correct, and this address date is written as 0x55555555; If different, then make error counter add 1, also this address date is written as 0x55555555 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.9) afterwards;
(2.9) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x55555555 are compared, if identical, then show that this address date is correct, and this address date is written as 0x33333333; If different, then make error counter add 1, also this address date is written as 0x33333333 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.10) afterwards;
(2.10) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x33333333 are compared, if identical, then show that this address date is correct, and this address date is written as 0xCCCCCCCC; If different, then make error counter add 1, also this address date is written as 0xCCCCCCCC simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.11) afterwards;
(2.11) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xCCCCCCCC are compared, if identical, then show that this address date is correct, and this address date is written as 0x33333333; If different, then make error counter add 1, also this address date is written as 0x33333333 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.12) afterwards;
(2.12) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x33333333 are compared, if identical, then show that this address date is correct, and this address date is written as 0x0F0F0F0F; If different, then make error counter add 1, also this address date is written as 0x0F0F0F0F simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.13) afterwards;
(2.13) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x0F0F0F0F are compared, if identical, then show that this address date is correct, and this address date is written as 0xF0F0F0F0; If different, then make error counter add 1, also this address date is written as 0xF0F0F0F0 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.14) afterwards;
(2.14) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xF0F0F0F0 are compared, if identical, then show that this address date is correct, and this address date is written as 0x0F0F0F0F; If different, then make error counter add 1, also this address date is written as 0x0F0F0F0F simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.15) afterwards;
(2.15) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x0F0F0F0F are compared, if identical, then show that this address date is correct, and this address date is written as 0x00FF00FF; If different, then make error counter add 1, also this address date is written as 0x00FF00FF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.16) afterwards;
(2.16) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00FF00FF are compared, if identical, then show that this address date is correct, and this address date is written as 0xFF00FF00; If different, then make error counter add 1, also this address date is written as 0xFF00FF00 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.17) afterwards;
(2.17) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xFF00FF00 are compared, if identical, then show that this address date is correct, and this address date is written as 0x00FF00FF; If different, then make error counter add 1, also this address date is written as 0x00FF00FF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.18) afterwards;
(2.18) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00FF00FF are compared, if identical, then show that this address date is correct, and this address date is written as 0x0000FFFF; If different, then make error counter add 1, also this address date is written as 0x0000FFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.19) afterwards;
(2.19) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x0000FFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFF0000; If different, then make error counter add 1, also this address date is written as 0xFFFF0000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.20) afterwards;
(2.20) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xFFFF0000 are compared, if identical, then show that this address date is correct, and this address date is written as 0x0000FFFF; If different, then make error counter add 1, also this address date is written as 0x0000FFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.21) afterwards;
(2.21) from last address 0x7FFFF by order of successively decreasing, read the data of each address in SRAM memory, and the data read out and 0x0000FFFF compared, if identical, then show that this address date is correct; If different, then error counter is made to add 1; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, after time delay 100ms, enter step (2.22);
(2.22) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x0000FFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFF0000; If different, then make error counter add 1, also this address date is written as 0xFFFF0000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, after time delay 100ms, enter step (2.23);
(2.23) press incremental order from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xFFFF0000 are compared, if identical, then show that this address date is correct; If different, then error counter is made to add 1; After traveling through all addresses, the value of error counter is uploaded to host computer.
The carry out 1bit note wrong test of described step (3) to SRAM memory is carried out especially by such as under type:
(3.1) determine that the wrong data of note of SRAM memory being carried out to the wrong test of 1bit note are 0x00000001, the wrong identification pine SBE of the list of SRAM memory connects SBE hardware counter, and initial value is 0; Arrange the soft counter of SBE, its initial value is also set to 0;
The list of described SBE hardware counter to SRAM memory wrong identification pine SBE output pulse signal counts;
(3.2) the EDAC error correction mode of SRAM memory is opened;
(3.3) addresses all in SRAM memory are all write 0x00000000;
(3.4) the EDAC error correction mode of SRAM memory is closed;
(3.5) addresses all in SRAM memory are all write the wrong data of note;
(3.6) the EDAC error correction mode of SRAM memory is opened;
(3.7) press incremental order from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is corrected automatically by SRAM memory; If different, then the soft counter of SBE is made to add 1; After traveling through all addresses, the value of soft for SBE counter and SBE hardware counter is uploaded to host computer, and just the soft counter of SBE and SBE hardware counter reset, and enter step (3.8) afterwards;
(3.8) wrong for note data are moved to left 1, repeat step (3.2) ~ (3.7), again wrong for note data are moved to left 2 afterwards, repeat step (3.2) ~ (3.7) again, by that analogy, until wrong for note data are moved to left 32, repeat step (3.2) ~ (3.7); After 32 circulations are finished, enter step (3.9);
(3.9) wrong for note data are set to 0x00010001, repeat step (3.2) ~ (3.7), 0x00010001 is moved to left 1 more afterwards, repeat step (3.2) ~ (3.7), by that analogy, until moved to left by 0,x00,010,001 16, repeat step (3.2) ~ (3.7).
The carry out 2bit note wrong test of described step (4) to SRAM memory is carried out especially by such as under type:
(4.1) determine that the wrong data of note of SRAM memory being carried out to the wrong test of 1bit note are 0x00000003, the two wrong identification pine MBE of SRAM memory connects MBE hardware counter, and initial value is 0; Arrange the soft counter of MBE, its initial value is also set to 0;
The two wrong identification pine MBE output pulse signal of described MBE hardware counter to SRAM memory counts;
(4.2) the EDAC error correction mode of SRAM memory is opened;
(4.3) addresses all in SRAM memory are all write 0x00000000;
(4.4) the EDAC error correction mode of SRAM memory is closed;
(4.5) addresses all in SRAM memory are all write the wrong data of note;
(4.6) the EDAC error correction mode of SRAM memory is opened;
(4.7) press incremental order from first address 0x00000, read the data of each address in SRAM memory, and the data read out and the wrong data of described note are compared, if identical, then show that this address date is not corrected automatically by SRAM memory; If different, then the soft counter of MBE is made to add 1; After traveling through all addresses, the value of soft for MBE counter and MBE hardware counter is uploaded to host computer, and just the soft counter of MBE and MBE hardware counter reset, and enter step (4.8) afterwards;
(4.8) wrong for note data are moved to left 1, repeat step (4.2) ~ (4.7), again wrong for note data are moved to left 2 afterwards, repeat step (4.2) ~ (4.7) again, by that analogy, until wrong for note data are moved to left 32, repeat step (4.2) ~ (4.7); After 32 circulations are finished, enter step (4.9);
(4.9) wrong for note data are set to 0x00030003, repeat step (4.2) ~ (4.7), 0x00030003 is moved to left 1 more afterwards, repeat step (4.2) ~ (4.7), by that analogy, until moved to left by 0,x00,030,003 16, repeat step (4.2) ~ (4.7).
The present invention's beneficial effect compared with prior art:
(1) the invention provides complete, a comprehensive aerospace band EDAC function SRAM memory function verification method, can according to the needs of device application checking, at any time adjustment and measurement is carried out to Verification Project or method, significant for the functional verification of aerospace band EDAC function SRAM memory.
(2) the present invention compares with common March C-algorithm, by increasing the coupling fault test data background sequential in word, data width is increased to 32 from 1; Meanwhile, delay test is carried out to the data background of wherein a pair radix-minus-one complement each other, realizes cover data and keep fault.
(3) the present invention can to the persistent fault of SRAM memory, translation exception, coupling fault, address decoding fault, read destructive malfunction, mistake writes logical fault, data retention failures reaches 100% coverage rate; And algorithm complex is low, 23 steps are only needed to complete checking to the storage unit of 32 bit widths.
(4) the present invention adopts 1bit and 2bit to note wrong test, wrong test can be noted to each bit data bit of each storage unit of band EDAC function SRAM memory, compared with actual single particle experiment, have and realize the advantage simple, verification efficiency is high.
(5) data in the present invention are that the band EDAC function SRAM memory being 512K bit wide 32bit for capacity designs, the band EDAC function SRAM memory function verification method of other capacity and bit wide can be general, only need do adaptability revision to corresponding data.
Accompanying drawing explanation
Fig. 1 is band EDAC function SRAM memory function verification method process flow diagram of the present invention;
Fig. 2 is band EDAC function SRAM memory March C-algorithm flow chart of the present invention;
Fig. 3 is that band EDAC function SRAM memory 1bit of the present invention notes wrong test flow chart;
Fig. 4 is that band EDAC function SRAM memory 2bit of the present invention notes wrong test flow chart;
Embodiment
As shown in Figure 1, the invention provides a kind of aerospace band EDAC function SRAM memory function verification method, step is as follows:
(1) the EDAC error correction mode of SRAM memory is opened, carry out the checking of March C-algorithm function, and the result of each test vector is sent to host computer by serial ports, if the result of all test vectors is 0, make the value of total count device remain unchanged; Otherwise, make the value of total count device add 1; The initial value of total count device is 0;
As shown in Figure 2, carry out the checking of March C-algorithm function to carry out all in the following way:
(1.1) press incremental order from first address 0x00000, addresses all in SRAM memory are all initialized as 0x00000000, error counter are set, and are initialized as 0;
(1.2) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFFFFFF; If different, then make error counter add 1, also this address date is written as 0xFFFFFFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (13) afterwards;
(1.3) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xFFFFFFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0x00000000; If different, then make error counter add 1, also this address date is written as 0x00000000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.4) afterwards;
(1.4) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFFFFFF; If different, then make error counter add 1, also this address date is written as 0xFFFFFFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.5) afterwards;
(1.5) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xFFFFFFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0x0000000; If different, then make error counter add 1, also this address date is written as 0x0000000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.6) afterwards;
(1.6) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is correct, and this address date is written as 0x55555555; If different, then make error counter add 1, also this address date is written as 0x55555555 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.7) afterwards;
(1.7) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x55555555 are compared, if identical, then show that this address date is correct, and this address date is written as 0xAAAAAAAA; If different, then make error counter add 1, also this address date is written as 0xAAAAAAAA simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.8) afterwards;
(1.8) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xAAAAAAAA are compared, if identical, then show that this address date is correct, and this address date is written as 0x55555555; If different, then make error counter add 1, also this address date is written as 0x55555555 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.9) afterwards;
(1.9) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x55555555 are compared, if identical, then show that this address date is correct, and this address date is written as 0x33333333; If different, then make error counter add 1, also this address date is written as 0x33333333 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.10) afterwards;
(1.10) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x33333333 are compared, if identical, then show that this address date is correct, and this address date is written as 0xCCCCCCCC; If different, then make error counter add 1, also this address date is written as 0xCCCCCCCC simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.11) afterwards;
(1.11) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xCCCCCCCC are compared, if identical, then show that this address date is correct, and this address date is written as 0x33333333; If different, then make error counter add 1, also this address date is written as 0x33333333 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.12) afterwards;
(1.12) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x33333333 are compared, if identical, then show that this address date is correct, and this address date is written as 0x0F0F0F0F; If different, then make error counter add 1, also this address date is written as 0x0F0F0F0F simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.13) afterwards;
(1.13) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x0F0F0F0F are compared, if identical, then show that this address date is correct, and this address date is written as 0xF0F0F0F0; If different, then make error counter add 1, also this address date is written as 0xF0F0F0F0 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.14) afterwards;
(1.14) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xF0F0F0F0 are compared, if identical, then show that this address date is correct, and this address date is written as 0x0F0F0F0F; If different, then make error counter add 1, also this address date is written as 0x0F0F0F0F simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.15) afterwards;
(1.15) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x0F0F0F0F are compared, if identical, then show that this address date is correct, and this address date is written as 0x00FF00FF; If different, then make error counter add 1, also this address date is written as 0x00FF00FF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.16) afterwards;
(1.16) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00FF00FF are compared, if identical, then show that this address date is correct, and this address date is written as 0xFF00FF00; If different, then make error counter add 1, also this address date is written as 0xFF00FF00 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.17) afterwards;
(1.17) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xFF00FF00 are compared, if identical, then show that this address date is correct, and this address date is written as 0x00FF00FF; If different, then make error counter add 1, also this address date is written as 0x00FF00FF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.18) afterwards;
(1.18) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00FF00FF are compared, if identical, then show that this address date is correct, and this address date is written as 0x0000FFFF; If different, then make error counter add 1, also this address date is written as 0x0000FFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.19) afterwards;
(1.19) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x0000FFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFF0000; If different, then make error counter add 1, also this address date is written as 0xFFFF0000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.20) afterwards;
(1.20) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xFFFF0000 are compared, if identical, then show that this address date is correct, and this address date is written as 0x0000FFFF; If different, then make error counter add 1, also this address date is written as 0x0000FFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (1.21) afterwards;
(1.21) from last address 0x7FFFF by order of successively decreasing, read the data of each address in SRAM memory, and the data read out and 0x0000FFFF compared, if identical, then show that this address date is correct; If different, then error counter is made to add 1; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, after time delay 100ms, enter step (1.22);
(1.22) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x0000FFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFF0000; If different, then make error counter add 1, also this address date is written as 0xFFFF0000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, after time delay 100ms, enter step (1.23);
(1.23) press incremental order from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xFFFF0000 are compared, if identical, then show that this address date is correct; If different, then error counter is made to add 1; After traveling through all addresses, the value of error counter is uploaded to host computer.
(2) the EDAC error correction mode of SRAM memory is closed, again carry out the checking of March C-algorithm function, and the result of each test vector is sent to host computer by serial ports, if the result of all test vectors is 0, make the value of total count device remain unchanged; Otherwise, make the value of total count device add 1; The step of again carrying out the checking of March C-algorithm function in this step is identical with step (1);
(3) the 1bit note mistake of carrying out of SRAM memory is tested, and test result is uploaded to host computer, test result comprises the value of the soft counter of multiple SBE and the value of multiple SBE hardware counter, if the soft Counter Value of all SBE is 0 and all SBE hardware counter values are 512K, then the value of total count device is made to remain unchanged; Otherwise, make the value of total count device add 1;
The invention provides a kind of band EDAC function SRAM memory 1bit and note wrong method of testing, first carry out low 16bit and note wrong test, then carry out high 16bit and note wrong test, finally carry out low 16bit and high 16bit and note wrong test simultaneously, pass through cyclic shift, by the error correction of each bit data bit of checking, in specific operation process, first the wrong data of note are changed at the beginning, it is 0x00000001 that low 16bit notes wrong data, it is 0x00010000 that high 16bit notes wrong data, and it is 0x00010001 that height 16bit notes wrong data simultaneously.First EDAC pattern is opened, to full address write data 0x00000000; Then close EDAC pattern, carry out error injection; Then open EDAC pattern to start to read data, judge whether SBE zone bit is set to high level simultaneously, and record upset number of times.Specifically as shown in Figure 3, the wrong test of 1bit note of carrying out of SRAM memory is specially:
(3.1) determine that the wrong data of note of SRAM memory being carried out to the wrong test of 1bit note are 0x00000001, the wrong identification pine SBE of the list of SRAM memory connects SBE hardware counter, and initial value is 0; Arrange the soft counter of SBE, its initial value is also set to 0;
The list of described SBE hardware counter to SRAM memory wrong identification pine SBE output pulse signal counts;
(3.2) the EDAC error correction mode of SRAM memory is opened;
(3.3) addresses all in SRAM memory are all write 0x00000000;
(3.4) the EDAC error correction mode of SRAM memory is closed;
(3.5) addresses all in SRAM memory are all write the wrong data of note;
(3.6) the EDAC error correction mode of SRAM memory is opened;
(3.7) press incremental order from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is corrected automatically by SRAM memory; If different, then the soft counter of SBE is made to add 1; After traveling through all addresses, the value of soft for SBE counter and SBE hardware counter is uploaded to host computer, and just the soft counter of SBE and SBE hardware counter reset, and enter step (3.8) afterwards;
(3.8) wrong for note data are moved to left 1, repeat step (3.2) ~ (3.7), again wrong for note data are moved to left 2 afterwards, repeat step (3.2) ~ (3.7) again, by that analogy, until wrong for note data are moved to left 32, repeat step (3.2) ~ (3.7); After 32 circulations are finished, enter step (3.9);
(3.9) wrong for note data are set to 0x00010001, repeat step (3.2) ~ (3.7), 0x00010001 is moved to left 1 more afterwards, repeat step (3.2) ~ (3.7), by that analogy, until moved to left by 0,x00,010,001 16, repeat step (3.2) ~ (3.7).
(4) the 2bit note mistake of carrying out of SRAM memory is tested; And test result is uploaded to host computer, test result comprises the value of the soft counter of multiple MBE and the value of multiple MBE hardware counter, if the soft Counter Value of all MBE is 0 and all MBE hardware counter values are 512K, then the value of total count device is made to remain unchanged; Otherwise, make the value of total count device add 1; Enter step (5) afterwards;
The invention provides a kind of band EDAC function SRAM memory 2bit and note wrong method of testing, first carry out low 16bit and note wrong test, then carry out high 16bit and note wrong test, finally carry out low 16bit and high 16bit and note wrong test simultaneously, pass through cyclic shift, by the error detecing capability of the every 2bit data bit of checking, in specific operation process, first the wrong data of note are changed at the beginning, it is 0x00000003 that low 16bit notes wrong data, it is 0x00030000 that high 16bit notes wrong data, and it is 0x00030003 that height 16bit notes wrong data simultaneously.First EDAC pattern is opened, to full address write data 0x00000000; Then close EDAC pattern, carry out error injection; Then open EDAC pattern to start to read data, judge whether MBE zone bit is set to high level simultaneously, and record upset number of times.
As shown in Figure 4, the wrong test of 2bit note of carrying out of SRAM memory is specially:
(4.1) determine that the wrong data of note of SRAM memory being carried out to the wrong test of 1bit note are 0x00000003, the two wrong identification pine MBE of SRAM memory connects MBE hardware counter, and initial value is 0; Arrange the soft counter of MBE, its initial value is also set to 0;
The two wrong identification pine MBE output pulse signal of described MBE hardware counter to SRAM memory counts;
(4.2) the EDAC error correction mode of SRAM memory is opened;
(4.3) addresses all in SRAM memory are all write 0x00000000;
(4.4) the EDAC error correction mode of SRAM memory is closed;
(4.5) addresses all in SRAM memory are all write the wrong data of note;
(4.6) the EDAC error correction mode of SRAM memory is opened;
(4.7) press incremental order from first address 0x00000, read the data of each address in SRAM memory, and the data read out and the wrong data of described note are compared, if identical, then show that this address date is not corrected automatically by SRAM memory; If different, then the soft counter of MBE is made to add 1; After traveling through all addresses, the value of soft for MBE counter and MBE hardware counter is uploaded to host computer, and just the soft counter of MBE and MBE hardware counter reset, and enter step (4.8) afterwards;
(4.8) wrong for note data are moved to left 1, repeat step (4.2) ~ (4.7), again wrong for note data are moved to left 2 afterwards, repeat step (4.2) ~ (4.7) again, by that analogy, until wrong for note data are moved to left 32, repeat step (4.2) ~ (4.7); After 32 circulations are finished, enter step (4.9);
(4.9) wrong for note data are set to 0x00030003, repeat step (4.2) ~ (4.7), 0x00030003 is moved to left 1 more afterwards, repeat step (4.2) ~ (4.7), by that analogy, until moved to left by 0,x00,030,003 16, repeat step (4.2) ~ (4.7);
(5) judge the value of total count device, if the value of total count device is 0, then the SRAM memory functional verification of described band EDAC function is passed through, otherwise shows SRAM memory dysfunction.
The content be not described in detail in instructions of the present invention belongs to the known technology of professional and technical personnel in the field.
Claims (4)
1. an aerospace band EDAC function SRAM memory function verification method, is characterized in that step is as follows:
(1) the EDAC error correction mode of SRAM memory is opened, carry out the checking of March C-algorithm function, and the result of each test vector is sent to host computer by serial ports, if the result of all test vectors is 0, make the value of total count device remain unchanged; Otherwise, make the value of total count device add 1; The initial value of total count device is 0;
(2) the EDAC error correction mode of SRAM memory is closed, again carry out the checking of March C-algorithm function, and the result of each test vector is sent to host computer by serial ports, if the result of all test vectors is 0, make the value of total count device remain unchanged; Otherwise, make the value of total count device add 1;
(3) the 1bit note mistake of carrying out of SRAM memory is tested, and test result is uploaded to host computer, test result comprises the value of the soft counter of multiple SBE and the value of multiple SBE hardware counter, if the soft Counter Value of all SBE is 0 and all SBE hardware counter values are 512K, then the value of total count device is made to remain unchanged; Otherwise, make the value of total count device add 1;
(4) the 2bit note mistake of carrying out of SRAM memory is tested; And test result is uploaded to host computer, test result comprises the value of the soft counter of multiple MBE and the value of multiple MBE hardware counter, if the soft Counter Value of all MBE is 0 and all MBE hardware counter values are 512K, then the value of total count device is made to remain unchanged; Otherwise, make the value of total count device add 1; Enter step (5) afterwards;
(5) judge the value of total count device, if the value of total count device is 0, then the SRAM memory functional verification of described band EDAC function is passed through, otherwise shows SRAM memory dysfunction.
2. a kind of aerospace band EDAC function SRAM memory function verification method according to claim 1, is characterized in that:
Carry out the checking of March C-algorithm function in described step (1) and step (2) to carry out all in the following way:
(2.1) press incremental order from first address 0x00000, addresses all in SRAM memory are all initialized as 0x00000000, error counter are set, and are initialized as 0;
(2.2) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFFFFFF; If different, then make error counter add 1, also this address date is written as 0xFFFFFFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.3) afterwards;
(2.3) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xFFFFFFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0x00000000; If different, then make error counter add 1, also this address date is written as 0x00000000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.4) afterwards;
(2.4) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFFFFFF; If different, then make error counter add 1, also this address date is written as 0xFFFFFFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.5) afterwards;
(2.5) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xFFFFFFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0x0000000; If different, then make error counter add 1, also this address date is written as 0x0000000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.6) afterwards;
(2.6) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is correct, and this address date is written as 0x55555555; If different, then make error counter add 1, also this address date is written as 0x55555555 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.7) afterwards;
(2.7) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x55555555 are compared, if identical, then show that this address date is correct, and this address date is written as 0xAAAAAAAA; If different, then make error counter add 1, also this address date is written as 0xAAAAAAAA simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.8) afterwards;
(2.8) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xAAAAAAAA are compared, if identical, then show that this address date is correct, and this address date is written as 0x55555555; If different, then make error counter add 1, also this address date is written as 0x55555555 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.9) afterwards;
(2.9) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x55555555 are compared, if identical, then show that this address date is correct, and this address date is written as 0x33333333; If different, then make error counter add 1, also this address date is written as 0x33333333 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.10) afterwards;
(2.10) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x33333333 are compared, if identical, then show that this address date is correct, and this address date is written as 0xCCCCCCCC; If different, then make error counter add 1, also this address date is written as 0xCCCCCCCC simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.11) afterwards;
(2.11) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xCCCCCCCC are compared, if identical, then show that this address date is correct, and this address date is written as 0x33333333; If different, then make error counter add 1, also this address date is written as 0x33333333 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.12) afterwards;
(2.12) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x33333333 are compared, if identical, then show that this address date is correct, and this address date is written as 0x0F0F0F0F; If different, then make error counter add 1, also this address date is written as 0x0F0F0F0F simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.13) afterwards;
(2.13) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x0F0F0F0F are compared, if identical, then show that this address date is correct, and this address date is written as 0xF0F0F0F0; If different, then make error counter add 1, also this address date is written as 0xF0F0F0F0 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.14) afterwards;
(2.14) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xF0F0F0F0 are compared, if identical, then show that this address date is correct, and this address date is written as 0x0F0F0F0F; If different, then make error counter add 1, also this address date is written as 0x0F0F0F0F simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.15) afterwards;
(2.15) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x0F0F0F0F are compared, if identical, then show that this address date is correct, and this address date is written as 0x00FF00FF; If different, then make error counter add 1, also this address date is written as 0x00FF00FF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.16) afterwards;
(2.16) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00FF00FF are compared, if identical, then show that this address date is correct, and this address date is written as 0xFF00FF00; If different, then make error counter add 1, also this address date is written as 0xFF00FF00 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.17) afterwards;
(2.17) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xFF00FF00 are compared, if identical, then show that this address date is correct, and this address date is written as 0x00FF00FF; If different, then make error counter add 1, also this address date is written as 0x00FF00FF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.18) afterwards;
(2.18) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00FF00FF are compared, if identical, then show that this address date is correct, and this address date is written as 0x0000FFFF; If different, then make error counter add 1, also this address date is written as 0x0000FFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.19) afterwards;
(2.19) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0x0000FFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFF0000; If different, then make error counter add 1, also this address date is written as 0xFFFF0000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.20) afterwards;
(2.20) from last address 0x7FFFF by successively decrease order, read the data of each address in SRAM memory, and the data read out and 0xFFFF0000 are compared, if identical, then show that this address date is correct, and this address date is written as 0x0000FFFF; If different, then make error counter add 1, also this address date is written as 0x0000FFFF simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, enter step (2.21) afterwards;
(2.21) from last address 0x7FFFF by order of successively decreasing, read the data of each address in SRAM memory, and the data read out and 0x0000FFFF compared, if identical, then show that this address date is correct; If different, then error counter is made to add 1; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, after time delay 100ms, enter step (2.22);
(2.22) incremental order is pressed from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x0000FFFF are compared, if identical, then show that this address date is correct, and this address date is written as 0xFFFF0000; If different, then make error counter add 1, also this address date is written as 0xFFFF0000 simultaneously; After traveling through all addresses, the value of error counter is uploaded to host computer, then the value of error counter is reset, after time delay 100ms, enter step (2.23);
(2.23) press incremental order from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0xFFFF0000 are compared, if identical, then show that this address date is correct; If different, then error counter is made to add 1; After traveling through all addresses, the value of error counter is uploaded to host computer.
3. a kind of aerospace band EDAC function SRAM memory function verification method according to claim 1, is characterized in that: the carry out 1bit note wrong test of described step (3) to SRAM memory is carried out especially by such as under type:
(3.1) determine that the wrong data of note of SRAM memory being carried out to the wrong test of 1bit note are 0x00000001, the wrong identification pine SBE of the list of SRAM memory connects SBE hardware counter, and initial value is 0; Arrange the soft counter of SBE, its initial value is also set to 0;
The list of described SBE hardware counter to SRAM memory wrong identification pine SBE output pulse signal counts;
(3.2) the EDAC error correction mode of SRAM memory is opened;
(3.3) addresses all in SRAM memory are all write 0x00000000;
(3.4) the EDAC error correction mode of SRAM memory is closed;
(3.5) addresses all in SRAM memory are all write the wrong data of note;
(3.6) the EDAC error correction mode of SRAM memory is opened;
(3.7) press incremental order from first address 0x00000, read the data of each address in SRAM memory, and the data read out and 0x00000000 are compared, if identical, then show that this address date is corrected automatically by SRAM memory; If different, then the soft counter of SBE is made to add 1; After traveling through all addresses, the value of soft for SBE counter and SBE hardware counter is uploaded to host computer, and just the soft counter of SBE and SBE hardware counter reset, and enter step (3.8) afterwards;
(3.8) wrong for note data are moved to left 1, repeat step (3.2) ~ (3.7), again wrong for note data are moved to left 2 afterwards, repeat step (3.2) ~ (3.7) again, by that analogy, until wrong for note data are moved to left 32, repeat step (3.2) ~ (3.7); After 32 circulations are finished, enter step (3.9);
(3.9) wrong for note data are set to 0x00010001, repeat step (3.2) ~ (3.7), 0x00010001 is moved to left 1 more afterwards, repeat step (3.2) ~ (3.7), by that analogy, until moved to left by 0,x00,010,001 16, repeat step (3.2) ~ (3.7).
4. a kind of aerospace band EDAC function SRAM memory function verification method according to claim 1, is characterized in that: the carry out 2bit note wrong test of described step (4) to SRAM memory is carried out especially by such as under type:
(4.1) determine that the wrong data of note of SRAM memory being carried out to the wrong test of 1bit note are 0x00000003, the two wrong identification pine MBE of SRAM memory connects MBE hardware counter, and initial value is 0; Arrange the soft counter of MBE, its initial value is also set to 0;
The two wrong identification pine MBE output pulse signal of described MBE hardware counter to SRAM memory counts;
(4.2) the EDAC error correction mode of SRAM memory is opened;
(4.3) addresses all in SRAM memory are all write 0x00000000;
(4.4) the EDAC error correction mode of SRAM memory is closed;
(4.5) addresses all in SRAM memory are all write the wrong data of note;
(4.6) the EDAC error correction mode of SRAM memory is opened;
(4.7) press incremental order from first address 0x00000, read the data of each address in SRAM memory, and the data read out and the wrong data of described note are compared, if identical, then show that this address date is not corrected automatically by SRAM memory; If different, then the soft counter of MBE is made to add 1; After traveling through all addresses, the value of soft for MBE counter and MBE hardware counter is uploaded to host computer, and just the soft counter of MBE and MBE hardware counter reset, and enter step (4.8) afterwards;
(4.8) wrong for note data are moved to left 1, repeat step (4.2) ~ (4.7), again wrong for note data are moved to left 2 afterwards, repeat step (4.2) ~ (4.7) again, by that analogy, until wrong for note data are moved to left 32, repeat step (4.2) ~ (4.7); After 32 circulations are finished, enter step (4.9);
(4.9) wrong for note data are set to 0x00030003, repeat step (4.2) ~ (4.7), 0x00030003 is moved to left 1 more afterwards, repeat step (4.2) ~ (4.7), by that analogy, until moved to left by 0,x00,030,003 16, repeat step (4.2) ~ (4.7).
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| CN108122598A (en) * | 2017-12-18 | 2018-06-05 | 中国电子产品可靠性与环境试验研究所 | Possess the soft error rate method for predicting and system of EDAC functions SRAM |
| CN108122598B (en) * | 2017-12-18 | 2020-12-08 | 中国电子产品可靠性与环境试验研究所 | Soft error rate prediction method and system of SRAM with EDAC function |
| CN109739774A (en) * | 2019-01-25 | 2019-05-10 | 上海创景信息科技有限公司 | EDAC direct fault location and detection method |
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