CN107992412A - The test method of single event upset fault resistance of on-board software based on ERC32 - Google Patents
The test method of single event upset fault resistance of on-board software based on ERC32 Download PDFInfo
- Publication number
- CN107992412A CN107992412A CN201711207545.XA CN201711207545A CN107992412A CN 107992412 A CN107992412 A CN 107992412A CN 201711207545 A CN201711207545 A CN 201711207545A CN 107992412 A CN107992412 A CN 107992412A
- Authority
- CN
- China
- Prior art keywords
- edac
- function
- board software
- eeprom
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The present invention provides a kind of test method of the single event upset fault resistance of on-board software based on ERC32, ERC32 On-board software test platforms are run on, are specifically included：The TESCTR registers carried using the ERC32 chips of test platform, the function that mono- dislocations of EDAC and two dislocation failures are injected to described program Operational Zone SRAM is designed according to the characteristics of program Operational Zone SRAM；The characteristics of carrying software locks according to program storage area EEPROM, designs the function that mono- dislocations of EDAC and two dislocation failures are injected to EEPROM；Direct fault location function module is finally loaded into compilation run in tested On-board software, realizes the test to the anti-single particle function validity of On-board software.This method need not leave jtag interface, without hardware emulator, it is only necessary to add one section of software code, it is possible to the test of anti-single particle upset failure is reliably flexibly carried out to On-board software.
Description
Technical field
It is more particularly to a kind of based on the spaceborne of ERC32 the present invention relates to the relevant technical field of On-board software fault test
Software anti-single particle overturns the test method of failure.
Background technology
Aircraft in complex space environment, be highly prone to solar wind, spatial electromagnetic storm, Energetic particle and
The threat of cosmic ray, occurs single-particle inversion failure.The embedded software of operation thereon, such as spaceborne management software, star
Business software etc., is the control core of satellite, and higher want is suffered to reliability, security, maintainability and service life
Ask, should particularly possess self detection and repair ability after single-particle failure occurs.
But in Software for Design to self detection of single-particle failure and repair function after, how to be noted in development process
Enter single-particle failure, verify the detection of single-particle failure and the correctness of repair function, be the problem that must be solved.
On-board software anti-single particle failure function is applied in aerospace engineering, in the prior art, injects simple grain
The method of sub- failure relies primarily on emulator.The shortcomings that this method is：1. emulator needs to connect the JTAG debugging interfaces of CPU,
Cause the interface to be shielded from hardware, reduce the reliability of CPU；2. emulator is the equipment of an exterior access, single
The correctness of particle direct fault location cannot be completely secured.
Therefore, how to allow On-board software reliablely and stablely to test anti-single particle failure function is that there is an urgent need for solution for this area
Technical problem certainly.
The content of the invention
It is an object of the invention to provide a kind of test side of the single event upset fault resistance of on-board software based on ERC32
Method, to solve the problems, such as that existing technology can not reliablely and stablely test single event upset fault resistance of on-board software function.
To achieve the above object, the present invention provides a kind of single event upset fault resistance of on-board software based on ERC32
Test method, this method run on ERC32 On-board software test platforms, specifically include：
The TESCTR registers carried using the ERC32 chips of ERC32 On-board software test platforms, are run according to program
The characteristics of area SRAM, designs the function that mono- dislocations of EDAC and two dislocation failures are injected to described program Operational Zone SRAM；
The characteristics of carrying software locks according to program storage area EEPROM, designs to EEPROM and injects mono- dislocations of EDAC and two
The function of wrong failure；
Direct fault location function module is finally loaded into compilation run in tested On-board software, simulates spaceborne computer
In single-particle failure, to realize the test to the anti-single particle function validity of the On-board software.
It is preferred that the function that mono- dislocations of EDAC and two dislocation failures are injected to described program Operational Zone SRAM specifically includes：
The data on the ERC32 data/address bus of EDAC functions are opened, by 32 data bit, 1 bit parity check position and 7 Chinese
Totally 40 data compositions, the EDAC that by the Hamming code remaining 33 data are carried out with rectifying one and checking two are verified plain code, obtain school
Test value；Then：
(1) include to the failure function of SRAM areas injection mono- dislocations of EDAC：The data of specified memory are read, it is correct to calculate its
EDAC check values, according to correct check value, produce EDAC check values one wrong, finally utilize the TESCTR registers
To EDAC check values one wrong caused by specified memory injection, complete to inject EDAC to described program Operational Zone SRAM areas
The function of one dislocation failure；
(2) include to the failure function of SRAM areas injection two dislocations of EDAC：The data of specified memory are read, it is correct to calculate its
EDAC check values, then inject correct EDAC check values to the specified memory using the TESCTR registers, at the same time will
The data of the specified memory data write error one, according to data one wrong, parity check bit also can be one wrong, so far completes
To the function of described program Operational Zone SRAM areas injection two dislocation failures of EDAC.
It is preferred that the characteristics of carrying software locks according to program storage area EEPROM, designs to EEPROM and injects EDAC mono-
Wrong and two dislocation failures functions specifically include：
Since program storage area EEPROM carries software locks, it is necessary to write correct data sequence to specified address, just may be used
To unlock, data can be just write after unlocking, then：
(1) mono- dislocations of EDAC are injected to EEPROM
After reading the data for specifying address, only unlock to preceding 32 data fields, data one wrong then are write this refers to
Determine address, check bit area does not unlock, and the correct verification of not wrong data, so far completes to note to EEPROM before check code is still at this time
Enter the function of mono- dislocation failures of EDAC；
(2) two dislocations of EDAC are injected to EEPROM
After reading the data for specifying address, only unlock to preceding 32 data fields, data two wrong then are write this refers to
Determine address, so far complete the function to EEPROM injection two dislocation failures of EDAC.
The failure of mono- dislocations of EDAC and two dislocations is injected it is preferred that designing to described program Operational Zone SRAM and to EEPROM
During the power function of injection mono- dislocations of EDAC and two dislocation failures, the power function has 4 incoming parameters, the incoming ginseng
Number be respectively used to determine SRAM injections EDAC mono- dislocations, two dislocations of SRAM injection EDAC, mono- dislocations of EEPROM injection EDAC,
Whether EEPROM injections two dislocation functions of EDAC open.
It is preferred that after designing the power function, the power function is called at the beginning of On-board software, and by defeated
The incoming parameter entered opens the wrong function that injection needs to test.
Specifically included it is preferred that direct fault location function module to be added to compilation run in tested On-board software：
First, carry out the On-board software after the direct fault location function module can will be with the addition of in the PC machine of cross compile
Compiling, the code after being compiled.The amended On-board software with the addition of the direct fault location function module, and spaceborne soft
Part beginning is called, and the function of the corresponding single-particle failure that need to be injected is opened by being passed to parameter；
Then, the code after compiling is loaded into the SRAM of spaceborne computer by ground checkout equipment and is run,
The power function of direct fault location function module can trigger the failure opened in single-particle failure after operation；
Finally, handling result of the On-board software to each failure of the spaceborne computer is obtained by telemetry intelligence (TELINT), with complete
Into the test of the anti-single particle function validity of the On-board software.
It is preferred that the code after compiling is sent to spaceborne computer by the ground checkout equipment by serial ports, by described
Code after compiling is loaded into SRAM by the monitoring software in spaceborne computer PROM.
The invention has the advantages that：
It is different from traditional needs and the shortcomings that JTAG debugging interfaces are to connect hardware emulator, the present invention is being opened on CPU
The method of offer may not need the jtag interface for leaving and reducing spaceborne computer reliability, without hardware emulator, it is only necessary to add
Enter one section of software code, it is possible to the test of anti-single particle upset failure is reliably flexibly carried out to On-board software.
The method of the present invention can especially have as the test method of single event upset fault resistance of on-board software in space industry
There is preferable engineering application value.
Brief description of the drawings
Fig. 1 is system structure diagram used in the embodiment of the present invention；
Fig. 2 is the method flow diagram that the preferred embodiment of the present invention provides；
Fig. 3 is the flow chart for four kinds of single-particle direct fault location functions that the method for the present invention provides.
Label declaration：1-PC machines；2- ground checkout equipments；3- spaceborne computers.
Embodiment
Below with reference to the attached drawing of the present invention, clear, complete description is carried out to the technical solution in the embodiment of the present invention
And discussion, it is clear that as described herein is only a part of example of the present invention, is not whole examples, based on the present invention
In embodiment, the every other implementation that those of ordinary skill in the art are obtained on the premise of creative work is not made
Example, belongs to protection scope of the present invention.
For the ease of the understanding to the embodiment of the present invention, make further by taking specific embodiment as an example below in conjunction with attached drawing
Illustrate, and each embodiment does not form the restriction to the embodiment of the present invention.
The test method for the single event upset fault resistance of on-board software based on ERC32 that the present embodiment is provided, this method
ERC32 On-board software test platforms are run on, are specifically included：
The TESCTR registers carried using the ERC32 chips of ERC32 On-board software test platforms, are run according to program
The characteristics of area SRAM, designs the function that mono- dislocations of EDAC and two dislocation failures are injected to described program Operational Zone SRAM；
The characteristics of carrying software locks according to program storage area EEPROM, designs to EEPROM and injects mono- dislocations of EDAC and two
The function of wrong failure；
The corresponding direct fault location function module of the failure function is finally loaded into the SRAM of tested spaceborne computer
Middle compilation run, simulates the single-particle failure in spaceborne computer, has to realize to the anti-single particle function of the On-board software
The test of effect property.
Further, the function of mono- dislocations of EDAC and two dislocation failures being injected to described program Operational Zone SRAM is specifically wrapped
Include：
The data on the ERC32 data/address bus of EDAC functions are opened, by 32 data bit, 1 bit parity check position and 7 Chinese
Plain code (CB [6:0]) totally 40 data form, and pass through Hamming code (CB [6:0] rectifying one and checking two) is carried out to remaining 33 data
EDAC is verified, and obtains check value；Then：
(1) include to the failure function of SRAM areas injection mono- dislocations of EDAC：The data of specified memory are read, it is correct to calculate its
EDAC check values, according to correct check value, produce EDAC check values one wrong, finally utilize the TESCTR registers
To EDAC check values one wrong caused by specified memory injection, complete to inject EDAC to described program Operational Zone SRAM areas
The function of one dislocation failure；
(2) include to the failure function of SRAM areas injection two dislocations of EDAC：The data of specified memory are read, it is correct to calculate its
EDAC check values, then inject correct EDAC check values to the specified memory using the TESCTR registers, at the same time will
The data of the specified memory data write error one, according to data one wrong, parity check bit also can be one wrong, so far completes
To the function of described program Operational Zone SRAM areas injection two dislocation failures of EDAC.
Further, the characteristics of carrying software locks according to program storage area EEPROM, designs to EEPROM and injects EDAC mono-
The function of dislocation and two dislocation failures specifically includes：
Since program storage area EEPROM carries software locks, it is necessary to write correct data sequence to specified address, just may be used
To unlock, data can be just write after unlocking, then：
(1) mono- dislocations of EDAC are injected to EEPROM
After reading the data for specifying address, only unlock to preceding 32 data fields, data one wrong then are write this refers to
Determine address, check bit area does not unlock, and the correct verification of not wrong data, so far completes to note to EEPROM before check code is still at this time
Enter the function of mono- dislocation failures of EDAC；
(2) two dislocations of EDAC are injected to EEPROM
After reading the data for specifying address, only unlock to preceding 32 data fields, data two wrong then are write this refers to
Determine address, so far complete the function to EEPROM injection two dislocation failures of EDAC.
Wherein, design and inject mono- dislocations of EDAC and two dislocation failures to described program Operational Zone SRAM and injected to EEPROM
During the power function of mono- dislocations of EDAC and two dislocation failures, which has 4 incoming parameters, this 4 incoming parameters point
Mono- dislocations of SRAM injection EDAC, two dislocations of SRAM injection EDAC, mono- dislocations of EEPROM injection EDAC, EEPROM notes Yong Yu not be determined
Enter whether two dislocation functions of EDAC open.After power function is devised, the power function is called at the beginning of On-board software,
And the error injection function of needing to test is opened by the incoming parameter of input.
For this method when it is implemented, building checking system platform first, system uses structure as shown in Figure 1, including one
The PC machine 1, one for being used for carrying out cross compile of platform installation (SuSE) Linux OS sends target by serial ports to spaceborne computer
The ground checkout equipment 2 and spaceborne computer 3 for the remote measurement that code, simulation inter satellite link, display On-board software hand down.These
The concrete function that equipment is provided is as follows：
The PC machine for being used for carrying out cross compile of installation (SuSE) Linux OS：Cross compile is carried out to program, so as to adding
Add the On-board software after single-particle direct fault location function to be compiled, generate the object code that can be run；
Ground checkout equipment 2：Be connected by serial ports with spaceborne computer, by generated in the PC machine of cross compile two into
Object code processed is sent to spaceborne computer 3, and the telemetry that the state and On-board software to program operation pass down is shown；
Spaceborne computer：To run the unit of On-board software, possess and receive the object code that ground checkout equipment 2 is sent,
And the function of operational objective code.
Refering to what is shown in Fig. 2, in operating process during whole working platform, once complete single-particle inversion fault test
Journey (will also open the corresponding direct fault location function module of corresponding failure function and be added to compiling fortune in tested On-board software
OK) specifically include：
First, when needing to carry out single-particle fault test, direct fault location will can with the addition of in the PC machine 1 of cross compile
On-board software after function module carries out cross compile, the binary object code after generation change；
Then, the object code after compiling is loaded into the SRAM of spaceborne computer 3 by ground checkout equipment 2 and carried out
Operation, direct fault location function module can trigger the failure opened in single-particle failure after operation；
Finally, handling result of the On-board software to each failure of the spaceborne computer is obtained by telemetry intelligence (TELINT), with complete
Into the test of the anti-single particle function validity of the On-board software.
Wherein, the code after compiling is sent to spaceborne computer by ground checkout equipment by serial ports, by the spaceborne meter
Code after compiling is loaded into SRAM by the monitoring software of calculation machine storage in the prom.Specifically, spaceborne computer 3 will receive
To object code be loaded into SRAM, the code is performed after reception.Code is that burning exists in actual model
In EEPROM, moved in SRAM and run by the monitoring cured in the prom in spaceborne computer 3, single-particle failure is also to be subject to too
Sky radiation just occurs, and here in order to verify the reliability of the anti-single particle failure of On-board software, takes software simulated injection
Single-particle failure, and be a kind of means of testing by way of object code is loaded into and to be run in SRAM by serial ports, the test hand
Section is able to verify that the correctness of the in-orbit rear anti-single particle trouble handling function of On-board software.
Shown in refer to the attached drawing 3, for the flow chart of the single-particle direct fault location function added in spaceborne computer, the present embodiment
In experimental satellite On-board software in single-particle troubleshooting it is as follows：(1) SRAM areas occur mono- dislocations of EDAC troubleshooting be
It will be passed under wrong address remote measurement, one dislocation of SRAM areas, which counts, adds one, and software does not reset；(2) two dislocations of EDAC occur for SRAM areas
Troubleshooting is will to be passed under wrong address remote measurement, and two dislocation of SRAM areas, which counts, adds one, software reset；(3) EEPROM areas occur
The troubleshooting of mono- dislocations of EDAC is will to be passed under wrong address remote measurement, and one dislocation of EEPROM areas, which counts, adds one, and software does not reset；
(4) troubleshooting that two dislocations of EDAC occur for EEPROM areas is will to be passed under wrong address remote measurement, and two dislocation of EEPROM areas, which counts, to be added
One, software does not reset.
The test method of spaceborne computer software anti-single particle failure test using the above method and step
Card.Table 1 below~4 are experimental result.It can be seen that the results show that after SRAM injection mono- dislocations of EDAC in table 1, program is correctly examined
A dislocation is corrected after measuring a dislocation, mono- dislocations of EDAC of SRAM count increase in telemetry, and reset count does not increase；Table
The results show that after SRAM injection two dislocations of EDAC in 2, program is correctly detecting two dislocations of EDAC, reset count in telemetry
Increase shows software reset's mistake, and two dislocation of SRAM areas counts plus one, SRAM areas, two dislocation address correctly passes down；Result is shown in table 3
Show, after EEPROM is filled with mono- dislocations of EDAC, program is correctly detecting mono- dislocations of EDAC, one dislocation of EEPROM areas in telemetry
Count and add one, reset count does not increase, normal program operation；In table 4 the results show that after EEPROM is filled with two dislocations of EDAC,
Program is correctly detecting two dislocations of EDAC, and EDAC two dislocations in EEPROM areas count plus one in telemetry, and reset count does not increase,
Normal program operation.Test result indicates that single-particle failure is correctly injected to, On-board software correctly captures single-particle failure, and
According to the correct processing single-particle failure of design, the test for the On-board software anti-single particle failure that old place face is realized by software mode
Methods experiment success.
Table 1：The experimental result of one dislocation troubleshooting telemetry of SRAM areas
Table 2：The experimental result of two dislocation troubleshooting telemetry of SRAM areas
Table 3：The experimental result of two dislocation troubleshooting telemetry of EEPROM areas
Table 4：The experimental result of two dislocation troubleshooting telemetry of EEPROM areas
Method provided by the invention, runs on ERC32 platforms, the characteristics of using SRAM, EEPROM each, design to
Mono- dislocations of SRAM, EEPROM injection EDAC, the software function of two dislocations, and the function is added in On-board software to be tested
Compilation run, realizes the simulation of single-particle failure in spaceborne computer, test single event upset fault resistance of on-board software function
Correctness.This method is for SRAM and EEPROM, without open jtag interface, without connecting emulator, whenever and wherever possible, by
The code of mono- dislocations of EDAC or two dislocation direct fault locations is added in On-board software can realize test On-board software anti-single particle event
Hinder the purpose of function.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any
Those skilled in the art the invention discloses technical scope in, to the present invention deformation or replacement done, should all cover
Within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the scope of the claims.
Claims (7)
1. a kind of test method of the single event upset fault resistance of on-board software based on ERC32, it is characterised in that this method is run
In ERC32 On-board software test platforms, specifically include：
The TESCTR registers carried using the ERC32 chips of ERC32 On-board software test platforms, according to program Operational Zone
The characteristics of SRAM, designs the function that mono- dislocations of EDAC and two dislocation failures are injected to described program Operational Zone SRAM；
The characteristics of carrying software locks according to program storage area EEPROM, designs to EEPROM and injects mono- dislocations of EDAC and the event of two dislocations
The function of barrier, is not Operational Zone since EEPROM is the memory block of On-board software, therefore the single-particle inversion failure of EEPROM needs
Detected and found by the On-board software for operating in SRAM；
The direct fault location function module is finally loaded into compilation run in tested On-board software, simulates spaceborne computer
In single-particle failure, to realize the test to the anti-single particle function validity of the On-board software.
2. the test method of the single event upset fault resistance of on-board software according to claim 1 based on ERC32, its feature
It is, the function that mono- dislocations of EDAC and two dislocation failures are injected to described program Operational Zone SRAM specifically includes：
The data on the ERC32 data/address bus of EDAC functions are opened, by 32 data bit, 1 bit parity check position and 7 Hamming codes
Totally 40 data compositions, the EDAC that by the Hamming code remaining 33 data are carried out with rectifying one and checking two are verified, and obtain check value；
Then：
(1) include to the function of SRAM areas injection mono- dislocation failures of EDAC：The data of specified memory are read, it is correct to calculate its
EDAC check values, according to correct check value, produce EDAC check values one wrong, finally using the TESCTR registers to
EDAC check values one wrong caused by specified memory injection, complete to inject EDAC mono- to described program Operational Zone SRAM areas
The function of dislocation failure；
(2) include to the failure function of SRAM areas injection two dislocations of EDAC：The data of specified memory are read, it is correct to calculate its
EDAC check values, then inject correct EDAC check values using the TESCTR registers to the specified memory, while should
The data that specified memory data write error is one, according to the data of wrong one, parity check bit also can be one wrong, so far complete to
The function of two dislocation failures of EDAC is injected in described program Operational Zone SRAM areas.
3. the test method of the single event upset fault resistance of on-board software according to claim 1 based on ERC32, its feature
It is, EEPROM is the program storage area in spaceborne computer, and the On-board software run in sram need to be maintained, and is resisted
Single-particle inversion failure.The characteristics of carrying software locks according to program storage area EEPROM, designs to EEPROM and injects EDAC mono-
Wrong and two dislocation failures functions specifically include：
Since program storage area EEPROM carries software locks, it is necessary to write correct data sequence to specified address, can just open
Lock, can just write data, then after unlocking：
(1) mono- dislocations of EDAC are injected to EEPROM
After reading the data for specifying address, only unlock to preceding 32 data fields, data one wrong then are write this specifies ground
Location, check bit area does not unlock, and the correct verification of not wrong data, so far completes to inject to EEPROM before check code is still at this time
The function of mono- dislocation failures of EDAC；
(2) two dislocations of EDAC are injected to EEPROM
After reading the data for specifying address, only unlock to preceding 32 data fields, data two wrong then are write this specifies ground
Location, so far completes the function to EEPROM injection two dislocation failures of EDAC.
4. the test method of the single event upset fault resistance of on-board software according to claim 1 based on ERC32, its feature
It is, designs and inject mono- dislocations of EDAC and two dislocation failures to described program Operational Zone SRAM and inject EDAC mono- to EEPROM
During wrong and two dislocation failures power functions, the power function has 4 incoming parameters, and the incoming parameter is respectively used to determine
Determine mono- dislocations of SRAM injection EDAC, two dislocations of SRAM injection EDAC, mono- dislocations of EEPROM injection EDAC, EEPROM injections EDAC two
Whether dislocation function opens.
5. the test method of the single event upset fault resistance of on-board software according to claim 4 based on ERC32, its feature
It is, after designing the power function, the power function, and the incoming ginseng for passing through input is called at the beginning of On-board software
Number opens the single-particle failure for needing to inject.
6. the test method of the single event upset fault resistance of on-board software according to claim 1 based on ERC32, its feature
It is, direct fault location function module is added to compilation run in tested On-board software and is specifically included：
First, amended On-board software can be compiled to the code after being compiled in the PC machine of cross compile.This is repaiied
On-board software after changing with the addition of the direct fault location function module, and be called at On-board software beginning, pass through incoming ginseng
Number opens the function of the corresponding single-particle failure that need to be injected；
Then, the code after compiling is loaded into the SRAM of spaceborne computer by ground checkout equipment and is run, run
Direct fault location function module can trigger the failure opened in single-particle failure afterwards；
Finally, handling result of the On-board software to each failure of the spaceborne computer is obtained by telemetry intelligence (TELINT), to complete
State the test of the anti-single particle function validity of On-board software.
7. the test method of the single event upset fault resistance of on-board software according to claim 6 based on ERC32, its feature
It is, the code after compiling is sent to spaceborne computer by the ground checkout equipment by serial ports, by the spaceborne computer
Storage monitoring software in the prom the code after compiling is loaded into SRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711207545.XA CN107992412B (en) | 2017-11-27 | 2017-11-27 | ERC 32-based satellite-borne software single event upset fault resistance testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711207545.XA CN107992412B (en) | 2017-11-27 | 2017-11-27 | ERC 32-based satellite-borne software single event upset fault resistance testing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107992412A true CN107992412A (en) | 2018-05-04 |
| CN107992412B CN107992412B (en) | 2021-05-11 |
Family
ID=62032185
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711207545.XA Active CN107992412B (en) | 2017-11-27 | 2017-11-27 | ERC 32-based satellite-borne software single event upset fault resistance testing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107992412B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240127A (en) * | 2018-11-20 | 2019-01-18 | 上海航天控制技术研究所 | Simulation and verification platform and emulation verification method |
| CN109739774A (en) * | 2019-01-25 | 2019-05-10 | 上海创景信息科技有限公司 | EDAC direct fault location and detection method |
| CN111708695A (en) * | 2020-06-12 | 2020-09-25 | 上海航天计算机技术研究所 | AT 697-based cache single event upset resistant effect verification method |
| CN111813688A (en) * | 2020-06-15 | 2020-10-23 | 上海航天计算机技术研究所 | Method and system for evaluating single event upset resistance reliability of aerospace software |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201828914U (en) * | 2010-07-16 | 2011-05-11 | 北京航空航天大学 | System for positioning FPGA (field-programmable gate array) chip sensitive area |
| CN102096627A (en) * | 2009-12-11 | 2011-06-15 | 上海卫星工程研究所 | Device for testing single event upset fault resistance of on-board software |
| CN102270162A (en) * | 2011-07-29 | 2011-12-07 | 中国航天科技集团公司第五研究院第五一三研究所 | Fault-tolerant guide method applied to SPARCV8 structure computer |
| US20120078853A1 (en) * | 2010-09-21 | 2012-03-29 | Cambridgesoft Corporation | Systems, methods, and apparatus for facilitating chemical analyses |
| US20140281810A1 (en) * | 2013-03-15 | 2014-09-18 | Silicon Space Technology Corporation | Memory circuit incorporating error detection and correction (edac), method of operation, and system |
| CN104851467A (en) * | 2015-05-20 | 2015-08-19 | 中国空间技术研究院 | Function verification method for SRAM with EDAC function for use in space navigation |
| CN107144783A (en) * | 2017-05-10 | 2017-09-08 | 哈尔滨工业大学 | Support unit and the SRAM type FPGA appraisal procedures of multidigit direct fault location |
-
2017
- 2017-11-27 CN CN201711207545.XA patent/CN107992412B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102096627A (en) * | 2009-12-11 | 2011-06-15 | 上海卫星工程研究所 | Device for testing single event upset fault resistance of on-board software |
| CN201828914U (en) * | 2010-07-16 | 2011-05-11 | 北京航空航天大学 | System for positioning FPGA (field-programmable gate array) chip sensitive area |
| US20120078853A1 (en) * | 2010-09-21 | 2012-03-29 | Cambridgesoft Corporation | Systems, methods, and apparatus for facilitating chemical analyses |
| CN102270162A (en) * | 2011-07-29 | 2011-12-07 | 中国航天科技集团公司第五研究院第五一三研究所 | Fault-tolerant guide method applied to SPARCV8 structure computer |
| US20140281810A1 (en) * | 2013-03-15 | 2014-09-18 | Silicon Space Technology Corporation | Memory circuit incorporating error detection and correction (edac), method of operation, and system |
| CN104851467A (en) * | 2015-05-20 | 2015-08-19 | 中国空间技术研究院 | Function verification method for SRAM with EDAC function for use in space navigation |
| CN107144783A (en) * | 2017-05-10 | 2017-09-08 | 哈尔滨工业大学 | Support unit and the SRAM type FPGA appraisal procedures of multidigit direct fault location |
Non-Patent Citations (3)
| Title |
|---|
| GOTHENBURG, SWEDEN: "ESA DSP Day 2016 Workshop Proceedings", 《AMICSA&DSP》 * |
| 吴晓青、龙翔、杨雄: ""基于32位SPARC微处理器的EDAC设计"", 《软件》 * |
| 陆灵君、胡晓刚: ""一种EEPROM中星载软件高可靠维护方法"", 《中国现代小卫星技术发展研究论文集》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240127A (en) * | 2018-11-20 | 2019-01-18 | 上海航天控制技术研究所 | Simulation and verification platform and emulation verification method |
| CN109739774A (en) * | 2019-01-25 | 2019-05-10 | 上海创景信息科技有限公司 | EDAC direct fault location and detection method |
| CN111708695A (en) * | 2020-06-12 | 2020-09-25 | 上海航天计算机技术研究所 | AT 697-based cache single event upset resistant effect verification method |
| CN111813688A (en) * | 2020-06-15 | 2020-10-23 | 上海航天计算机技术研究所 | Method and system for evaluating single event upset resistance reliability of aerospace software |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107992412B (en) | 2021-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Cheynet et al. | Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors | |
| Sawant et al. | Software testing techniques and strategies | |
| CN107992412A (en) | The test method of single event upset fault resistance of on-board software based on ERC32 | |
| Bozzano et al. | Improving system reliability via model checking: The FSAP/NuSMV-SA safety analysis platform | |
| Kooli et al. | A survey on simulation-based fault injection tools for complex systems | |
| Bozzano et al. | The COMPASS approach: Correctness, modelling and performability of aerospace systems | |
| CN108710551B (en) | SPARC processor-based single event upset fault injection test method and system | |
| CN103529820B (en) | A kind of direct fault location test macro and method of testing being applicable to embedded device | |
| Höller et al. | A virtual fault injection framework for reliability-aware software development | |
| Hasan et al. | Translating circuit behavior manifestations of hardware Trojans using model checkers into run-time Trojan detection monitors | |
| Calvagna et al. | Automated conformance testing of Java virtual machines | |
| Vedder et al. | Combining fault-injection with property-based testing | |
| Goddard | Validating the safety of embedded real-time control systems using FMEA | |
| Kharchenko | Independent verification and diversity: Two echelons of cyber physical systems safety and security assurance | |
| Nicolescu et al. | A software fault tolerance method for safety-critical systems: Effectiveness and drawbacks | |
| Kharchenko et al. | Fault insertion testing of FPGA-based NPP I&C systems: SIL certification issues | |
| Hui et al. | Metamorphic testing integer overflow faults of mission critical program: A case study | |
| CN111708695A (en) | AT 697-based cache single event upset resistant effect verification method | |
| Qu et al. | Research on security evaluation of space used very large scale integration (VLSI) | |
| Yao et al. | Research on metamorphic testing for oracle problem of integer bugs | |
| Boniol et al. | PHYLOG: a model-based certification framework | |
| Isha | Software testing techniques and strategieg | |
| Nicolescu et al. | On the use of model checking for the verification of a dynamic signature monitoring approach | |
| Nicolescu et al. | Efficiency of transient bit-flips detection by software means: a complete study | |
| Babeshko et al. | NPP I&C safety assessment by aggregation of formal techniques |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 201109 Minhang District, Shanghai Road, No. 1777 spring Applicant after: Shanghai Spaceflight Institute of TT&C And Telecommunication Address before: 200080 Shanghai city Hongkou District street Xingang Tianbao Road No. 881 Applicant before: Shanghai Spaceflight Institute of TT&C And Telecommunication |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |