JPH0916423A - Error correcting method - Google Patents

Abstract

PURPOSE: To provide the error correcting method which severely protects a specific block in an information word. CONSTITUTION: An encoding circuit 2 adds inspection bits to input data 1, which are sent out to a communication path 4 through a channel 3. An information word which is received through the communication path 4 is inputted to a decoding circuit 6 through a channel 5. The decoding circuit 6 multiplies the received information word D by the transposed matrix HT of a parity inspection matrix H to generate a syndrome S and further makes error corrections according to the pattern of the syndrome S. The information after having errors corrected and being decoded is outputted as output data 7. The parity inspection matrix H has the structure shown in 6-1 and functions for correcting all errors in the specific block in the information word and correcting one-bit errors occurring outside the block at the same time with errors in the block in addition to one-bit error correction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction method for automatically correcting an error to improve the reliability of an apparatus / system, and particularly under a bad working environment due to temperature, vibration, noise and the like. The present invention relates to an error correction method used in industrial devices / systems that must operate normally, or devices / systems requiring reliability such as medical care, aerospace, and public systems.

[0002]

2. Description of the Related Art There are many conventional methods for automatically correcting errors, such as the following. (1) A method in which the circuit / device is tripled and the majority of the output is taken. (2) A method of duplicating circuits / devices so that each circuit / device has an inspection function, and if one of the circuits detects an error by the inspection function, the other output is made a normal output. (3) A method of restarting the operation when an error is detected. (4) A method of applying an error correction code to automatically correct an error.

Of these, the present invention relates to a method using an error correction code. Error correction codes have been conventionally studied as a code theory, and many codes having various functions have been put to practical use in the fields of computers, communications, and AV equipment.
In particular, in the field of computers that require high-speed automatic error correction, it has a function of 1-bit error correction / 2-bit error detection in consideration of a soft error due to noise etc. for a device using a semiconductor memory. The sign is mainly used.

Here, the basic technique of the error correction code will be briefly described. FIG. 16 is a diagram showing a general automatic error correction method using an error correction code. In FIG. 16, the input data 91 is given to the encoding circuit 92. The encoding circuit 92 adds a check bit based on a parity check matrix described later. Information encoded in this way is called an "information word". The information word is sent to the communication path 94 as transmission information via the channel 93. Channel 9
4 transmits the transmission information and gives the reception information to the communication destination.
The received information is sent to the decoding circuit 96 via the channel 95, and the decoding circuit 96 decodes the received information to generate reproduction information, that is, output data 97.

However, in the middle of the communication path 94, a disturbance factor such as malfunction or external noise (shown as a noise source 99 in the figure).
The received information appearing on channel 95 is not always correct and may contain errors. It is the role of the decoding circuit 96 to correct this error. Although this figure assumes a communication system, the error correction code is often applied to a memory system in many cases. In that case, the communication path 94 becomes the actual memory element, and the channel 9
It can be considered that 3 corresponds to writing to the memory and channel 95 corresponds to reading from the memory.

When an information word is generally represented by an n-bit binary number and D = (d _0, d _{1, ...,} d _n-1 ), an r-bit check determined by a code is included therein. Including a bit. The encoding method is often expressed by a parity check matrix of r rows and n columns (hereinafter, referred to as H matrix) having binary numbers of 0 and 1 as elements. The following relationship is established between the information words D and H matrix that do not contain errors. That is,
The check bit is previously determined as D so that the following relationship is established.

[0007]

## EQU2 ## D.H ^T = 0 (2) Here, H ^T is a transposed matrix in which the rows and columns of H are interchanged. At this time, if an error occurs in D for some reason, the calculation result of the left side of the above equation (2) is not 0 (r-bit zero vector). This result is called syndrome S and is represented by a vector consisting of r bits. That is, if S = 0, it is determined that there is no error, if S ≠ 0, the error is detected, and the position and size of the error are obtained and corrected by analyzing the pattern of S based on H. This is the principle of code error correction. How to construct the code having the required function is equal to how to construct the H matrix.

Recently, due to the rapid development of memory devices, devices having a simultaneous input / output of a plurality of bits such as 4, 8 and 16 bits per one device are becoming central. A device / system using such an element has a patent No. 1239.
1-bit error correction, 2-bit error detection, 1-byte error detection as seen in No. 430 (November 13, 1984) and the like, or Patent No. 1236411 (1984, 1
A code having a 1-byte error correction / 2-byte error detection function as seen in (October 17) has been used. Here, the byte means a unit of a plurality of bits such as 4, 8, 16 and the like.

As described above, an error occurs in the information word due to various physical factors, and the information word needs to be corrected. Although an error can occur in any part of an information word, an information word often contains a very important information part in general, and it may be desirable to correct all errors in this part. For example, address information in an information word, control information, pointer information in a database, etc. correspond to this, and include very important information as compared with other data parts. It is clear that an error in this part has a significant effect on the subsequent processing. Therefore, it is necessary to take measures so that the important part is not affected by an error caused in other parts of the word as much as possible. That is, it is necessary to strongly protect a specific part of an information word compared to other parts, and a code including a part of the information word having a different degree of protection is required.

Under such a background, the above-mentioned 1-bit error correction / 2-bit error detection code and 1-byte error correction /
It is clear that the 2-byte error detection code cannot sufficiently meet the requirement.

Generally, as a code in which the degree of protection in an information word is changed in digit units, conventionally, for example, IEEE Transactions on Information Theory, vol.
Published in IT-3, no.4, pp. 600-607, October 1967
The paper “On Linear Unequa” by B. Masnick and J. Wolf
Unequal Err as shown in “Error Protection Codes”
or Protection Code (UEP code) has been proposed and theoretically studied.

[0012]

[Problems to be Solved by the Invention]
The EP code has a large problem from an economical point of view because it is very complicated to decode and requires a large number of check bits.

In particular, considering a computer information word, with respect to a block of a plurality of bits such as address information and control information existing at a position determined in the word, each bit in the block is errored to a uniform degree. Often, the model you want to protect is sufficient. However, the degree of protection inside the block and the degree of protection outside the block are different, and the former is naturally stronger. Also at this time, the protection for each bit outside the block may be uniform. In addition, a function to correct a 1-bit error that occurs in an arbitrary bit in an information word due to a physical influence from the outside, and a function to correct all errors that occurred in the block existing at the fixed position earlier are added. A code model with is practically sufficient.

With such a simple model, decoding is inevitably easy and the number of check bits must be small.
In this 1-bit error correction, a main error in a semiconductor memory device (even in a multi-bit output device) is a random 1-bit error, and an error due to external noise is often a 1-bit error other than in a memory. That is the basis.

Based on the above consideration regarding the degree of protection of the information word, a practical error correction method that replaces the conventional complicated code is required. The present invention has been made in view of the above point, and corrects all the errors occurring in a part of an information word that requires special protection against errors, and further corrects another part. It is an object of the present invention to provide an error correction method which has a function of correcting these 1-bit errors even when they occur at the same time, and which can be realized at high speed and economically.

In particular, the present invention discloses a code in which even if a block error and a 1-bit error occur at the same time, these are correctly corrected and the error in the block is prevented from being erroneously corrected. That is, the degree of protection within a block is such that all errors that occur within the block can be corrected, and even if an error of 1 bit is added outside the block, these are correctly corrected and the information within the block is protected, Is the strongest degree. On the other hand, outside the block, if there is an arbitrary random 1-bit error, it is corrected to the correct degree, and when compared within the block, the level of protection is low. This provides a code in which the block is strongly protected from errors.

[0017]

According to the present invention, in order to solve the above problems, a check bit is added and b (b>
2) In an error correction method for an information word having one block of bits, a parity check matrix H,

[0018]

(Equation 3)

(However, the parity check matrix H
Each submatrix of I _b = b × b identity matrix, I _r = r × r
Identity matrix, P = (r−b) × b matrix composed of different (b) column vectors of (r−b) degree with weight 2 or more, 0 = maximum (2 ^rb −r−1) A zero matrix composed of b-th column vector of Q, with Q = weight 2 or more (r
-B) In the next different column vector, the information word encoded based on the maximum (2 ^rb -r-1) column vector not included in the matrix P) is ^added to the parity. An error correction method is provided in which a check matrix H is multiplied to generate an r-bit syndrome S, and an error is corrected based on the syndrome S which is not all zero.

In the error correction, when the syndrome S coincides with the column vector h _i (0≤i≤n-1) forming the parity check matrix H,
The i-th bit of the information word is corrected and the syndrome
When the column S does not match any of the column vectors h _i , the matrix G _F = [P | I _rb ] (where I _rb = (r
−b) × (r−b) identity matrix), S · G _F ^T is calculated, and when the S · G _F ^T is all zero, it is determined that the block is in error, and the upper b of the syndrome S is An error correction method for correcting an error in the block using bits as an error pattern is provided.

Further, in correcting the error, the S
When the result of G _F ^T is not zero, it is determined that there is a 1-bit error outside the block in addition to the error of the block, and S S G _F ^T is the matrix Q or the matrix I _r. When a column vector of weight 1 equal to the submatrix I _{r- b} in the block is matched, the error of 1 bit corresponding to the matched vector is corrected and the error of the block is corrected by using the upper b bits of the syndrome as an error pattern. Further, when the S · G _F ^T matches the column vector p _j (0 ≦ j ≦ b−1) forming the matrix P, the j-th bit in the check bits of the upper b bits is corrected. Of the upper b bits of the syndrome S
There is provided an error correction method for correcting an error in the block using a pattern obtained by inverting the th bit as an error pattern.

[0022]

When a check word is added based on the parity check matrix H and an information word having one block of b bits is received, the received information word is multiplied by the parity check matrix H, and the generated syndrome S is added to the generated syndrome S. Based on this, error detection / correction is performed.

In error detection / correction, the syndrome S is first compared with the columns of the parity check matrix H to detect and correct a 1-bit error. Further SG
_{When F} ^T is all zero, the error in the block is detected and corrected. Furthermore, when S · G _F ^T is not zero, S
Comparing G _F ^T with the sub-matrix of the parity check matrix H to detect and correct out-of-block errors and also to correct block errors.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.
I do. FIG. 1 is a block diagram showing a schematic configuration of the present invention.
You. The input data 1 has a check bit by the encoding circuit 2.
It is added and sent to the communication path 4 through the channel 3.
Information words received via communication channel 4 are transmitted through channel 5.
It is input to the decoding circuit 6. The decoding circuit 6 receives the received information.
Transpose matrix H of parity check matrix H to report word D ^TSquared
To generate the syndrome S (6-1 in the figure), and
Error correction based on the pattern of this syndrome S
Perform (6-2 in the figure). The error is corrected and the decoding is completed
The information is output as output data 7 and is used for another purpose.
It is.

Here, the encoding and decoding methods in the present invention are characterized by the above-mentioned parity check matrix H (hereinafter referred to as H matrix). The H matrix has a characteristic structure as shown by 6-1 in the figure, and its details will be described with reference to FIG.

FIG. 2 is a diagram showing the structure of the information word format and the parity check matrix H of the error correction method of the present invention. FIG. 2A shows a format of an information word having a length of n bits. That is, a block having a length of b bits is positioned at the beginning, and a check bit consisting of r bits is placed at the end. The block may be placed at any position as long as it does not overlap with the check bit, but here it is placed at the beginning without loss of generality. If it is not actually the head position, the corresponding partial matrix in the H matrix may be moved in H accordingly.

FIG. 2B shows an information word expressed as a vector. d ₀ to d _b-1 are block information, and d
_nr to d _n-1 are r check bits. FIG.
(C) shows the structure of the H matrix. The H matrix is composed of sub-matrices H _F , H ₀ and I _r .

As shown in FIG. 2 (d), H _F is composed of b columns, the upper stage is composed of a b × b unit matrix I _b , and the lower stage is composed of b different column vectors having a weight of 2 or more. (R
-B) xb matrix P. H ₀ is b × in the upper row
Zero matrix of (2 ^rb −r−1) (at maximum configuration), P in the lower stage
(B−r) × (2 ^rb −r−1) (maximum configuration) composed of non-zero column vectors (maximum 2 ^rb −r−1 column vectors) excluding b columns and columns with a weight of 1 used in Hour) matrix Q. Therefore, when the lower submatrices P and Q of the H matrix are made adjacent to each other to form a matrix [P | Q], this is (r−b) × (2 ^rb + b−) consisting of column vectors having different weights of 2 or more. r-1) (maximum configuration). Further, I _r is an r × r identity matrix. H _F and I _r correspond to the block and the check bit portion, respectively.

The maximum bit length n _max of the information word of this code
Is

[0030]

## ^EQU00004 ## It can be expressed by n _max = 2 ^rb + b-1 (4). It can be proved that this is the theoretical maximum length for a code having the functions described below.

Next, it is proved that the code disclosed in the present invention, that is, the H matrix shown in FIG. 2 satisfies the following three functions. [Function 1] 1-bit error correction [Function 2] All error correction in block [Function 3] Error correction for both 1-bit error and block error In general, in order to enable these error corrections, It is only necessary to be able to prove that the syndromes due to the error are different.

First, the fact that [Function 1] can be realized is H
This can be proved by the fact that all column vectors in the matrix are different. That is, the syndrome S due to a 1-bit error is an r-bit vector obtained by calculating the left side D · H of the equation (2). If this matches any column vector in the H matrix, the bit corresponding to that column can be corrected as an error. Therefore, if all the column vectors in H are different, a 1-bit error can be identified and corrected.

Next, the realization of [Function 2] is that H
_Since the upper part of _F is I _b , it can be easily proved from the fact that the syndromes of the upper b bits are different even if any error occurs in the block. However, at this time, it must be proved that it does not match the 1-bit syndrome. A column vector having a pattern close to the 1-bit error syndrome exists in I _r (check bit part) having the same partial matrix as I _b . The syndrome due to a 1-bit error in this part has a weight of 1 in its upper b bits and its lower (r−b) bits are all zero, which is different from the syndrome due to any error in the block. On the contrary, there is a possibility that all the lower (r−b) bits become zero due to the error in the block, but at this time, the syndrome of the upper b bits always has a weight of 2 or more, and the syndrome due to the 1-bit error of the inspection unit is generated. There is no match. Therefore, it was proved that [Function 2] was satisfied.

Next, the [function 3] will be proved in different cases depending on whether the 1-bit error occurs in the portion corresponding to H ₀ or in the portion corresponding to I _r (check bit portion). There is a need.

First, when a block error and a 1-bit error in the portion corresponding to H ₀ occur at the same time, the syndrome does not match the syndrome due to another 1-bit error in the portion corresponding to H _0. . This is because a block error that occurs at the same time and a syndrome due to the 1-bit error cannot have all zeros in the high-order b bits, while there is a zero matrix in the high-order of H ₀ .
Therefore, this does not coincide with the 1-bit error in the portion corresponding to the H ₀ portion. It can also be easily shown that this does not coincide with the 1-bit error in the part corresponding to I _r , and the syndrome due to other errors in the block.

Next, it will be described that, in addition to the block error, when a 1-bit error occurs in a portion (check bit portion) corresponding to the I _r portion, this syndrome does not match the syndrome due to another 1-bit error. The syndrome caused by the block error and the 1-bit error in the check bit portion that occur at the same time may be such that the upper b bits are all zero (that is, the specific 1-bit error in the block and the specific 1-bit error in the check unit are ), At this time the lower (r-
b) The syndrome of bits matches the one-column vector of P, and hence no syndrome due to any one-bit error. In addition, the syndrome top b
Even if the bit matches the syndrome of the high-order b bits due to the block error, the syndrome of the low-order (r−b) bits is sure to be proved from the fact that both are different at this time.

From the above, it has been proved that the H matrix shown in FIG. 2 satisfies all of [Functions 1 to 3]. FIG.
3 is a flowchart showing a processing procedure of an error correction method of the present invention. According to the invention, the detection and correction of errors in the received information word is performed by the following steps. [S1] The information word is multiplied by the transposed matrix of the H matrix,
The syndrome S, which is the r-th vector, is calculated. [S2] It is determined whether the syndrome S is a zero vector (a vector in which all the elements are zero). If it is a zero vector, it is assumed that there is no error in the information word, and decoding is completed. If it is not a zero vector, the process proceeds to step S3. [S3] Syndrome S and n forming H matrix
Compare each of the column vectors. If Syndrome S
When it matches the i-th (0 ≦ i ≦ n−1) column vector h _i , the process proceeds to step S4. If there is no matching column vector, the process proceeds to step S5. [S4] In the information word, the i-th bit counting from 0, that is, d _i is corrected, and the decoding is completed. [S5] Submatrix P of H matrix and matrix G _F consisting of (rb) unit matrix

[0038]

## EQU00005 ## The conversion syndrome S '= S.G ^T is calculated based on G _F = [P | I _rb ] ...
Determine if this is a zero vector. If it is a zero vector, it is recognized that an error exists only in the block, and the process proceeds to step S11. If it is not a zero vector, it is recognized that an error exists outside the block in addition to the error in the block, and the process proceeds to step S6. [S6] The conversion syndrome S ′ is compared with the column vector forming the partial matrix Q of the H matrix. Similarly, the conversion syndrome S ′ is compared with the column vector of weight 1 forming I _rb of the partial matrix I _r of the H matrix, respectively. If the transformation syndrome S ′ matches one of these column vectors, it is recognized that the error outside the block is in the portion corresponding to the matrix Q or the matrix I _rb , and the process proceeds to step S7. If there is no matching column vector, it is recognized that the error outside the block is in another portion, and the process proceeds to step S8. [S7] The bit of the information word corresponding to the position of the column vector that coincides in step S6 is corrected. Further, in order to correct the block error, the process proceeds to step S11. [S8] The conversion syndrome S ′ is compared with the column vector p _i forming the partial matrix P of the H matrix. If the conversion syndrome S ′ matches the i-th (0 ≦ i ≦ b−1) column vector p _i , it is recognized that the error outside the block is in the check bit portion, and the process proceeds to step S9. If there is no matching column vector, it is recognized that there is an uncorrectable error, the error is detected, and the process ends. [S9] The i-th check bit is corrected. Further, in order to correct the block error, the process proceeds to step S10. [S10] The i-th bit in the syndrome S, that is, s _i (0 ≦ i ≦ b-1) is inverted and set as an error pattern, and the process proceeds to step S11. [S11] The upper b bits of the syndrome S are used as an error pattern to correct the block and the decoding is completed.

According to the above algorithm, it is first determined in steps S1 and S2 whether or not there is an error, and in steps S3 and S4, a 1-bit error at an arbitrary position is corrected. If it is not a 1-bit error, it is further determined in step S5 whether it is an error inside the block or a combination with an error outside the block. If there are errors in the block, all errors are corrected in step S11. The error outside the block is identified in step S6 and step S8, and respectively in step S7 and step S8.
Correct with 9. In particular, the out-of-block error detected in step S8 is an error in the check bit that directly corresponds to the block information. Therefore, the check bit is corrected and the error pattern for correcting the intra-block error is also corrected. If the position of the error cannot be specified in steps S6 and S8, the error cannot be corrected by the method of the present invention.

A configuration for specifically realizing the present invention will be described below. FIG. 4 is a block diagram showing the configuration of the communication system according to the embodiment of the present invention, particularly the internal configuration of the decoding circuit. A check bit is added to the input data 1 by the encoding circuit 2 and sent to the communication path 4 through the channel 3.
The information word received through the communication path 4 is input to the syndrome generation circuit 8 through the channel 5 and creates the syndrome 9. Further, this syndrome is input to the syndrome decoding circuit 10 and outputs an error indication signal (error pattern) 11 giving a specific error instruction, and the correction circuit 1
At 2, the error in the received information is inverted and corrected. The corrected information is output via the channel 7 and used for another purpose.

Next, it will be shown that the encoding circuit and the decoding circuit can be actually constructed by using the more specific code examples in the above configuration. FIG. 5 is a diagram showing an H matrix when b = 3 and r = 7. The maximum length of the information word is n _max = 18 bits from the equation (4). As shown in D of FIG. 5, the block length is 3 bits, the check length is 7 bits, and the length of the part excluding the block and the check part is The length is 8 bits. Therefore, with respect to the information word of _{d 0 ~d 17, d 0 ~d} 2
There data in the block, d ₁₁ to d ₁₇ is check bits. Each bit of the information word and each column of the H matrix have a one-to-one correspondence as shown in the figure. The requirements for the submatrix forming the H matrix have been described in the description of FIG. 2, but in the present embodiment, the matrices P and Q are as shown in the figure.

FIG. 6 is a circuit diagram showing details of the encoding circuit 2 in this embodiment. This circuit constructs an information word of 18 bits by adding check bits d ₁₁ to d ₁₇ from the H matrix shown in FIG. The check bit is generated from the following relational expression.

[0043]

(Equation 6)

Here, the sign in which the plus sign is circled is
Indicates exclusive OR. FIG. 6 shows d₀~ D_Ten11 bits
The data portion consisting of is the bit d of the information word D. ₀~ D_TenWhen
Output as it is, and the upper 3 bits d of the check bit₁₁
~ D₁₃Respectively d_0,d_1,d_TwoDirectly from the data signal of
It is generated. 2-14, 2-15, 2
-16 and 2-17 generate check bits from the above equation, respectively.
It is a circuit to be formed and is a multi-input parity checker. You
That is, if the number of logic 1 input signals is even,
If the force is 0, the output is 1 if it is odd. Note that
The 2-input parity checker is a so-called exclusive OR gate.
It is.

FIG. 7 is a circuit diagram showing details of the syndrome generation circuit 8. This circuit is constructed by the following relational expression based on the H matrix shown in FIG.

[0046]

(Equation 7)

S _{0 to} s ₆ are the elements of the syndrome S, and 8-0 to 8-6 are multi-input parity checkers constructed based on the above equations. The reception information received by the decoding circuit 8 is given a dash (') to distinguish it from the transmission information output from the encoding circuit. That is, there is no error in the transmission information immediately after being encoded, but some error may be mixed in the reception information at the stage of passing through the communication path (or memory).
The two are treated separately.

Next, a circuit that performs error correction based on the created syndrome will be described. FIG. 8 is a block diagram showing the configuration of the syndrome decoding circuit 10. Reference numeral 15 is an error bit pointer generation circuit (1) that inputs the syndrome signal group 9 consisting of r bits and points out the bit in which an error exists. When an error of 1 bit in the received information exists, the bit error is pointed out. It is a circuit that outputs a signal. Reference numeral 17 is an error bit pointer signal group consisting of the n bits.

Reference numeral 16 denotes a syndrome conversion circuit, which is a circuit for multiplying the syndrome by a specific matrix G _F to obtain a converted and compressed syndrome, and outputs a (r−b) -bit converted syndrome signal 18 to a converted syndrome buffer circuit 19. Output. The conversion syndrome buffer circuit 19 is a circuit that confirms that there is no 1-bit error and outputs the conversion syndrome, and outputs the (r−b) -bit conversion syndrome signal group 20. Signal 29
Is a signal indicating that there is no 1-bit error.

21 is an error byte pointer generation circuit
(1) When the conversion syndrome is all zero, it is determined that the error is in the block, and the upper b bits (S _F ) of the syndrome are output as the error byte pointer signal 22.

On the other hand, when the conversion syndromes are not all zero, the circuits 23 and 24 judge that the error is a one-bit error inside and outside the block and generate an error pointer for both.

An error bit pointer generation circuit (2) 23 uses the conversion syndrome signal group 20 to output an error indication signal for 1 bit in the data excluding the inspection section and the block section, or the latter half of the inspection section (rb). ) This is a circuit that creates an error indication signal for 1 bit in the check bit. 25 and 26 are outputs of this circuit, and 25 is (n-
An error pointer signal group for the (b-r) -bit data portion, and 26 is an error pointer signal group for the (r-b) -bit check bit.

Reference numeral 24 is an error bit pointer generation circuit.
(3) The error indication signal for the first half b bits of the inspection unit is created. 27 is an output signal thereof, which is a pointer signal group for the b-bit check bits.

Reference numeral 28 denotes an error byte pointer generation circuit (2), which outputs a b-bit error pointer signal 31 for the block from the output signal group of the error bit pointer generation circuit (2) 23 and the upper b bits of the syndrome signal group 9. create.

On the other hand, 30 is an error byte pointer generation circuit.
(3) and, from the output signal group 27 of the error bit pointer generation circuit 24 and the upper b bits of the syndrome signal group 9, a b bit error pointer signal 32 for the block
Create

33 is an error pointer synthesizing circuit, which is 1
The error bit pointer signals and the error byte pointer signals generated from the circuits 5, 21, 23, 24, 28 and 30 are combined to generate an n-bit error bit pointer signal group 11
Create

Next, a decoding method and its circuit for the specific code shown in FIG. 5 will be shown, and in general, r
A method of decoding from the bit syndrome S to the general configuration of the code shown in FIG. 2 will also be described.

First, when S = 0, it is determined that there is no error in the received information, as shown in equation (2). When S ≠ 0,
It is regarded as error detection, and when the r-bit syndrome matches the H matrix column vector, it is regarded as an error in the bit corresponding to the column vector, and a signal for correction is output.

FIG. 9 shows the error bit pointer generation circuit (1) 1
It is a figure which shows the specific circuit of FIG. For all 18-bit information
H-matrix for which the 7-bit syndrome of the input is
It is shown whether or not it matches the column vector pattern of. 18
18 columns of H at the inputs of the 7-input AND gates
A matrix column pattern is associated with each gate. Input
The circles mean inverted input, and the value of 0 in the column vector
Corresponds to the element you have. 7-bit syndrome line
If any of the vectors matches, then the corresponding AN
Output an error pointer signal with logical value ‘1’ from D gate
If they do not match, a logical value "0" is output. like this
18-bit pointer signal e ₀~ E₁₇Is raw
Is done.

The left side of FIG. 10 is a syndrome conversion circuit 16 which converts the syndrome based on the H matrix. Here, the transformation matrix G _F is defined as follows.

[0061]

## EQU8 ## G _F = [P | I _rb ] ... (8) That is, G _F is (r−b) × b partial matrix P and (r−b) × (r in the H matrix. (B) is an (r−b) × r matrix in which the unit matrix I _rb is adjacent to each other, and at this time, the following relationship exists between G _F and H _F.

[0062]

[Equation 9] G _F · H _F = 0 (9) That is, G _F is orthogonal to H _F.

A concrete method of creating S · G _F ^T is shown in FIG.
From the code shown in

[0064]

(Equation 10)

And from now on

[0066]

[Equation 11]

Is obtained. here,

[0068]

[Equation 12] S = [S _F | S _P ] (12) where S _F = [s _0, s _1, s ₂ ], S _P = [s _3, s _4, s _5, s _6, ]] and the compressed syndrome after conversion is

[0069]

Equation 13] S · G _F ^T = ^{_{[s 0,, s 1,,}} s 2,, s 3, ] ‥‥‥‥ When (13),

[0070]

[Equation 14]

The conversion syndrome group 18 of (rb) bits (7-3 = 4 bits in this embodiment) is generally output. FIG. 10 shows a circuit that satisfies the above relational expression, and four parity checkers 16-0 based on the above expression.
16-3.

The conversion syndrome buffer circuit 19 is on the right side of FIG. 10, and the error bit pointer generation circuit (1) 15
In S, when S ≠ 0, but a 1-bit error is not detected, the error generated in the block is corrected by using this (r−b) -bit conversion syndrome, or 1 generated outside the block in addition to the intra-block error. A buffer circuit for correcting a bit error. That is, this is a circuit for sending the conversion syndrome created by the syndrome conversion circuit 16 to the circuit of the next stage when there is no 1-bit error. Therefore, when all the pointer signals output from the error bit pointer generation circuit (1) 15 are zero, the conversion syndrome is converted into a 2-input AND gate 19-
It is sufficient to output from 0 to 19-3. At this time, if the output signal 29 of the inverting input AND gate 19-4 is "1", it means that the error in the received information is not only one bit.

FIG. 11 shows an error byte pointer generation circuit (1).
21 is a circuit for indicating the high-order b bits S _F of the syndrome 9 as it is as a signal group of 22 as a byte error signal group when the converted syndrome signal group 20 is all 0, not 1-bit error. At this time, when the output of the inverting input AND gate 21-3 is "1", the conversion syndrome 20
Is determined to be all zero.

The lower part of FIG. 12 shows the error bit pointer generation circuit (2) 23, and the conversion syndrome buffer circuit 19
From the conversion syndrome 20 which is the output of the above, for the error inside the block and the error of 1 bit outside the block, the latter half (r−b) bit of the check unit and the block and the check unit do not belong (n−r−b). It is a circuit that points out a 1-bit error position in bit data. In this embodiment, error bit pointer signals for d ₃ ′ to d ₁₀ ′ and d ₁₄ ′ to d ₁₇ ′ are created, and I _rb = I ₄ of the conversion syndromes 20 and Q column vectors and I _r. It is determined whether or not the column vector corresponding to the column vector matches, and if they match, 23-3 to 23-10, 2
The output of the 4-input AND gates 3-14 to 23-17 is set to "1". Error bit pointer signal group 25 (e ₃ '
To e ₁₀ ') are each d _3' ~d ₁₀ 'indicates the error position of the data, also the error bit pointer signal group 26 (e _14'
To e ₁₇ ') is, d _14', respectively showing the error position of the check bits to d ₁₇ '.

The upper part of FIG. 12 shows the error byte pointer generation circuit (2) 28, and the error bit pointer generation circuit (2) 2
In addition to the 1-bit error in the data pointed out by the circuit output of No. 3, this circuit points out an intra-block error.
At this time, the error pattern of the block is equal to S _F, now, under the condition that there is 1 bit to '1' in the signal group 25 and 26 is a circuit output of the error bit pointer generation circuit (2) 23, The b bit pattern of S _F may be output. In this embodiment, taking the OR logic with respect to a total of 12 bits of the error bit pointer signal groups 25 and 26, when the output of OR gate 28-3 is '1', an _{S F s 0, s 1,} s ₂ is a 2-input AND gate 28-0 to 28-2
Output respectively. These block error patterns are represented by an error byte pointer signal group 31 of e ₀ ″, e ₁ ″, e ₂ ″ corresponding to the block data d ₀ ′ _, d ₁ ′ _, d ₂ ′. .

The lower part of FIG. 13 shows an error bit pointer generation circuit (3) 24, which is a circuit for pointing out the error position for the first half b bits of the inspection section. In this embodiment, d ₁₁ ′ -d
An error bit pointer signal for ₁₃ 'is created, and it is determined whether the conversion syndrome 20 and the column vector of P match, and if they match, 4-input AND gates 24-1 to 24-24.
The output of -3 becomes "1", and the error pointer signal group 27 is obtained.

The upper part of FIG. 13 shows the error byte pointer generation circuit (3) 30. Error bit pointer generation circuit (3)
The block error position is pointed out with respect to the 1-bit error in the b-bit portion of the first half of the inspection unit indicated by 24. At this time, the block error pattern is not the S _F itself as described above, but the exclusive OR of the block error pattern and the b-bit error pattern indicated by the error pointer signal group 27 is output (30-3 in this embodiment). , 30-4, 30-5 exclusive OR gate outputs) are the block error patterns. Therefore, 30-6
As shown in the 3-input OR gate of No. 30-0, 30-1, under the condition that a pointer signal of 1-bit error exists in the circuit output of the error bit pointer generation circuit (3) 24,
This block error pattern may be output from the output of the 2-input AND gate 30-2. The block error pattern output is the error byte pointer signal group 32 of e ₀ ″ ″, e ₁ ″ ″, and e ₂ ″ ″.

FIG. 14 shows the error pointer synthesizing circuit 33, which calculates 15, 21, 23, 24 for n-bit data.
It is a circuit in which the error pointer signal output from each of the circuits 28 and 30 is ORed for each bit. Therefore, four types of pointer signals are input from the circuits 15, 21, 28, and 30 to the first b bits corresponding to the block, and four-input OR gates (23-0, 23-0,
23-1, 23-2) creates a block error pointer of b bits, and becomes a signal group 11 of E _{0 to} E ₂ . on the other hand,
The error pointer signal for the bit outside the block is divided into the signal coming from the circuit 15 and the signal coming from the circuits 23 and 24.
There are types, so there are 2 inputs O for each bit.
An error bit pointer is created by the R gate (23-3 to 23-17). In this embodiment, the signal group 1 of E _{3 to} E ₁₇
Output as 1.

FIG. 15 is a diagram showing details of the correction circuit 12. The n-bit received signal is corrected by the error pointer signal 11 from the syndrome decoding circuit 10. That is, a pointer signal E _i (0 ≦ i ≦ n−
If 1) is' 1 ', the corresponding received signal d _i ' is inverted and corrected. If the pointer signal is "0", the received signal is output as it is because there is no error in the received signal. The corrected output signal group is shown as 7. In this embodiment, the syndrome decoding circuit 1
For the error pointer signal group 11 and the received signal group 5 from 0, the exclusive OR is performed for each bit for each of the gates 12-0 to 12-12.
At -17, the corrected received signal group 7 is output.

When the syndrome S is not zero and the pointer signals E _i (0≤i≤n-1) are all zero, it means that there is an uncorrectable error. Although not shown in this embodiment, outputting a signal for detecting such an error can be easily realized by a simple logic circuit.

As is clear from the circuit diagrams of FIGS. 6 to 15, the circuit for executing the error correction method of the present invention is composed of only a relatively simple combinational logic circuit. Therefore, it can be easily realized by an integrated circuit, and its encoding and decoding operations are fast. By incorporating such a circuit in the communication control circuit, a highly reliable system can be realized.

The above description is centered on the code of b = 3, r = 7 shown in FIG. 5, the data length of which is 18 bits, and the check length is 7 bits. It is clear that the configuration can be configured for any b and r, n. Also, the blocks that have important information are
Although it is assumed that the block is located at the head of the information word in the embodiment, the block can be similarly constructed at any position. That is, it is clear from the general code structure of the present invention shown in FIG. 2 that the partial matrix H _F may be moved to the position where the block starts. Further, all the circuit configurations described in the embodiments may be exactly the same, and by moving H _F , the order of input signals in only some circuits is moved accordingly.

Further, although the application to the communication system is assumed in the description of the embodiments, the present invention can also be applied to the memory system. In that case, the communication path 4 becomes the actual memory element, the channel 3 writes to the memory,
It can be considered that the channel 5 corresponds to reading from the memory. The operations of the encoding circuit 2 and the decoding circuit 6 are exactly the same in both the communication system and the memory system.
It is possible to incorporate them as part of the memory control circuit.

[0084]

As described above, according to the present invention, when an important information part such as address information, control information, etc., which has a great influence on subsequent operations when an error occurs in that part, is included in an information word. The present invention provides a new code structure that has not existed in the past for strongly protecting this and a high-speed correction circuit structure. As a result, even if another 1-bit error occurs in addition to an arbitrary error in this portion, these can be corrected at high speed and economically, and the reliability of the device and system adopting the error correction method by this code can be improved. It can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of the present invention.

FIG. 2 is a diagram showing the structure of an information word format and a parity check matrix H in the error correction method of the present invention.

FIG. 3 is a flowchart showing a processing procedure of an error correction method of the present invention.

FIG. 4 is a block diagram showing a configuration of a communication system that is an embodiment of the present invention.

FIG. 5 is a diagram showing an example of an H matrix when b = 3 and r = 7 in the present invention.

FIG. 6 is a circuit diagram showing details of an encoding circuit.

FIG. 7 is a circuit diagram showing details of a syndrome generation circuit.

FIG. 8 is a block diagram showing a configuration of a syndrome decoding circuit.

FIG. 9 is a circuit diagram showing details of an error bit pointer generation circuit (1).

FIG. 10 is a circuit diagram showing details of a syndrome conversion circuit and a conversion syndrome buffer circuit.

FIG. 11 is a circuit diagram showing details of an error byte pointer generation circuit (1).

FIG. 12 is a circuit diagram showing details of an error bit pointer generation circuit (2) and an error byte pointer generation circuit (2).

FIG. 13 is a circuit diagram showing details of an error bit pointer generation circuit (3) and an error byte pointer generation circuit (3).

FIG. 14 is a circuit diagram showing details of an error pointer synthesis circuit.

FIG. 15 is a circuit diagram showing details of a correction circuit.

FIG. 16 is a diagram showing a general automatic error correction method using an error correction code.

[Explanation of symbols]

 1 Input data 2 Encoding circuit 3, 5 channels 4 Communication channel 6 Decoding circuit 6-1 Syndrome generation 6-2 Error correction 7 Output data

Claims (7)

[Claims] 1. A check bit is added, and b (b> 2).
In an error correction method for an information word having one block of bits, a parity check matrix H However, each sub-matrix of the parity check matrix H is: I _b = b × b unit matrix, I _r = r × r unit matrix, P = (r−b) -th order b different b with weight 2 or more (R−b) × b matrix composed of column vectors, 0 = zero matrix consisting of maximum (2 ^rb −r−1) b-th column vector, Q = having weight 2 or more (r -B) The next different column vector, which is composed of a maximum of (2 ^rb -r-1) column vectors that are not included in the matrix P, and the parity is added to the information word encoded based on: An error correction method that multiplies a check matrix H to generate an r-bit syndrome S and corrects an error based on the syndrome S that is not all zero. 2. The correction of the error is performed by the syndrome S including the parity check matrix H.
When the column vector h _i (0 ≦ i ≦ n−1) that composes is matched, the i-th bit of the corresponding information word is corrected, and the syndrome S matches any of the column vectors h _i. If not, the matrix P and (r−b) × (r−b)
Matrix G _F = [P | I composed of unit matrix I _rb
rb ], the syndrome S is multiplied to obtain S · G _F ^T , and when the S · G _F ^T is all zero, it is determined that the block is in error, and the upper b bits of the syndrome S are used as an error pattern. The error correction method according to claim 1, wherein an error of the block is corrected. 3. The error correction further comprises determining that, in addition to the block error, there is a 1-bit error outside the block when the result of S · G _F ^T is not zero, When S · G _F ^T matches a column vector of weight 1 equal to the matrix Q or the submatrix I _rb in the matrix I _r , the 1-bit error corresponding to the matched column vector is corrected and 3. The error correction method according to claim 2, wherein the error of the block is corrected by using the upper b bits of the syndrome S as an error pattern. 4. The correction of the error further comprises a column vector p _{j in which the} S · G _F ^T constitutes the matrix P.
When it matches (0 ≦ j ≦ b−1), the j-th bit in the check bits of the high-order b bits is corrected, and the pattern in which the j-th bit of the high-order b bits of the syndrome is inverted is erroneous. The error correction method according to claim 3, wherein an error in the block is corrected as a pattern. 5. The uncorrectable error is detected by the fact that S · G _F ^T does not match any of the column vectors p _j forming the matrix P. Error correction method. 6. The error correction method according to claim 1, wherein the error correction method is used in an information communication system. 7. The error correction method according to claim 1, wherein the error correction method is used in a memory system.