JPH0361210B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for correcting double byte errors, and particularly to a circuit for correcting random double byte errors at high speed with a small amount of circuitry.

In order to improve the data reliability of file devices such as magnetic files, Reed-Solomon codes and b-adjacent error correction codes are often used to correct single byte errors. When using a medium with a lower error rate than a magnetic medium, or in order to further improve data reliability, it is desirable to use a Reed-Solomon code that has the ability to correct random double-byte errors. However, one of the drawbacks of double-byte error correction is that it requires a large circuit to decode the location of the erroneous byte and the error pattern.

One byte is generally represented by m bits,
To correct such byte errors, it is necessary to decipher the error position and error pattern within the code. For deciphering (decoding), a method is used in which an error position is first calculated from the syndrome, and then an error pattern is calculated using the obtained error position. Decoding Reed-Solomon codes to correct double-byte errors is known, but this method has the disadvantage that the decoding process is complicated because it takes the following three steps.

(Step 1) Find the coefficients of a quadratic equation regarding the error byte position, ie, an error location polynomial, from the syndrome.

(Step 2) Find two roots of the error location polynomial. This root represents the erroneous byte position.

(Step 3) Two error patterns corresponding to each error position are determined from the two determined error positions and the syndrome.

For this reason, conventional decoders including double-byte error correction have the drawbacks of large decoding delay time and large circuit scale. Here, the decoding delay time is the time from the end of reception of a data block to the start of transfer of corrected data. In a file device, data is transferred serially in byte units. Once the received data block is stored in the buffer memory, errors are corrected and then transferred to the host device.

Traditional double-byte error correction methods
Steps 1 and 2 start from the block reception end time.
and 3 are executed, errors in the data stored in the buffer memory are corrected, and then transferred to the host device, resulting in a long decoding delay time. Particularly when interleaving a plurality of double-byte error correcting Reed-Solomon codes for burst error correction, this decoding delay time becomes considerably large, which poses a practical problem.

In order to reduce the decoding delay time, a method is needed to directly determine the error location and pattern from the syndrome without establishing an error location polynomial, but such a method has not been known so far.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an error correction circuit that directly determines error positions and patterns for double-byte error correction Reed-Solomon codes without establishing an error location polynomial.

The double byte error correction circuit of the present invention reads the data byte from the buffer memory without setting an error location polynomial after receiving the data block, and transfers the data byte to the host device while correcting the error. The decoding delay time is zero. Furthermore, the amount of circuitry for the error correction circuit is small. Furthermore, it has a structure suitable for interleaving multiple codes.

The double byte error correction circuit of the present invention includes a parity check matrix H of a double byte error correction Reed-Solomon code constructed using a primitive element α of Galois GF (2 ^m ) defined by an arbitrary integer m, 1 1……1……1 α ¹ α ² ………α ⁱ ………α ⁿ H= α ² α ⁴ ………α ²ⁱ ………α ²ⁿ α ³ α ⁶ ………α ³ⁱ … ...In a system that encodes data according to α ³ⁿ ,
A decoding circuit for correcting double byte errors randomly occurring in an n-byte received code block is provided. Here n=2 ^m -1 and a byte is represented by m bits. Here, 4 bytes in the n-byte block are check bytes, and (n-4) bytes are information bytes.

The decoding circuit of the present invention includes the first row of the parity check matrix H,
A syndrome generation circuit that generates syndromes S ₁ , S ₁ , S ₂ and S ₃ corresponding to the second, third and fourth rows, and an exclusive ORS ₀ between the syndromes;
A circuit that takes S ₁ , S ₁ S ₂ and S ₂ S ₃ and the exclusive
A logic circuit that can determine an error pattern by detecting A ₀ · A _{2 A 1 2 = 0 with respect to ORA 0 = S 0 S 1 , A 1 =} ^S _{1 S 2 and A 2 =} S ₂ S ₃ . It consists of

Before explaining embodiments, the principle of the present invention will be explained. In the present invention, syndromes S ₀ , S ₁ ,
S ₂ and S ₃ are generated according to the parity check matrix H. That is, if b ₁ , b ₂ , ......, _bo are received code words of n bytes (byte b ₁ is m bits), the syndrome is generated according to the following formula S ₀ = b ₁ ... …b _i …b _o S ₁ =b ₁ α ¹ …b _i α ⁱ …b _o α ⁿ S ₂ =b ₁ α ² …b _i α ²ⁱ …b _o α ²ⁿ S ₃ =b ₁ α ³ ...b _i α _3i ...b _o α ³ⁿ } (1) Here, indicates exclusive OR. Assuming that an error of error pattern e _i occurs in the i-th byte b _i and an error pattern e _j occurs in the j-th byte b _j , the syndrome is expressed as shown below. However, e _i ≠0, e _j ≠0,
i=j ₀ S ₀ =e _i e _j S ₁ =e _i α ^{i e} _j α ^j S ₂ =e _i α ²ⁱ e _j α ^2j S ₃ =e _i α ³ⁱ e _j α ^3j } (2) The above syndrome S ₀ , S ₁ , ^S ₂ and ^{S 3} _have bytes b _o , ^b _o-1 ^,
It is generated by inputting ..., b ₂ and b ₁ in this order.

In the present invention, after the syndrome is generated, the syndrome register is further shifted to search for error locations. Assuming a double symbol error expressed by equation (2), the syndromes (contents of the syndrome register) S ₀ , S ₁ , S ₂ , and S ₃ after being shifted k times are expressed by the following equations.

S ₀ =e _i e _j S ₁ =e _i α ^i+k e _j α ^j+k S ₂ =e _i α ^2(i+k) e _j α ^2(j+k) S ₃ =e _i α ^{3 (i+k)} e _j α ^3(j+k) } (3) Exclusive OR between the above syndromes, i.e.
A ₀ =S ₀ S ₁ , A ₁ =S ₁ S ₂ and A ₂ =S ₂ S ₃ are expressed by the following formulas.

A ₀ =S ₀ S ₁ =e _i (1α ^i+k )e _j (1α ^j+k ) A ₁ =S ₁ S ₂ =e _i (1α ^i+k e _j (1α ^j+k A ₂ =S ₂ S ₃ = e _i (1α ^i+k ) α ^2(i+k) e _j (1α ^j+k ) α ^2(j+k) } (4) Here, L=A ₀ A ₂ A ₁ ² Then, L= only when the number of shifts k is k=ni or k=nj
It can be determined that the value is 0 as follows. L=
By substituting the previous equation (4) into A ₀ A ₂ A ₁ ² , L is expressed as the following equation (5)
It is expressed as

L=e _i e _j (1α ^i+k ) (1α ^j+k) (α ^2(i+k) α ^2(j
+k) )(5) Here, since i≠j, α ^2(i+k) α ^2(j+k) ≠0
It is. L=0 is 1α ^i+k =0 or 1
Only when α ^j+k =0. In other words, L=0 only when α ^i+k =1 or α ^j+k =1. Here α ⁿ
=α ⁰ =1, so i+k=n or j+k=n
, that is, L=0 only when k=n−i and k=n−j. i+k=n (or j+k=n)
The fact that L=0 when , can be understood as follows. When i+k=n, 1+α ^i+k in the previous equation (4)
= 0, so A ₀ , A ₁ , and A ₂ are as follows.

A ₀ = e _j (1α ^j+k A ₁ = e _j (1α ^j+k A ₂ = e _j (1α ^j+k ) α ^2(j+k) From this point on, it is clear that A ₀・A ₂ = A ₁ ² = e _j ² (1
α ^j+k ) ²・α ^2(j+k) , so L=A ₀・A ₂ A ₁ ² =
It is 0.

From the above, it has been shown that if an error occurs in byte positions i and j, L=0 when the syndrome register is shifted (n-i) times and (n-j) times. Here, if we prepare an n-byte buffer memory (shift register) and input the n-byte received data bytes b _o , b _o-1 , ..., b ₂ , b ₁ to the syndrome register, At the same time, it is assumed that the buffer memory is also input. and,
Assume that the data stored in the buffer memory is shifted out at the same time as the syndrome register is shifted for error correction. From buffer memory, data bytes b _o , b _o-1 , ...,
b ₁ is shifted out in this order. Therefore, (n-
At the k)th shift, data bytes b _k are output from the buffer memory.

Now, if there is an error in the i-th data b _i and the j-th data b _j (i > j), L = 0 at the (n-1)th shift, and at the same time data byte b is transferred from the buffer memory. _i is output. Furthermore (n-
At the j)th shift, L=0, and data byte b _j is output from the buffer memory. That is, L=0 exactly when the erroneous byte is output from the buffer memory. Therefore, the error can be corrected by finding the error pattern for the byte where L=0.

The error pattern is calculated using the following formula.

e=S ₀ A ₀ ² (A ₀ A ₁ ) ^-1 (6) If error pattern e _i occurs in the i-th byte b _i and error pattern e _j occurs in the j-th byte b _j , then the k-th With the shift (k=ni), L=0, and at this time A ₀ , A ₁ , A ₂ and S ₀ are expressed by the following formula.

S ₀ = e _i e _j A ₀ = e _j (1α ^j+k A ₁ = e _j (1α ^j+k ) α ^j+k A ₂ = e _j (1α ^j+k ) α ^2(j+k) } (7) At this time, the error pattern e becomes equal to e _i as shown in the following equation.

e=S ₀ A ₀ ² (A ₀ A ₁ ) ^-1 = e _i (8) Also, since byte b _i is output from the buffer memory at this time, the error in byte b _i is b _i e _i will be corrected.

Equations similar to the previous equations (7) and (8) also hold true for the error pattern e _j of the j-th byte b _j , and the error in the byte b _j is corrected. Here, there is a formula for calculating the error pattern e other than formula (6), for example, e=S ₀ A ₀
(1√ ₂・₀ ^-1 ) ^-1 , e=S ₀ A ₀ (1A ₂・
Although it can be calculated using A ₁ ^-1 ) ^-1, etc., the calculation method using equation (6) is considered to be the easiest.

As mentioned above, for double byte errors, the error position is determined by L = A ₀ A ₂ A ₁ ² = 0, and the error pattern is determined by e = S ₀ A ₀ ² (A ₀ A ₁ ) ^-1. It will be done.

It will be shown below that even single byte errors can be corrected by said L and e. Now, the i-th byte b _i
If an error of error pattern e _i occurs in , syndromes S ₀ to _{S 3} are expressed by the following formulas.

S ₀ = e _i S ₁ = e _i α ⁱ S ₂ = e _i α ²ⁱ S ₃ = e _i α ³ⁱ } (9) When the syndrome register is shifted k times, the syndrome becomes S ₀ = e _i S ₁ = e _i α ^j+k S ₂ = e _i α ^2(j+k) S ₃ = e _i α ^3(j+k) } (10). A ₀ , A ₁ , A ₂ are A ₀ = S ₀ S ₁ = e _i (1α ^i+k ) A ₁ = S ₁ S ₂ = e _i (1α ^i+k ) α ^i+k A ₂ = S ₂ S ₃ = e _i (1α ^i+k ) α ^2(i+k) } (11) Therefore, for any number of shifts k, L=
A ₀ A ₂ A ₁ ² =0. Also, error pattern e=S ₀
A ₀ ² (A ₀ A ₁ ) ^-1 is e=0 for i+k≠n,
For i+k=n, e=e ₁ . That is,
L=0 for any number of shifts k, but k
Since e=0 when ≠ni, no correction error occurs. Also, when k=n-i, e=e _i and the error is correctly corrected.

It has therefore been shown that single byte errors are corrected just as well as double byte errors.

As described above, in the present invention, a syndrome is generated from received data bytes, the received data is stored in a buffer memory, and when an error is corrected, the syndrome register is shifted and the data bytes are shifted out from the buffer memory while error correction is performed. You can correct the incorrect byte. In other words, errors are corrected while data is being transferred.

Therefore, since data can be transferred immediately after data reception is completed, the decoding delay is considered to be zero. This is one of the features of the present invention, and the decoding delay cannot be made zero in the conventional method in which error correction is performed after setting the error location polynomial.

The present invention will be explained below using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, circuits 1 to 4 are m-bit registers (syndrome registers), and circuit 2
0 to 22 are elements α ¹ of Galois field GF (2 ^m ),
This is a circuit that multiplies α ² and α ³ . However, α is
It is the primordial element of GF (2 ^m ). Circuits 5-12 are each m-bit exclusive OR circuits. In the figure, exclusive OR circuit 5 and register 1 are connected to syndrome S ₀
The exclusive OR circuit, the register 2, and the α ¹ multiplication circuit 20 constitute the generation circuit for the syndrome S ₁ . In addition, the exclusive OR circuit 7, the register 3, and the α ² multiplication circuit 21 function as a generation circuit for syndrome S ₂ .
Exclusive OR circuit, register 4 and α ³ multiplier circuit 22
constitutes the generation circuit of syndrome _S3 .

The circuit 13 is a buffer memory (shift register) that stores n bytes of data. Here n=2 ^m -1 and a byte is m bits. n
Byte data is input to each of the syndrome generation circuits and the buffer memory 13 via the input line d in FIG. Shift clocks for syndrome registers 1-4 and buffer memory 13 are provided by signal lines in FIG. When data byte b _i (m bits) is input to the signal line,
By applying a shift clock to signal line c, data byte b _i is taken into the syndrome register and buffer memory. According to equation (1) above, data byte b _o is input first. and input the shift clock. A similar operation is then performed on data byte b _n-1 . After performing the same operation up to data byte b ₁ , the contents of registers 1 to 4 are expressed by formula (1).
Or syndromes S ₀ to _{S 3} expressed by (2) occur.
Output signal A ₀ = of exclusive OR circuit 9 in FIG.
S ₀ S ₁ , output signal A ₁ of exclusive OR circuit 10 = S ₁
S ₂ and the output signal A ₂ of the exclusive OR circuit 11 = S ₂ S ₃
is input to the error position detection circuit 14. The error position detection circuit 14 uses the signals A ₀ , A ₁ and A ₂ under the condition L=A ₀ A ₂
When A ₁ ² =0 is satisfied, the output signal g is set to logic 1, that is, g=1. The output signal g serves as a gate signal for the gate circuit 16 in FIG. The error pattern decoding circuit 15 in FIG. 1 generates and outputs an error pattern e from the signals A ₀ , A ₁ and S ₀ according to e=S ₀ A ₀ ² (A ₀ A ₁ ) ^-1 . The gate signal g and error pattern signal e are input to a gate circuit 16. The gate circuit 16 is constituted by a normal AND circuit which sets its output f to f=e when the gate signal g is logic 1, and sets its output f to f=0 when the gate signal g is logic 0. Exclusive OR circuit 12 is buffer memory 13
The output signal b of the gate circuit 16 and the output signal f of the gate circuit 16 are subjected to an exclusive OR circuit and a signal h=bf is output.
Said output h of exclusive OR 12 provides an error corrected data byte. In FIG. 1, after the generation of syndromes S ₀ to S ₃ is completed, a shift clock can be input to signal line c to perform error correction. At the kth shift clock, the contents of syndrome registers 1, 2, 3, and 4 become the syndrome expressed by equation (3), and data byte b _ok is output to output b of buffer memory 13.

If there is an error in the data byte b _ok , the output signal g of the error position detection circuit 14 becomes logic 1, and at the same time, the output signal e of the error pattern decoding circuit 15 becomes the error pattern e _{ok of the data byte b ok .} equal and error in data byte b _ok is exclusive OR
Corrected via 12.

In the following, m=4, that is, Galois field GF
(2 ⁴ ). The configuration of the error correction circuit of the present invention for Reed-Solomon codes will be explained. m
=4, the code length n of this code is 15 (= ^24-1 ). Here, 1 byte represents 4 bits. n=
4 bytes out of 15 bytes are inspection bytes and the remaining 11 bytes
A byte is an information byte.

Considering the Galois field GF(2 ⁴ ) modulo the primitive polynomial P(x)=X ⁴ +X+1, the Galois field GF(2 ⁴ )
The 16 elements 0, α ⁰ (=1), α ¹ α ₂ , α ¹⁴ (however, α ¹⁵ = α ⁰ ) are a 4-bit binary vector (a ₀ a ₁ a ) as shown in Figure 2. ₂ a ₃ ).

For example, as shown in the figure, α ⁹ =(0101). Second
This diagram shows the correspondence between the figures and is structured as follows. Any element α ⁱ of Galois field GF(2 ⁴ ) is α ⁰ = (1000), α ¹
= (0100), α ² = (0010) and α ³ = (0001), i.e. α ⁱ = a ₀ α ⁰ a ₁ α ¹ a 2 ^{α 2} _{a 3} α ³ =
It is expressed as (a ₀ a ₁ a ₂ a ₃ ). Here, since the primitive element α is the root of the polynomial P(x), P(α)=1
αα ⁴ =0. Therefore α ⁴ α ⁰ α ¹ = (1100).
Also, for example, α ⁹ is α ⁹ = α ⁴・α ⁴・α ¹ = (α ⁰ α ¹ ) ² α ¹ = (α ⁰ α ² )
α ¹ = α ¹
α ³ = (0101).

In FIG. 1, the α ¹ multiplication circuit 20 is a circuit that multiplies a 4-bit input (a ₀ a ₁ a ₂ a ₃ ) by α ¹ and outputs the result (b ₀ b ₁ b ₂ b ₃ ).

Here, (b ₀ b ₁ b ₂ b ₃ )=α ¹ (a ₀ a ₁ a ₂ a ₃ )=α ¹ (a ₀ α ⁰ a ₁ α ¹
a ₂ α ² a ₃ α ³ ) = a ₀ α ¹ a ₁ α ² a ₂ α ³ a ₃ α ⁴ = a ₀ α ¹ a ₁ α ² a ₂ α ³ a ₃ (α ⁰ α ¹ ) = a ₃ α ⁰ (a ₀ a ₃ ) α ¹ a ₁ α ² a ₂ α ³ = (a ₃ (a ₀ a ₃ ) a ₁ a ₂ ), so b ₀ = a ₃ , b ₁ = a ₀ a ₃ , b ₂ = a ₁ , b ₃ =
a ₂ .

Figure 3 shows the α ¹ multiplier circuit 20 of Figure 1 which corresponds to the above equation.
3 is a block diagram specifically constructed using an exclusive OR circuit 30. FIG.

FIG. 4 is a block diagram specifically configuring the α ² multiplication circuit 21 in FIG. 1, which is constructed by cascading the α ¹ multiplication circuits shown in FIG. 3 in two stages.

Similarly, FIG. 5 is a concrete block diagram of the α ³ multiplication circuit 22 shown in FIG. 1, which is constructed by cascading three stages of the α ¹ multiplication circuits shown in FIG. 3.

Next, the configuration of the error position detection circuit 14 shown in FIG. 1 will be explained. As already explained, this circuit has _the condition _{A 0 A 2} A _{1 2} ⁼
This circuit makes the output g logic 1 only when 0 is established. Condition A ₀ A ₂ A ₁ ² = 0 is the following (12a) ~
This is equivalent to equation (12b).

A ₀ A ₂ A ₁ ² = 0 (12a) A ₁ ² /A ₀ A ₂ = 0 (12b) A ₁ ² /A ₂ A ₀ = 0 (12c) A ₀ /A ₁ ^A _1A2 = 0 (12d) Therefore, the error position detection circuit 14 has the above equation (12a) ~
(12d) can be used. Below, a circuit configuration when using conditional determination (12a) will be described.

FIG. 6 shows a block diagram of the error position detection circuit 14 using the condition A ₀ A ₂ =A ₁ ² . In FIG. 6, a circuit 40 converts input signals A ₀ and A ₂ into a Galois field GF(2 ⁴ ).
This is a circuit that multiplies on A ₀ and A ₂ and outputs A 0 and A 2.
The circuit 41 is a circuit that squares the input signal A ₁ on GF(2 ⁴ ) and outputs A ₁ ² . Here, input A ₀ ,
A ₁ , A ₂ and outputs A ₀ , A ₂ , A ₁ ² are each 4 bits. The circuit 42 receives the output signal A ₀ of the circuit 40.
A 4-bit exclusive OR that takes the exclusive OR of A ₂ and the output signal A ₁ ² of the circuit 41 and outputs A ₀・A ₂ A ₁ ²
It is an OR circuit. Circuit 43 is the output signal of circuit 42
This is an NR circuit that detects that all bits of A ₀ and A ₂ A ₁ ² are zero. The NR circuit 43
The output signal g is set to logic 1 only when A ₀ ·A ₂ A ₁ ² =0.

The multiplication circuit 40 on the GF(2 ⁴ ) can be realized using a random logic circuit consisting of an AND and an exclusive OR circuit or an existing memory element such as a programmable RM (read only memory). In particular, in the case of this embodiment, since the inputs _A0 and _A2 are each 4 bits, and the outputs _A0 and _A2 are 4 bits,
The circuit 40 can be realized with one RM with 8-bit address input/4-bit output (256 words x 8 bits). When using RM, input A ₀ to the upper 4-bit address of RM, input A ₂ to the lower 4-bit address of RM, and store the product A ₀ · A ₂ in the corresponding address location. good.

FIG. 7 is a diagram showing the correspondence between addresses and outputs of the ROM. As shown in the figure, if the ROM address input is A ₀ = α ^p , A ₂ = α ^q , A ₀・A ₂ = α ^p+q is output, and if A ₀ or A ₂ is 0, A ₀・A ₂ =0 is output. The correspondence between addresses and outputs as described above can be constructed using the correspondence between α ⁱ and vector (a ₀ a ₁ a ₂ a ₃ ) shown in FIG. For example, A ₀ = α ⁸ = (1010), A ₂ = α ¹¹ =
(0111) then A ₀・A ₂ = α ⁸⁺¹¹ = α ¹⁵⁺⁴ = α ⁴ =
(1100), so ROM address input A ₀ =
The output corresponding to (1010), A ₂ = (0111) is A ₀・A ₂
= (1100). As above, when m=4,
The multiplier circuit 40 can be realized by one RM with 8-bit address input/4-bit data output (256 words x 4 bits). Generally, the multiplication circuit 40 on GF (2 ^m ) can be realized with one ROM having 2 m bit address input/m bit output (22 ^m words x m bits). 256 words x 8 for a commercially available programmable ROM
Since 1024 words x 8 bits and 4096 words x 8 bits are available, we can use one of these ROMs to create multiplication circuits for GF(2 ⁴ ), GF(2 ⁵ ), and GF(2 ⁶ ), respectively. realizable. The GF(2 ^m ) multiplier circuit where m≧7 is constructed as follows, since 22 ^m words x m bits ROM is not available.
One ROM is not possible. In this case, multiple
GF using ROM or random logic
(2 ^m ) It is necessary to construct a multiplication circuit.

FIG. 8 shows the GF(2 ⁴ ) multiplication circuit 40 as an AND circuit,
A block diagram is shown in which the circuit is constructed using random logic consisting of an exclusive OR circuit. The inputs A ₀ and A ₂ of the GF (2 ⁴ ) multiplier circuit 40 are respectively (a ₀ a ₁ a ₂ a ₃ ),
(b ₀ b ₁ b ₂ b ₃ ), and the product output A ₀ · A ₂ is expressed as (c ₀ c ₁ c ₂ c ₃ ), then the product (c ₀ c ₁ c ₂ c ₃ ) is as follows. is expressed in

(c ₀ c ₁ c ₂ c ₃ ) = (a ₀ a ₁ a ₂ a ₃ )・(b ₀ b ₁ b ₂ b ₃ ) = (a ₀ α ⁰ a ₁ α ¹ a ₂ α ² a ₃ α ³ )・(b ₀ b ₁ b ₂ b ₃ ) =a ₀・α ⁰ (b ₀ b ₁ b ₂ b ₃ ) a ₁・α ¹ (b ₀ b ₁ b ₂ b ₃ ) a ₂・α ² (b ₀ b ₁ b ₂ b ₃ ) a ₃・α ³ (b ₀ b ₁ b ₂ b ₃ ) The above formula is input (b ₀ b ₁ b ₂ b ₃ ) to α ⁰ (b ₀ b ₁ b ₂ b ₃ ) , α ¹
(b ₀ b ₁ b ₂ b ₃ ), α ² (b ₀ b ₁ b ₂ b ₃ ) and _α ³ (b _{0 b 1} b _{2 b 3} ), respectively. If we take AND with a ₃ and then take exclusive OR, we get the product (c ₀ c ₁ c ₂ c ₃ )
is generated. Therefore, G.F.
(2 ⁴ ) The multiplication circuit 40 includes ^α1 multiplication circuits 52, 53 and 54, AND gates 55, 56,
57 and 58 and an exclusive OR circuit 59. α multiplication circuits 52, 53 and 54 are the same as the α multiplication circuit of FIG.

FIG. 9 shows the GF(2 ⁴ ) square circuit 41 in FIG.
The block diagram is shown below. The 4-bit input signal A ₁ and output signal A ₁ ² in the square circuit 41 are expressed as vectors, A ₁ = (a ₀ a ₁ a ₂ a ₃ ), A ₁ ² = (b ₀ b ₁ b ₂ b ₃ ), then b ₀ to _{b 3} are b ₀ = a ₀ a ₂ , b ₁ = a ₂ , b ₂ = a ₁ a ₃ , b ₃
It is expressed as = a ₃ . That is, (b ₀ b ₁ b ₂ b ₃ ) = (a ₀ a ₁ a ₂ a ₃ ) ² = (a ₀ α ⁰ a ₁ α ¹ a ₂ α ² a ₂ α ² a ₃ α ³ ) ² = a ₀ α ⁰ a ₁ α ² a ₂ α ⁴ a ₃ α ⁶ , and since α ⁴ = α ₀ α ¹ and α ⁶ = α ² α ³ , (b ₀ b ₁ b ₂ b ₃ ) = a ₀ α ⁰ a ₁ α ² a ₂ (α ⁰ α ¹ )a ₃ (α
²
α ³ ) = (a ₀ a ₂ ) α ⁰ a ₂ α ¹ (a ₁ a ₃ ) α ²
a ₃ α ³ = ((a ₀ a ₂ ) a ₂ (a ₁ a ₃ ) a ₃ ). Therefore b ₀ = a ₀ a ₂ , b ₁ = a ₂ , b ₂ = a ₁ a ₃
and b ₃ = a ₃ holds true. Therefore, the GF(2 ⁴ ) square circuit 41 is configured as an exclusive OR circuit 50, 51 as shown in FIG.
It is configured using

In general, GF(2 _n ) squared circuits are also exclusive as shown above.
Constructed using an OR circuit.

Also, the GF(2 ⁴ ) square circuit 41 has a 4-bit address input/4-bit output (16 words x 4 bits).
It can also be configured using ROM. In other words, if the ROM is programmed to output A ₁ ² = α ^2p when the address input is _A 1 = α ^p , and output A ₁ ² = 0 when the address input is A ₁ = 0. good. For example, when the address input is A ₁ = α ¹¹ = (0111), A ₁ ² = α ²²
Program the ROM to output = α ^{15 + 7} = α ⁷ = (1101).

The error position detection circuit 14 shown in FIG. 1 is configured as described above. Next, the configuration of the error pattern decoding circuit 15 shown in FIG. 1 will be explained. The error pattern decoding circuit 15 uses equation (6), that is, e=S ₀ A ₀ ² (A _0
A1 ) Can be configured according to ^-1 .

FIG. 10 shows a block diagram of the error pattern decoding circuit 15. In FIG. 10, the circuit 60 has an input
This circuit calculates A ₀ ² (A ₀ A ₁ ) ^-1 from A ₀ and A ₁ on GF(2 ⁴ ), and the circuit 61 is a 4-bit exclusive OR circuit.

FIG. 11 shows the configuration of the circuit 60. circuit 6
0 is a circuit that calculates the output A _{0 2} (A ₀ A ₁ ) ^-1 from the inputs A ⁰ and A ₁ , so as shown in Figure 11, the input A ₀
A circuit 71 takes the exclusive ORA ₀ A ₁ of A _{1 and the} inverse ^element (A ⁰
A circuit 72 for calculating A ₁ ) ^-1 , a circuit 70 for calculating A ₀ squared A ₀ ² , and the above A ₀ ² and (A ₀ A ₁ ) ^-1 as GF(2 ⁴ )
and a multiplication circuit 73 that performs multiplication at. Here, the squaring circuit 70 has the same configuration as the GF(2 ⁴ ) squaring circuit shown in FIG.
It has the same configuration as the multiplication circuit shown in the figure. The circuit 72 for calculating the inverse element (A ₀ A ₁ ) ^-1 of A ₀ A ₁ is composed of random logic or a ROM of ²⁴ words x 4 bits.
Using random logic requires a large amount of circuitry, so it is preferable to use ROM. When using RM, when the address input is A ₀ A ₁ = α ^p , the ROM is designed to output (A ₀ A ₁ ) ^-1 = α ^-p = α ^15-P.
Program it. For example, address input
When A ₀ A ₁ = α ⁶ = (0011), (A ⁰ A ₁ ) ^-1 = α ^15-6
=α ⁹ =(0101) is output. Also, when the address input is A ₀ A ₁ = 0 = (0000), (A ⁰ A ₁ ) ^-1 = 0
Program the ROM to output = (0000). The circuit 60 for calculating A ₀ ² (A ⁰ A ₁ ) ^-1 is configured as described above, but it can also be configured in other ways. Since the inputs A ₀ and A ₁ of circuit 60 are both 4 bits, and the output A ₀ ² (A ⁰ A ₁ ) ^-1 is also 4 bits, circuit 60 has an 8-bit address input/4 bits.
This can be achieved with one RM with bit output ( ²⁸ words x 4 bits). That is, input A ₀ to the upper 4 bits of the ROM address, input A ₁ to the lower 4 bits,
A ₀ ² (A ₀
A ₁ ) ^-1 should be stored.

FIG. 12 is a diagram showing the correspondence between address input and output of this ROM. As shown in the figure, the ROM is programmed to output 0 when address input A ₀ or A ₁ is 0, or when A ₀ =A ₁ . In other cases, i.e. A ₀ ≠ 0 to A ₁ ≠ 0 and
When A ₀ ≠ A ₁ , address input A ₀ = α ^p , A ₁ = α ^q
(p≠q), A ₀ ² (A ⁰ A ₁ ) ^-1 = α ^2p (α ^p
α ^q ) Program the ROM to output ^-1 . For example, the address input is A ₀ = α ⁸ = (1010),
When A ₁ = α ¹¹ = (0111), A ₀ ² (A ⁰ A ₁ ) ^-1 = α ¹⁶ (α ⁸
Since α ¹¹ ) = α ^-6 = α ⁹ , A ₀ ² (A ⁰ A ₁ ) ^-1 = α ⁹
= (0101) is output. The error pattern detection circuit 15 shown in FIG. 1 is configured as described above.

As can be seen from the above description, the double byte error correction circuit of the present invention can directly correct double byte errors with a relatively small amount of circuitry and without setting an error location polynomial. Fully achievable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a double byte error correction circuit according to the present invention, and FIG. 2 is a Galois field diagram.
Diagrams showing the correspondence between elements α ⁱ of GF(2 ⁴ ) and binary vectors. Figure 3 is a block diagram of the α ¹ multiplication circuit, Figure 4 is a block diagram of the α ² multiplication circuit, and Figure 5 is the α ³ multiplication circuit. A block diagram of the multiplication circuit; FIG. 6 is a block diagram of the error position detection circuit; and ^FIG . Figure 8 is a block diagram showing the configuration of a multiplication circuit on GF (2 ⁴ ), Figure 9 is a diagram showing the correspondence between memory addresses and outputs when
A block diagram showing the configuration of a squaring circuit on GF(2 ⁴ ), FIG. ₁₀ is a block diagram of an error pattern ^decoding circuit, and _FIG .
A block diagram showing the configuration of a circuit that calculates A ₀ ² (A ⁰ A ₁ ) ^-1 , Figure 12 is a block diagram showing the configuration of a circuit that calculates A ₀ ² (A ⁰ A ₁ ) from inputs A ₀ and A ₁ on GF (2 ⁴ ). FIG. 7 is a diagram showing the correspondence between memory addresses and outputs when a circuit for calculating ^-1 is implemented using a read-only memory. In the figure, 1, 2, 3, 4 are syndrome registers, 5, 6, 7, 8, 9, 10, 11, 1
2, 30, 42, 50, 51, 59, 61, 71
is an exclusive OR circuit, 20, 21, 22 are α ¹ , α ² ,
α ³ multiplication circuits are shown respectively. 13 is a buffer memory, 14 is an error position detection circuit, 15 is an error pattern decoding circuit, 16 is an AND gate circuit, and 40 is a
A multiplication circuit on GF(2 ⁴ ), 41 a squaring circuit on GF(2 ⁴ ), and 43 a NOR circuit, respectively.
52, 53, 54 are α ¹ multiplication circuits, 55, 56, 5
7 and 58 are AND gate circuits, 60 is a circuit that calculates A ₀ ² (A ⁰ A ₁ ) ^-1 on GF (2 ⁴ ), and 70 is GF
72 shows ^{an inverse element circuit on GF(2 4 )} , and 73 shows a multiplication circuit on GF(2 ⁴ ).

Claims (1)

[Claims] 1. Galois field GF (2 ^m ) defined by an arbitrary integer m
Parity check matrix of double-byte error correction code constructed using primitive element α 111……1……1 1α ¹ α ² ……α ⁱ ……α ^2m-2 1α ² α ⁴ … Double byte error correction in a system that encodes and decodes data according to α ²ⁱ ………α ^2(2m-2) 1α ³ α ⁶ ………α ³ⁱ ………α ^3(2m-2) A circuit receives the encoded data and generates syndromes S ₀ , S ₁ , S 2 and S ₃ corresponding to rows 1, ₂ , 3 and 4 of the parity check matrix from the received data bytes. a syndrome generating circuit that takes the exclusive ORs of the syndromes, S ₀ ○ + S ₁ , S ₁ S ₂ and S ₂ S ₃ , and the exclusive ORs of the syndromes S ₀ S ₁ , S ₁ S ₂ ,
Regarding S ₂ S ₃ (S ₀ S ₁ )・(S ₂ S ₃ )(S ₁
S ₂ ) A double byte error correction circuit consisting of a logic circuit that detects ² = 0 and determines the location and error pattern of the erroneous byte.