JP2534563B2 - Tolerable error successive correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention uses an error correction block code and presets an allowable error bit number that is smaller than the correctable error bit number in the code word. The present invention relates to simplification of an error correction circuit in the case of improving the reliability of data transmission and recording by a decoding method which rejects errors exceeding the number of bits.

(Prior Art and its Problems) FIG. 3 shows an example of a configuration conventionally used as an error correction circuit in which the allowable error bit number (e) is set. In the figure, reference numeral 31 is a syndrome calculation circuit for calculating the syndrome S _Y corresponding to the received word Y in accordance with the processing determined from the received word Y according to the code system of the block code. 32, S _Y type a, 1 bit of the allowable error determination output indicating whether the error corresponding to the S _Y is allowable error (DET)
And the allowable error bit location table (EL _e ) for indicating each error bit position in the case of allowable error, the ROM (R
ead Only Memory). 33 inputs Y and EL _e , inverts the bit of the received word Y at the error bit position of e bits or less indicated by EL _e , corrects the error, and then
This is a permissible error correction circuit that outputs the permissible error correction word C to the outside, and is configured by an exclusive OR gate or the like.

According to the above configuration example, since the table is used to search the error position, the error correction process can be realized at high speed. However, assuming that the code word length of the block code to be used is n bits, the parity length (= syndrome length) is m bits, and the allowable error bit number is e, the information necessary for designating an error position of 1 bit is provided. Quantity is Is the smallest integer value greater than or equal to x), so the storage capacity (number of bits) of the allowable error bit location table 32
Is Becomes The above shows that the storage capacity of the table increases exponentially as m (parity length) increases,
Depending on the value of m, realization may be difficult.

As another conventional method, instead of 32 in FIG. 3, a table in which syndromes for all error patterns (allowable error patterns) having an allowable error bit number e or less (allowable error pattern) are listed together with information indicating the error position is used. , There is a method of searching whether or not a syndrome matching the syndrome S _Y corresponding to the received word exists in the table. The storage capacity of the table in this method is such that the error pattern of j (integer) bit error is Since there are individuals, the maximum Bit. Therefore, when e is relatively small, the storage capacity can be reduced as compared with the former, but the maximum processing required for retrieval is The difficulty of significantly increasing the number of processing steps (or time) arises because it must involve accessing the table once.

(Object of the Invention) The present invention alleviates the problem of the number of allowable error correction processing steps (or time) that occurs in the conventional method and the increase in the size of the table used for allowable error correction, and the processing is fast, and The table size used is relatively small,
It is an object of the present invention to provide a tolerable error successive correction circuit that can be easily integrated into an IC and software.

(Structure and Operation of the Invention) [Structure] Hereinafter, the word length, the parity length, and the allowable number of error bits of the code word to be used are respectively n, m, and e bits.

FIG. 1 is a diagram showing one structural example of a tolerable error successive correction circuit according to the present invention. Reference numeral 11 in the figure is a syndrome calculation circuit, which inputs a successive correction word Z obtained in the process of sequentially correcting the received word Y for each error bit, and which has a predetermined value depending on the algebraic structure of the error correction block code to be used. Performs a syndrome calculation process (for example, a known process using a matrix operation using a check matrix, a power operation of a root vector of a generator polynomial, a remainder operation of a polynomial using a shift register, etc.) The corresponding m-bit long syndrome S is output to the outside.

12 is the smallest m _e bit (m _e <m _e that can uniquely correspond to all allowable error patterns on a one-to-one basis among the syndromes S having an m-bit length output from the syndrome calculation circuit 11.
The permissible error partial syndrome S (m _e ) consisting of part m)
Is input as an address, and information (1 bit error location increase) EL ⁽¹ ) indicating the position of any one bit of the error bits (e bits or less) on the allowable error pattern corresponding to S (m _e ) EL ^{(1 1)} is a 1-bit error location table having output data and is composed of a ROM.

Reference numeral 13 denotes a 1-bit error correction circuit, which inputs the received word Y and the 1-bit error location information EL ^(1)
The 1-bit error correction process corresponding to ⁽¹⁾ is applied to the received word Y to generate the successive correction word Z, which is output to the outside and fed back to the input of the syndrome calculation circuit 11.

Next, FIG. 2 is a diagram showing another structural example of the permissible error successive correction circuit according to the present invention. In the figure, reference numeral 21 denotes a syndrome register that temporarily stores and holds the syndrome S corresponding to the sequentially corrected word when the received word Y is sequentially corrected bit by bit, and outputs the syndrome S to the outside, which corresponds to the received word Y. Receive syndrome S _Y (input from outside) is set as the initial value.

Further, 22 is a 1-bit error location table similar to 12 in FIG. 1, and is the minimum m _e that can uniquely correspond to all allowable error patterns in the syndrome S obtained from the syndrome register 21 in a one-to-one correspondence. Bit (m _e <m)
Input the allowable error partial syndrome (m _e ) consisting of the part as the address. 23 receives the 1-bit error location information EL ⁽¹⁾ and the received word Y sequentially output from the 1-bit error location table 22 and executes error correction of the received word Y corresponding to EL ^(1). The permissible error correction circuit finally outputs the permissible error correction word C to the outside, and the 1-bit error correction circuit 13 in FIG. 1 can be used instead.

24 inputs the above EL ⁽¹⁾ , and EL ⁽¹⁾ indicates 1
1-bit error syndrome S corresponding to bit error
^The 1-bit error syndrome generation circuit generated in ⁽¹⁾ can be easily configured by a table using a ROM or a circuit that executes syndrome calculation.

Reference numeral 25 denotes a syndrome calculation circuit which inputs the received word Y, calculates the reception syndrome S _Y corresponding to Y, and supplies the syndrome to the syndrome register 21. Its function as a single unit is the same as that of 11 in FIG. is there.

26 inputs the 1-bit error syndrome S ⁽¹⁾ output from the 1-bit error syndrome generation circuit 24 and the syndrome S output from the syndrome register 21, and the exclusive OR S + S ⁽¹⁾ corresponding to both bits (+
Is an exclusive OR circuit for calculating the exclusive OR, and its output is fed back to the input of the syndrome register 21.

[Work]

The operation of the allowable error successive correction circuit according to the present invention based on the first or second configuration example shown in FIGS. 1 and 2 will be described.

First, the construction method of the permissible error partial syndrome S (m _e ) which is an input to the 1-bit error location tables 12 and 22 commonly used in FIGS. 1 and 2 will be described by a specific example.

Now, as a specific example, n = 15, m = 8, information bit length: k = n
Taking BCH code (15,7) which is an error correction block code with -m = 7 and the maximum number of correctable error bits: t = 2, 1-bit error correction (allowable error bit number e = 1), 2
Consider the case of decoding by rejecting more than one bit.

The BCH code generator polynomial G (x), the next two polynomials ^{Gα (x) = x 4 +} x + 1 ...... (1) Gβ (x) = x 4 + x 3 + x 2 + x + 1 ...... (2) factor Is a polynomial and is

G (x) = Gα (x ) · Gβ (x) = X 8 + X 7 + X 6 + X 4 +1 ...... (3) In this case, each bit of any code word C _{i (i} = 0~15)
Code polynomial with Contains G (x) as a factor.

Here, if arbitrary roots of G ₁ (x) and G ₂ (x) given on the Galois extension field GF (2 ⁴ ) of characteristic 2 and degree 4 are respectively denoted by α and β, the above C (x ), C (α) = C (β) = 0 (5), so the following matrix And the codeword vector (n-dimensional) C = (C ₁₄ C ₁₃ ...... C ₂ C ₁ C ₀ ) ^T (7) (T represents transposition), the following equation holds.

H · C = 0 (8) Therefore, H in the equation (6) functions as a check matrix.
The check matrix H in the notation of the equation (6) is the power value of the following four α, Respectively Is expressed by four four-dimensional unit vectors, and converted into the next check matrix of m rows × n columns.

Each column vector in the part surrounded by the solid line and the broken line on the right side of the equation (10) corresponds to the power of α and β in the same column on the right side of the equation (6).

Next, the received word vector (n-dimensional): Y is set as Y = (Y ₁₄ Y ₁₃ ...... Y ₂ Y ₁ Y ₀ ) ^T (11), and the syndrome vector (m-dimensional): S for S
Let S = (S ₇ S ₆ ...... S ₂ S ₁ S ₀ ) ^T (12), then S is calculated by the following equation.

S = H · Y (13) Therefore, when Y is equal to the codeword vector C, S is 0.
It becomes a vector.

On the other hand, when Y contains an error, if this error pattern is set as an n-dimensional vector E = (E ₁₄ E ₁₃ ...... E ₂ E ₁ E ₀ ) ^T (14), then Y = C + E ...... ( 15) (However, + is addition modulo 2 of elements, or exclusive OR), so from equations (8), (13), and (15), S = H · (C + E) = H ・ C + H ・ E = H ・ E …… (1
6) is obtained, and the syndrome vector S uniquely corresponds to the error pattern vector E.

Now, on the premise of the above-mentioned coding system, when the number of error bits is 1, the characteristic of the allowable error syndrome S obtained by the calculation of the equation (16) is examined. In this case, the vector of the error pattern E (14 Since one of the bits E _{14 to} E _{0 in} the equation is “1” (error) and the other is “0” (normal), the allowable error syndrome S corresponds to the position of this error bit. (10) is equal to one column vector of the check matrix.

On the other hand, the factor Gα (x) of the generator polynomial G (x) is a primitive polynomial, and its root α is a primitive element of GF (2 ⁴ ). That is, The minimum root of i other than 0 (that is, the order of α) is 2 ⁴
Since −1 = 15, α ⁰ , α ¹ , ... α ¹⁵ have a property that they are not equal even if any two of them are compared. This means that each 4-bit column vector of the submatrix in the upper 4 rows (part surrounded by the solid line) of the parity check matrix of equation (10) is unique, and the same vector does not exist. ing.

Therefore, when the number of error bits e = 1, the partial syndrome composed of 4 bits S ₇ , S ₆ , S ₅ , and S ₄ is defined as the allowable error partial syndrome S (m _e ), (m _e = 4). , Where S (m _e ) is a 1-bit error pattern E
1 to 1 (that is, each of the 1-bit error positions) is uniquely corresponded to one by one, and the rest of S (m _e ) is removed from S.
The partial syndrome S (m-m _e ) composed of m-m _e (= 4) bits of S ₃ , S ₂ , S ₁ , and S ₀ is a redundant part uniquely determined by S (m _e ).

On the other hand, the syndrome S when the number of error bits is 2 is
Clearly from equation (16), the sum of two examples of the check matrix of equation (10) corresponding to each 1-bit error position (however, addition of modulo 2 of elements, or exclusive OR) Therefore, it is no longer possible to uniquely correspond to all 2-bit error patterns on a one-to-one basis only with the partial syndrome S (m _e ), which makes it impossible to distinguish from the case where the number of error bits is 1. In this case, the partial syndrome S (m-
m _e ) is not a redundant part, error position determination using S (m−m _e ) is possible, and the syndrome S itself is different from any of the syndromes when the number of errors is 1. Becomes

The properties of the check matrix and the syndrome shown in the above specific examples are generally found also in the case of other block codes with the maximum number of correctable error bits: t ≧ 2, and are allowed by the present invention. The error successive correction circuit executes the permissible error correction by applying the above property.

The operation of the present invention based on the first and second configuration examples of FIGS. 1 and 2 will be described below.

First, in the configuration example of FIG. 1, the received word Y is set as the initial value of the successive correction word Z output from the 1-bit error correction circuit 13. On the other hand, the syndrome calculation circuit 11 causes the syndrome S corresponding to the successive correction word Z.
Is calculated according to the following equation S = H · Z (17) based on the equation (13). Of the syndromes S, the permissible error part syndrome S (m _e ) is input to the 1-bit error location table 12, and among the error bits on the permissible error pattern corresponding to the permissible error part syndrome S (m _e ), 1-bit error location information EL ⁽¹⁾ indicating any one-bit position is output and supplied to the 1-bit error correction circuit 13. 13 corrects and updates the relevant bit of the current output Z (= Y) according to the 1-bit error position information indicated by EL ⁽¹⁾ . That is, assuming that the 1-bit error pattern is E ⁽¹⁾ , the next update process Z + E ⁽¹⁾ → Z (+ is exclusive OR) ... (A) is performed.

As is apparent from the above operation, it is understood that the error is successively corrected bit by bit in the successive correction word Z output by 13 for each processing of the loop formed by 11, 12, and 13. Therefore, when the above loop processing is completed a maximum of e times, a maximum of e
Since the allowable error of the bit is corrected by the 1-bit error correction circuit 13, a patent error correction word appears at the output Z thereof.

When the error contained in the received word Y is not an allowable error (the number of error bits> e), the loop processing for the maximum number of times e is eventually invalid. However, in this case, the syndrome S output from the syndrome calculation circuit 11 does not have a “0” pattern, and therefore S can be used for the rejection test of the allowable error correction word on the outside.

Next, in the configuration example of FIG. 2, first, the reception syndrome S _Y corresponding to the reception word Y is calculated by the syndrome calculation circuit 25 and given to the syndrome register 21. The syndrome S, which is the output of the syndrome register 21, is set to S _Y as an initial value and output to the outside. The permissible error partial syndrome S (m _e ) of the syndrome S is 1
The bit error location table 22 is input to the S
Among the error bits on the allowable error pattern corresponding to (m _e ), the 1-bit error location information EL ⁽¹⁾ indicating the position of any one bit is from 22 to the allowable error correction circuit 23 and the 1-bit error syndrome generation circuit 24. Supplied to each.

By supplying the EL ⁽¹⁾ , the error correction of the one beat in the allowable error correction circuit 23 becomes possible and
The 1-bit error syndrome S corresponding to the relevant 1-bit error is generated by the bit-error syndrome generation circuit 24.
⁽¹⁾ is generated. The S ⁽¹⁾ and the syndrome S are combined by the exclusive OR circuit 26, and S + S ⁽¹⁾ is fed back to the syndrome register 21, whereby the next update process S + S ⁽¹⁾ → S ... (B) Are executed in the syndrome register 21. Here, the S ⁽¹⁾ and the 1-bit error pattern E
^{Since the} following equation S ⁽¹⁾ = HE ⁽¹⁾ (18) is established between equation (16) and equation (16), the update process of (B) is performed by equation (17), ( 1
From formula 8), H · Z + HE · E ⁽¹⁾ → H · Z (B ') This update process (B ') is equivalent to the update process (A) shown in the operation of the configuration example of FIG. 1, and the syndrome S shown in FIGS. 1 and 2 may exhibit the same operation. Recognize. As is clear from the above, in FIG.
For each loop processing formed by 21,22,24,26, the 1-bit error location information EL ⁽¹⁾ output by 22 is used to correct the error of the received word Y in the allowable error correction circuit 23 bit by bit. It will be possible.

Further, even when the error included in the received word is not the allowable error, it is also obvious that the syndrome S can be used for the rejection test of the allowable error correction word on the outside, as in the configuration example of FIG.

Next, in the allowable error successive correction circuit according to the present invention described above, the memory size of the table used (that is, the 1-bit error location table memory 22) and the number of processing steps will be examined.

First, the storage capacity of the table is, as is clear from the description in the above configuration, It will be later.

On the other hand, the number of processing steps is at most e times when evaluated by the number of times the table is accessed. Specific example of the above (n = 15, m
= 8, m _e = 4, e = 1), the values of the above two specifications are summarized in Table 1 together with the cases of the above-mentioned two conventional methods.

It can be seen from Table 1 that the allowable error successive correction circuit according to the present invention can significantly reduce the storage capacity as compared with the conventional method although the number of processing steps is small.

(Effect of the Invention) As described in detail above, according to the present invention, the increase in the number of steps of the permissible error correction processing is small, and
Since the storage capacity of the table used can be greatly reduced,
Easy to make IC and miniaturize. Also, other processing except the table is a simple software. Since it can be realized by air, it can further contribute to the economy of the circuit.

[Brief description of drawings]

FIG. 1 is a first configuration example diagram of a tolerable error successive correction circuit according to the present invention, FIG. 2 is a second configuration example diagram of a tolerable error successive correction circuit according to the present invention, and FIG. 3 is a conventional tolerable error correction circuit. It is a structural example figure. 11,25 ... Syndrome calculation circuit, 12,22 ... 1-bit error location table, 13 ... 1-bit error correction circuit, 23 ... Allowable error correction circuit, 21 ... Syndrome register, 24 ... 1-bit error syndrome Generation circuit, 26 ...
… Exclusive OR circuit.

Front page continuation (72) Inventor Yasuhiro Murayama 2-1-1 Shinmeidai, Hamura-cho, Nishitama-gun, Tokyo Kokusai Electric Co., Ltd. Hamura factory (56) Reference JP-A-58-191050 (JP, A)

Claims (2)

(57) [Claims] 1. A sequential correction word obtained in the process of sequentially correcting a received word of n (natural number) bits for each error bit is input, and a code length is n bits and a parity length is m (natural number, m <n).
A syndrome calculation circuit that calculates an m-bit length syndrome corresponding to the successive correction word by a calculation method that relies on the algebraic structure of a bit error correction block code and outputs the syndrome to the outside, and the syndrome can correct the syndrome. Of the smallest m _e (m _e <m) bits that can uniquely correspond on a one-to-one basis to all allowable error patterns that have errors less than the maximum allowable error bit number A 1-bit error location table that inputs the error partial syndrome as an address and outputs 1-bit error location information indicating the position of any one bit of the error bits on the allowable error pattern corresponding to the allowable error partial syndrome; , Inputting the received word and the 1-bit error location information, and inputting the received word according to the information On the other hand, the tolerable error sequence is generated by performing a 1-bit error correction process, and is output to the outside as a tolerable error correction word and is fed back to the input of the syndrome calculation circuit. Correction circuit. 2. A received word of n (natural number) bits is input, and the received word is received by a calculation method which depends on an algebraic structure of an error correction block code having a code length of n bits and a parity length of m (natural number, m <n) bits. A syndrome calculation circuit for calculating and outputting a reception syndrome of m-bit length corresponding to a word, the reception syndrome as an initial value, and the receiver having an error 1
The syndrome register that temporarily stores and holds the syndrome corresponding to the sequentially corrected word when sequentially corrected bit by bit, and the syndrome register that is output to the outside, and the largest error bit that can be corrected in the coding system among the syndromes that are output from the syndrome register Address the allowable error part syndrome consisting of the smallest m _e (m _e <m) bit parts that can uniquely correspond one-to-one to all allowable error patterns having errors less than the number of allowable error bits And a 1-bit error location table that outputs 1-bit error location information indicating the position of any one bit of the error bits on the allowable error pattern corresponding to the allowable error partial syndrome as output data, A word and the 1-bit error location information are input, and the reception information is input according to the information. A permissible error correction circuit that outputs an permissible error correction word to the outside by performing error correction processing on the signal word and finally correcting all permissible error bits, and inputs the 1-bit error location information, and the information indicates A 1-bit error syndrome generation circuit that generates and outputs a 1-bit error syndrome corresponding to a 1-bit error, the 1-bit error syndrome, and the syndrome output from the syndrome register are input, and the 2-input bit is input. A permissible error successive correction circuit configured by an exclusive OR circuit that calculates a corresponding exclusive OR and feeds back to the input of the syndrome register as an updated value of the syndrome corresponding to the successive correction word.