US7278085B1  Simple errorcorrection codes for data buffers  Google Patents
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 US7278085B1 US7278085B1 US10/608,320 US60832003A US7278085B1 US 7278085 B1 US7278085 B1 US 7278085B1 US 60832003 A US60832003 A US 60832003A US 7278085 B1 US7278085 B1 US 7278085B1
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 G—PHYSICS
 G11—INFORMATION STORAGE
 G11C—STATIC STORES
 G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
 G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
 G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F11/00—Error detection; Error correction; Monitoring
 G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
 G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
 G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
 G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

 G—PHYSICS
 G11—INFORMATION STORAGE
 G11C—STATIC STORES
 G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
 G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
 G11C2029/0411—Online error correction

 G—PHYSICS
 G11—INFORMATION STORAGE
 G11C—STATIC STORES
 G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
 G11C2207/10—Aspects relating to interfaces of memory device to external buses
 G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
Abstract
Description
This application claims priority from U.S. Provisional Patent Application No. 60/452,416, filed Mar. 6, 2003, which is incorporated herein by reference in its entirety for all purposes.
The invention relates to encoding and decoding techniques for error correction and detection.
In conventional data storage systems, data being transferred between a processor and a storage device (such as a hard disk) is buffered in memory. Typically, the buffer memory is implemented with semiconductor memory devices such as Dynamic Random Access Memory (DRAM) devices.
Semiconductor memory devices, in particular, DRAMs, are susceptible to errors known as “soft errors”. Soft errors are unexpected or unwanted changes in the value of a bit (or bits) somewhere in the memory. One bit may suddenly, randomly change state, or noise may get stored as if it were valid data. Soft errors are caused by external factors, such as terrestrial cosmic rays.
When soft errors go undetected in a data storage system, erroneous data may be written to disk, or good data read back can be corrupted before it is sent to the processor. In order to provide an acceptable level of reliability for data read from a memory array, therefore, error correcting codes (ECC) such as linear block codes have been employed to correct bit errors in the data stored in the memory. For example, Hamming codes have been used to provide singlebit error correction and doublebit error detection to preserve the data accuracy. As more than two errors cannot be properly detected by the Hamming code, often a Cyclic Redundancy Check (CRC) code is used to supplement the detection capability of the Hamming code. The CRC has no error correction capability, but can detect errors occurring in more than two bits at a time. Together, the Hamming check and CRC can correct single bit errors and detect multibit errors reliably.
Conventional linear block codes such as Hamming codes are efficient and easily implemented by using linear feedback shift registers as encoders. During decoding, however, the error locations are indicated by syndromes, which need to be mapped to the actual locations of the errors in the buffer memory. One common approach to this task is to use a large table, which maps the syndromes to the actual memory locations of the errors. The use of such a lookup table incurs additional complexity and cost.
This invention features a coding technique that produces a syndrome that directly points to the memory location of an erroneous data word so that no syndrome conversion is needed.
In one aspect of the invention, a method of decoding errors occurring in data stored in memory includes: (i) applying data to be stored in a buffer memory to a generator matrix to generate parity check bits; (ii) storing the parity check bits in the buffer memory following the data; (iii) reading the stored data and parity check bits; (iv) regenerating the parity check bits; and (v) producing from the stored and reregenerated parity check bits a syndrome of a form that is usable to directly identify a location of an erroneous bit of the data in the buffer memory.
In another aspect of the invention, an apparatus includes a controller coupled to a storage medium and a buffer memory coupled to the controller for storing data to be written to the storage medium and data read from the storage medium. The controller is operable to perform the following steps: (i) applying data to be stored in a buffer memory to a generator matrix to generate parity check bits; (ii) storing the parity check bits in the buffer memory following the data; (iii) reading the stored data and parity check bits; (iv) regenerating the parity check bits; and (v) producing from the stored and regenerated parity check bits a result that is usable to directly identify a location of an erroneous bit of the data in the buffer memory.
Other features and advantages of the invention will be apparent from the following detailed description, and from the claims.
Like reference numerals will be used to represent like elements.
Referring to
In the illustrated embodiment, the data storage system 14 includes a front end (FE) interface 20 that interfaces the controller 16 to the processor 12, a back end (BE) interface 21 that interfaces the controller 16 to the storage media 18 and a buffer memory 22, which serves as a staging area for data being transferred between the processor 12 and the storage media 18 via the two interfaces 20, 21. In one embodiment, the buffer memory 22 is implemented as Dynamic Random Access Memory (DRAM) which, as discussed above, may be particularly vulnerable to single and multibit error occurrences.
In one exemplary embodiment, the controller 16 is configured to support coding to ensure the integrity of the data that is stored in the buffer memory 22. In particular, the coding includes error correction coding (ECC). The ECC is in the form of a linear block code that, in one embodiment, is similar to a Hamming code, and in another embodiment, is similar to a BCH code, as will be discussed later. For additional error detection capability, and as shown, the controller 16 may support Cyclic Redundancy Check (CRC) coding as well.
Data to be written to the storage media 18 is provided to the FE interface 20, which provides the data to a CRC unit 24 and ECC unit 26 via bus 28. The CRC unit 24 and ECC unit 26 compute CRC checks and ECC checks, respectively, for the received data. The checks are appended to the data. The data and the checks are stored in the buffer memory 22. When the data is read from the buffer memory 22 for transfer to the disk unit 18, the checks are recomputed for error detection and correction, as will be described.
Similarly, when data is moved from the storage media 18 to the processor 12, the data is provided to the controller 16 by the storage media 18 via the BE interface 21. The data is again stored in the buffer memory 22 temporarily. As before, checks are computed and stored along with the data in the buffer memory, and then recomputed when the data is read from the buffer memory 22 for transfer to the processor 12 via the FE interface 20.
The exemplary data storage system 14 as thus described with reference to
As is well known in the art, Extended Hamming codes allow the correction of single bit errors and detection of two bit errors per each unit of data plus associated parity check, called a “code word”. This is accomplished by using more than one parity bit, each computed on different combinations of bits in the data. The number of parity check bits required is given by the Hamming rule and is a function of the number of bits of data transmitted. The Hamming rule is expressed by the following k+p+2≦2^{p }where k is the number of data bits and p is the number of parity check bits.
In one embodiment, as illustrated in and described with reference to
As with the conventional Hamming and Extended Hamming codes, the ECC code word of the illustrated embodiments is generated by multiplying the data bits by a generator matrix G using modulo2 arithmetic. For an (n,k) code having an nbit code word with kbits of data followed by “nk” parity check bits, the (n,k) code is described by a k×n generator matrix G and by an “nk” x n parity check matrix H. The resulting code word vector (c_{1}, c_{2}, c_{3}, . . . , c_{n}), includes the original data bits ‘d’ and the calculated parity bits ‘p’. Hamming weight is the number of nonzero bits in a binary ntuple. The Hamming distance is the number of bits in which two binary ntuples differ.
The generator matrix G used in constructing the ECC consists of an identity matrix I and a parity generation matrix P: G=[I_{k}P]. The P partition of G is responsible for the generation of the actual parity check bits. Each column in P represents one parity check bit calculation computed on a subset of data d. Validating the received code word r (in the illustrated embodiment, the received code word is the code word as read from the buffer memory 22) involves multiplying it by the parity check matrix to form a syndrome vector “s”. That is, where parity matrix H=[P^{T}I_{nk}], syndrome s=H*r^{T}. If all elements of s are zero, the code word was received correctly. Typically, if s contains nonzero elements, the bit in error can be corrected as long as the error involves only a single bit.
Still referring to
Referring to
The embodiment of the ECC unit 26 shown in
Referring to
Referring to
It can be seen from the figure that the minimum Hamming distance of the code is 2. As is known, the minimum distance of a Hamming code should be at least three in order to correct a single error.
The minimum distance of the code described by the generator matrix G_{2 }can be extended to three in a number of ways. Exemplary generator matrices of a minimum distance 3 code are shown in
Referring to
It is a simple matter to prove that G_{4 }is indeed a minimum distance 4 code. First, it can be seen that each row contains at least four ‘1’'s. Therefore, any combination of rows will have even weights. Bits 1 to 14 provide distinct lists of all 2^{14}−1 binary representations of integers 1 to 2^{14}−1. Therefore, the sum of any two rows of G_{4 }has at least a single one among bit 1 to bit 14. Together with parity check bit 0, bits 0 through 14 have a weight of at least two for any combination of two rows. Therefore, any combination of two rows has a minimum weight of 4—two from bit 15 to bit 2 ^{14}−1 and two from bit 0 to bit 15. For any linear combination of three or more rows of G_{4 }the parity check bit 15 guarantees that the minimum weight is 4.
The codes described by the generator matrices of
Referring to
It will be appreciated that the circuit elements used to produce P[15], that is, XOR 94 p and register 96 p, could be eliminated for an implementation of the code described by the generator matrices G′_{3 }(
In practice, multiple data bits are transferred in parallel over a parallel data path or bus, for example, a 32bit or 64bit data bus. Another exemplary implementation of the parity check bit generator 32, this time having a parallel bus of N bits and a buffer width of Nbits, usable to encode the distance 4 code (described by the generator matrix G_{4 }of
Referring to
Referring to
Still referring to
Referring to
Still referring to
As was the case with the single bit embodiment of
Referring to
Referring to
The syndrome 150 is interpreted according to TABLE 1 below.
The first case in the table represents the normal, “no error” condition. In the fourth and eighth cases (corresponding to a singlebit error), where at least one of bits S[14] and S[15] is a ‘1’ and the bits S[0] through S[13] are not all zeros, the syndrome 150 directly identifies the word location and bit location of a single error in syndrome address offset field 152 and bit location field 154, respectively. The ECC unit 26, having detected a singlebit error and determined the location in memory, performs the correction. Single bit errors in the check are also identified. In response to a parity check error, the processor 12 may send the ECC unit 26 through a correction cycle even though the data was not in error. Doublebit errors are flagged (via the syndrome code 156) but not corrected. These errors may occur in any two bits in the codeword read from memory (two errors in the data, two errors in the check, or one error in each). Errors in three or more bits are beyond the capabilities of the ECC unit 26 to detect.
To increase the distance of the ECC further, more redundant bits are needed in the generator matrix. Thus, in another embodiment that uses a code similar to a BCH code, as described hereinafter with reference to
As shown in
A Galois field of GF(2^{14}) may be chosen for the code. The operations are performed in this field but the error locations are ordered as 1, 2, 3, . . . , k, where k is the data length in bits. As usual, an irreducible polynomial of degree 14 p(x)=x^{14}+x^{13}+x^{12}+x^{9}+x^{8}+x+1 is selected to generate all of the field elements as x^{k }mod p(x) for k=0, 1, 2, . . . , 2^{14}−2.
A code of distance 5 can be expressed in the conventional Galois field GF(2^{14}) generated by p(x). All of the field elements of the conventional field can be expressed as a linear combination of the basis x^{0}, x^{1}, x^{2}, x^{3}, . . . , x^{13}. Because the encoding and the decoding of a BCH type of code involves many operations of raising an element in power, multiplications and finding the inverse of the field element, however, a different field representation more suitable for ease of implementation may be used. Instead of using x^{0}, x^{1}, x^{2}, . . . x^{13 }as the basis, the elements x^{1}, x^{2}, x^{4}, x^{8}, x^{16}, x^{32}, x^{64}, x^{128}, x^{256}, x^{512}, x^{1024}, x^{2048}, x^{4096}, x^{8192 }and x^{16384 }are selected as the new basis, which is called a “normal” basis. It is convenient to use a 14bit binary vector to represent the field elements, and the normal basis are:
x^{1}=<binary>00 0000 0000 0001=<hex>0001
x^{2}=<binary>00 0000 0000 0010=<hex>0002
x^{4}=<binary>00 0000 0000 0100=<hex>0004
x^{8}=<binary>00 0000 0000 1000=<hex>0008
x^{16}=<binary>00 0000 0001 0000=<hex>0010
x^{32}=<binary>00 0000 0010 0000=<hex>0020
x^{64}=<binary>00 0000 0100 0000=<hex>0040
x^{128}=<binary>00 0000 1000 0000=<hex>0080
x^{256}=<binary>00 0001 0000 0000=<hex>0100
x^{512}=<binary>00 0010 0000 0000=<hex>0200
x^{1024}=<binary>00 0100 0000 0000=<hex>0400
x^{2048}=<binary>01 1000 0000 0000=<hex>0800
x^{4096}=<binary>10 0000 0000 0000=<hex>1000
x^{8192}=<binary>10 0000 0000 0000=<hex>2000
If the field elements with normal basis representation are denoted β^{k }for k=0, 1, 2, 3, . . . , 2^{14}−2, then the first few field elements of β^{k }are given by:
It can be seen that β^{2}*^{k }can be obtained from β^{k }by cyclic rotation to the left by one bit. Therefore, all β^{k}*^{q }can be obtained from β^{k }by cyclic rotation of β^{k }to the left by s bit if q=2^{s}.
Still referring to
The singleerrorcorrecting algorithm for the code described by generator matrix 160 is the same as the decoding procedure described above with reference to
A doubleerrorcorrection decoding algorithm for the code described by generator matrix 160 will now be described. The decoding algorithm requires four or more consecutive syndromes S_{j}, S_{j+1}, S_{j+2 }and S_{j+3 }to generate the error locator polynomial σ(x). The syndrome S_{0 }for a doubleerror is equal to 0, and the syndromes S_{1}, S_{2}=(S_{1})^{2}, S_{4}=(S_{1})^{4 }and S_{5 }are readily available from the parity check bits. Syndrome S_{3 }is not available, however. The consecutive syndromes are denoted as S_{0}, S_{1}, S_{2}, Z, S_{4}, S_{5 }and Z^{2}, where S_{6}=(S_{3})^{2}=Z^{2}. The parity bit on S_{1 }is denoted as P_{1}, the parity bit on S_{5 }is denoted as P_{5}, and the parity on S_{0}, P_{1 }and P_{5 }is denoted as Pa.
First, for a single error correction, an error locator polynomial σ(x)=σ_{1}x+1, where σ_{1}=S_{1}, is assumed. If S^{5}=(S_{1})^{5}, the correction is correct. If the single correction fails, then a twoerror correction should be attempted assuming the error locator polynomial to be σ(x)=σ_{2}x^{2}+σ_{1}x+β^{0}.
Using the first three consecutive syndromes gives σ_{2}S_{0}+σ_{1}S_{1}+β^{0}S_{2}=0. If one substitutes S_{0}=0 and S_{2}=S_{1} ^{2}, then σ_{1}=S_{1}. Using the next three consecutive syndromes starting with S_{1 }gives σ_{2}S_{1}+σ_{1}S_{2}+β^{0}Z=0. Substituting θ_{1}=S_{1 }in the equation gives σ_{2}S_{1}+θ_{1}(S_{1})^{2}+Z=0. Using the next three consecutive syndromes starting at S_{4 }gives σ_{2}S_{4}+σ_{1}S_{5}+β^{0}Z^{2}=0. By substituting σ_{1}=S_{1 }and S_{4}=(S_{1})^{4}, the equation becomes σ_{2}(S_{1})^{4}+S_{1}*S_{5}+Z^{2}=0. Therefore, the equations to solve are as follows:
σ_{2} S _{1}+(S _{1})^{2} +Z=0 Eq. 1
σ_{2}(S _{1})^{4} +S _{1} *S _{5} +Z ^{2}=0 Eq. 2
The first equation (Eq. 1) is squared and then added to the second equation (Eq. 2) to form (σ_{2})^{2}(S_{1})^{2}+σ_{2}(S_{1})^{4}+(S_{1})^{4}+S_{1}*S_{5}=0. The resulting equation is a quadratic equation for the unknown σ_{2}, which can be solved with known techniques. Note that there are two solutions to σ_{2}, but only one of them with yield the correct results.
An alternative approach is to solve Z first, by multiplying Eq. 1 by (S_{1})^{3 }and then adding it to Eq. 2, to give (S_{1})^{5}+S_{1}*S^{5}+(S_{1})^{3}*Z+Z^{2}=0. The resulting equation is a quadratic equation in Z, which can be solved for Z=S_{3}. As in the case of σ_{2}, there are two solutions for Z, but only one correct solution. Once S_{3 }is known, a conventional BCH decoding algorithm can be used to find the error locator polynomial σ(x).
When the number of errors in the data is known from the solved σ(x), the total number of errors in the data part and in the parity check part should add up to a number no greater than 2.
Conditions that indicate the number of errors in the check bits (excluding the error in Pa) are provided in TABLE 2 below.
In an alternative implementation, and referring to
The inverse of a Galois field element is needed in the above decoding algorithm. The operations for the inverse computation can be performed in the following manner. Given a 14bit Galois field element A=(a_{2}, a_{1}), where a_{2 }is the upper 7 bits of A and a_{1 }is the lower 7 bits of A, a second 14bit Galois field element B is formed by swapping the upper 7 bits with the lower 7 bits in A so that B=(a_{1}, a_{2}). It is possible to form C=A*B and use a tablelookup to find the inverse of C, namely, C^{−1}. Once C^{−1 }has be determined, the inverse of A, A^{−1}, can be determined from A^{−1}=C^{−1}*B. The table used in the tablelookup requires only 128 entries.
To illustrate the encoding/decoding method of the double error correcting code, an example using a Galois field of GF(2^{3}) is provided as follows. The example assumes the Galois field is generated by the irreducible polynomial p(x)=x^{3}+x^{2}+1, with the field elements {0=(000), α^{0}=(001), α^{1}=(010), α^{2}=(100), α^{3}=(101), α^{4}=(111), α^{5}=(011), α^{6}=(110)}. This field is represented by the conventional representation. That is, the basis includes three elements: α^{0}=(001); α^{1}=(010); and α^{2}=(100). To use normal basis representation, the basis includes the elements α^{1}=(010), α^{2}=(100) and α^{4}=(111).
All of the elements in normal basis representations can be obtained as follows. The method uses β^{j}=[xyz] to represent the normal basis representation, where [xyz] is a binary number. The element β^{j}=[xyz] is defined as follows:
β^{j} =[xyz]=x*α ^{4} +y*α ^{2} +z*α ^{1} =x*β ^{4} +y*β ^{2} +z*β ^{1}.
With this definition and by setting y=z=0 and x=1, it is possible to obtain β^{4}=[100]=α^{4}; and, similarly, β^{2}=[010]=α^{2}, and β^{1}=[001]=α^{1}. The normal basis representation of all of the elements can be readily obtained, and are given by the following:
[000]=0; [001]=β^{1}=α^{1}; [010]=β^{2}=α^{2}; [011]=β^{2}+β^{1}=α^{2}+α^{1}=(100)+(010)=(110)=α^{6}=β^{6}; [100]=β^{4}=α^{4}; [101]=β^{4}+β^{1}=α^{4}+α^{1}=(111)+(010)=(101)=α^{3}=β^{3}; [110]=β^{4}+β^{2}=α^{4}+α^{2}=(111)+(100)=(011)=α^{5}=β^{5}; and [111]=β^{4}+β^{2}+β^{1}=α^{4}+α^{2}+α^{1}=(111)+(100)+(010)=(001)=α^{0}=β^{0}. The relation and elements are summarized below:
α^{0}=(001)=β^{0}=[111]
α^{1}=(010)=β^{1}=[001]
α^{2}=(100)=β^{2}=[010]
α^{3}=(101)=β^{3}=[101]
α^{4}=(111)=β^{4}=[100]
α^{5}=(011)=β^{5}=[110]
α^{6}=(110)=β^{6}=[011]
From this point onward, only the normal basis representation β^{j }is used.
The matrix G_{4 }(from
The matrix G_{6 }(from
Letting the information bits be [0 0 1 0 0 1 1], the code word is given by [0 0 1 0 0 1 1]*G_{6}=[0 0 1 0 0 1 1 1 1 1 0 0 0 1 0 1]=c. Assuming an error is [0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0]=e, the read back corrupted code word is [0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 1]. The data bit of the read back corrupted code word is used to compute the following check bits:
[0 0 1 1 0 0 1]*G_{6}=[1 000 0 100 1]. ExclusiveORing the above with the check bits of the read back corrupted codeword gives:
[1 1 1 0 0 0 1 0 1]+[1 000 0 100 1]=[0 110 0 110 0]=[1 β^{5 }0 β^{5 }0]. Therefore, S_{1}=β^{5 }and S_{5}=β^{5}.
Assuming the two errors are β^{i }and β^{j}, it is possible to form the following two equations:
β^{i}+β^{j} =S _{1}=β^{5}; and Eq. 3
β^{5i}+β^{5j} =S _{5}=β^{5}. Eq. 4
Raising Eq. 3 to the fifth power gives the following equation:
β^{5i}+β^{4i}*β^{j}++β^{i}*β^{4j}+β^{5j}=β^{25}=β^{4}. Eq. 5
Adding Eq. 4 to Eq. 5 gives
β^{4i}*β^{j}++β^{i}*β^{4j}=β^{i}*β^{j}*(β^{3i}+β^{3j})=β^{5}+β^{4}=β^{2}, or
β^{i}*β^{j}*(β^{3i}+β^{3j})=β^{2}. Eq. 6
In Eq. 6, both β^{i}*β^{j }and (β^{3i}+β^{3j}) are unknown, and the goal is to find β^{i}*β^{j}. Raising S_{1 }to cubic power gives:
β^{3i}+β^{2i}*β^{j}+β^{i}*β^{i}*β^{2j}+β^{3j} =S _{1} ^{3}=β^{1}, or
(β^{3i}+β^{3j})+β^{i}*β^{j}*(β^{i}+β^{j})=β^{1}, or
(β^{3i}+β^{3j})+β^{i}*β^{j} *S _{1}=β^{1}, or
(β^{3i}+β^{3j})+β^{i}*β^{j}*β^{5}=β^{1}. Eq. 7
Substituting Eq. 7 into Eq. 6 provides the following:
β^{i}*β^{j}*(β^{i}*β^{j}*β^{5}+β^{1})=β^{2}, or
(β^{i}*β^{j})^{2}*β^{5}+(β^{i}*β^{j})*β^{1}=β^{2}. Eq. 8
If every term is divided by β^{5}, then (β^{i}*β^{j})^{2}+(β^{i}*β^{j})*β^{3}+β^{4}=0.
By letting (β^{i}*β^{j})=β^{3}*W, β^{6}*W^{2}+β^{6}*W+β^{4}=0, which leads to the following:
W ^{2} +W+β ^{5}=0 Eq. 9
To solve a quadratic equation in GF(2^{m}), it is necessary to prestore the solutions β^{1}+(β^{1})^{2}=β^{6}=[011] and β^{6}+(β^{6})^{2}=β^{3}=[101]. The requirement in this example is that the constant term has to be of even weight. In Eq. 9, the constant term is β^{5}=[110], which can be decomposed into [110]=[011]+[101]. Consequently, one solution of Eq. 9 is W=β^{1}+β^{6}=β^{2}. The other solution for W is β^{2}+β^{0}=β^{3}. Therefore, the two solutions for (β^{i}*β^{j})=β^{3}*W are β^{5 }and β^{6}.
The method first tries (β^{i}*β^{j})=β^{5 }and (β^{i}+β^{j})=S_{1}=β^{5 }in finding the solutions to x^{2}+β^{5}*x+β^{5}=0. Using the same procedure as before, and letting x=β^{5}*y, gives (β^{5}*y)^{2}+(β^{5})^{2}*y+β^{5}=0. Dividing every term by (β^{5})^{2 }gives y^{2}+y+β^{2}=0. Since β^{2}=[010] has an odd weight, y^{2}+y+β^{2}=0 has no solutions.
Next the method solves the quadratic equation for (β^{i}*β^{j})=β^{6}, which gives the following equation:
x ^{2}+β^{5} *x+β ^{6}=0. Eq. 10
Using x=β^{5}*y results in (β^{5}*y)^{2}+(β^{5})^{2}*y+β^{6}=0. Dividing every term by (β^{5})^{2 }then gives:
y ^{2} +y+β ^{3}=0. Eq. 11
From the foregoing it can be seen that one solution for Eq. 11 is y=β^{6 }and the other solution for Eq. 11 is y=β^{6}+β^{0}=β^{4}. Thus, the solutions for x^{2}+β^{5}*x+β^{6}=0 (Eq. 10) are x=β^{4 }and x=β^{2}. This result can be verified by determining that β^{4}+β^{2}=β^{5}=S_{1}.
The first error location is given by β^{4}=[100]. The actual error occurs at location 100−1=011 or bit 3, assuming the rightmost data bit is bit 0. The second error location is given by β^{2}=[010]. Again, if the rightmost data bit is bit 0, the actual error occurs at location 010−1=001 or bit 1.
For the case of G′6, the error locations are obtained from β^{k }and β^{−k}. Using β^{k }and β^{−k }may simplify the computation. The generator matrix G′_{6 }for the running example is in the form of the following:
Assuming the information bits to be [0 0 1 0 0 1 1], the code word is given by [0 0 1 0 0 1 1]*G_{6}′=[0 0 1 0 0 1 1 1 1 1 0 0 0 0 1 1]=c′. Assuming the error is [0 0 1 0 1 0 0 0 0 0 0 0 0 0 0]=e′=e, the read back corrupted code word is [0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1]. Using the data bit of the read back corrupted code word to compute the check bits thus gives
[0 0 1 1 0 0 1]*G_{6}′=[1 000 0 010 1]. ExclusiveORing the above with the check bit of the read back corrupted codeword gives
[1 1 1 0 0 0 0 1 1]+[1 000 0 010 1]=[0 110 0 011 0]=[1 β^{5 }0 β^{6 }0]. Therefore, S_{1}=β^{5 }and S_{−1}=β^{6}.
Assuming the two errors are β^{i }and β^{j}, it is possible to form the following two equations:
β^{i}+β^{j} =S _{1}=β^{5}; and Eq. 12
β^{−i}+β^{−j} =S _{−1}=β^{6}. Eq. 13
Since it is known that S_{0}=0 because there are two errors, then (β^{i}*β^{j})*S_{−1}+(β^{i}+β^{j})*S_{0}+β^{0}*S_{1}=0, or (β^{i}*β^{j})*β^{6}+β^{5}=0, and thus (β^{i}*β^{j})=β^{5}/β^{6}=β^{6}. The equation to solve is the following:
x ^{2}+(β^{i}+β^{j})*x+(β^{i}*β^{j})=0, or x ^{2}+β^{5} *x+β ^{6}=0. Eq. 14
Since Eq. 14 is the same as Eq. 10, it is understood to be the correct equation.
It is to be understood that while the invention has been described in conjunction with the detailed description thereof, the foregoing description is intended to illustrate and not limit the scope of the invention, which is defined by the scope of the appended claims. Other embodiments are within the scope of the following claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.
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US20060200724A1 (en) *  20050301  20060907  Stankovic Vladimir M  Multisource data encoding, transmission and decoding using SlepianWolf codes based on channel code partitioning 
US20060200733A1 (en) *  20050301  20060907  Stankovic Vladimir M  Multisource data encoding, transmission and decoding using SlepianWolf codes based on channel code partitioning 
US20070157064A1 (en) *  20051227  20070705  D.S.P. Group Ltd.  Systems and methods for error corrections 
US20070198890A1 (en) *  20051113  20070823  International Business Machines Corporation  Method for creating an error correction coding scheme 
US20080104477A1 (en) *  20030319  20080501  Stmicroelectronics S.R.I.  Method for performing error corrections of digital information codified as a symbol sequence 
US20080133684A1 (en) *  19990929  20080605  Tetsuro Motoyama  Method and system for remote diagnostic, control and information collection based on various communication modes for sending messages to users 
US20080148129A1 (en) *  20061214  20080619  Regents Of The University Of Minnesota  Error detection and correction using error pattern correcting codes 
US20080320364A1 (en) *  20070620  20081225  Texas Instruments Incorporated  Adding known data to crc processing without increased processing time 
US20090089646A1 (en) *  20071002  20090402  Masanobu Hirose  Semiconductor storage device 
US20100146369A1 (en) *  20050527  20100610  International Business Machines Corporation  Soft Error Protection in Individual Memory Devices 
US20100293443A1 (en) *  20061031  20101118  Josef Newald  Method for transmitting a data transfer block and method and system for transferring a data transfer block 
US20100306632A1 (en) *  20090527  20101202  International Business Machines Corporation  Error detection using parity compensation in binary coded decimal and densely packed decimal conversions 
US20110047439A1 (en) *  20090820  20110224  Broadcom Corporation  Soft error rate protection for memories 
US20110099451A1 (en) *  20091022  20110428  Arm Limited  Error control coding for single error correction and double error detection 
US20110246768A1 (en) *  20100406  20111006  King Saud University  Systems and methods improving cryptosystems with biometrics 
US20110289381A1 (en) *  20100524  20111124  Oracle International Corporation  Memory system that provides guaranteed componentfailure correction with doubleerror correction 
US8069392B1 (en) *  20071016  20111129  Integrated Device Technology, Inc.  Error correction code system and method 
US20120233521A1 (en) *  20110308  20120913  Kwok Zion S  Apparatus, system, and method for decoding linear block codes in a memory controller 
US20130139028A1 (en) *  20111128  20130530  Texas Instruments Incorporated  Extended Bidirectional Hamming Code for DoubleError Correction and TripleError Detection 
US20150098263A1 (en) *  20131003  20150409  Fujitsu Semiconductor Limited  Ferroelectric memory device 
US9037564B2 (en)  20110429  20150519  Stephen Lesavich  Method and system for electronic content storage and retrieval with galois fields on cloud computing networks 
US9137250B2 (en)  20110429  20150915  Stephen Lesavich  Method and system for electronic content storage and retrieval using galois fields and information entropy on cloud computing networks 
US20150363267A1 (en) *  20140617  20151217  Arm Limited  Error detection in stored data values 
US9361479B2 (en)  20110429  20160607  Stephen Lesavich  Method and system for electronic content storage and retrieval using Galois fields and geometric shapes on cloud computing networks 
US9430443B1 (en) *  20150508  20160830  Norwegian University Of Science And Technology  Systematic coding technique 
US9529671B2 (en)  20140617  20161227  Arm Limited  Error detection in stored data values 
US9569771B2 (en)  20110429  20170214  Stephen Lesavich  Method and system for storage and retrieval of blockchain blocks using galois fields 
US9569308B1 (en) *  20130715  20170214  Rambus Inc.  Reducedoverhead error detection and correction 
US9891976B2 (en)  20150226  20180213  Arm Limited  Error detection circuitry for use with memory 
US10211853B2 (en) *  20150817  20190219  Lattice Semiconductor Corporation  Method of transmitting and receiving audio signals and apparatus thereof 
US10552260B2 (en) *  20170612  20200204  Cirrus Logic, Inc.  Detection of double bit errors and correction of single bit errors in a multiword array 
Citations (9)
Publication number  Priority date  Publication date  Assignee  Title 

US4862462A (en) *  19870212  19890829  Honeywell Bull Italia S.P.A.  Memory systems and related error detection and correction apparatus 
US5452429A (en) *  19931117  19950919  International Business Machines Corporation  Error correction code on addon cards for writing portions of data words 
US5490155A (en) *  19921002  19960206  Compaq Computer Corp.  Error correction system for n bits using error correcting code designed for fewer than n bits 
US5537425A (en) *  19920929  19960716  International Business Machines Corporation  Paritybased error detection in a memory controller 
US5555250A (en) *  19941014  19960910  Compaq Computer Corporation  Data error detection and correction system 
US5612965A (en) *  19940426  19970318  Unisys Corporation  Multiple memory bit/chip failure detection 
US5666371A (en) *  19950224  19970909  Unisys Corporation  Method and apparatus for detecting errors in a system that employs multibit wide memory elements 
US5784393A (en) *  19950301  19980721  Unisys Corporation  Method and apparatus for providing fault detection to a bus within a computer system 
US6799291B1 (en) *  20001120  20040928  International Business Machines Corporation  Method and system for detecting a hard failure in a memory array 

2003
 20030627 US US10/608,320 patent/US7278085B1/en not_active Expired  Fee Related
Patent Citations (10)
Publication number  Priority date  Publication date  Assignee  Title 

US4862462A (en) *  19870212  19890829  Honeywell Bull Italia S.P.A.  Memory systems and related error detection and correction apparatus 
US5537425A (en) *  19920929  19960716  International Business Machines Corporation  Paritybased error detection in a memory controller 
US5663969A (en) *  19920929  19970902  International Business Machines Corporation  Paritybased error detection in a memory controller 
US5490155A (en) *  19921002  19960206  Compaq Computer Corp.  Error correction system for n bits using error correcting code designed for fewer than n bits 
US5452429A (en) *  19931117  19950919  International Business Machines Corporation  Error correction code on addon cards for writing portions of data words 
US5612965A (en) *  19940426  19970318  Unisys Corporation  Multiple memory bit/chip failure detection 
US5555250A (en) *  19941014  19960910  Compaq Computer Corporation  Data error detection and correction system 
US5666371A (en) *  19950224  19970909  Unisys Corporation  Method and apparatus for detecting errors in a system that employs multibit wide memory elements 
US5784393A (en) *  19950301  19980721  Unisys Corporation  Method and apparatus for providing fault detection to a bus within a computer system 
US6799291B1 (en) *  20001120  20040928  International Business Machines Corporation  Method and system for detecting a hard failure in a memory array 
Cited By (56)
Publication number  Priority date  Publication date  Assignee  Title 

US20080133684A1 (en) *  19990929  20080605  Tetsuro Motoyama  Method and system for remote diagnostic, control and information collection based on various communication modes for sending messages to users 
US20080104477A1 (en) *  20030319  20080501  Stmicroelectronics S.R.I.  Method for performing error corrections of digital information codified as a symbol sequence 
US10630317B2 (en)  20030319  20200421  Micron Technology, Inc.  Method for performing error corrections of digital information codified as a symbol sequence 
US8966335B2 (en) *  20030319  20150224  Micron Technology, Inc.  Method for performing error corrections of digital information codified as a symbol sequence 
US7779326B2 (en) *  20050301  20100817  The Texas A&M University System  Multisource data encoding, transmission and decoding using SlepianWolf codes based on channel code partitioning 
US7653867B2 (en) *  20050301  20100126  The Texas A&M University System  Multisource data encoding, transmission and decoding using SlepianWolf codes based on channel code partitioning 
US20110029846A1 (en) *  20050301  20110203  The Texas A&M University System  Multisource data encoding, transmission and decoding using slepianwolf codes based on channel code partitioning 
US20060200724A1 (en) *  20050301  20060907  Stankovic Vladimir M  Multisource data encoding, transmission and decoding using SlepianWolf codes based on channel code partitioning 
US8065592B2 (en)  20050301  20111122  The Texas A&M University System  Multisource data encoding, transmission and decoding using slepianwolf codes based on channel code partitioning 
US20060200733A1 (en) *  20050301  20060907  Stankovic Vladimir M  Multisource data encoding, transmission and decoding using SlepianWolf codes based on channel code partitioning 
US8949685B2 (en) *  20050527  20150203  International Business Machines Corporation  Soft error protection in individual memory devices 
US20100146369A1 (en) *  20050527  20100610  International Business Machines Corporation  Soft Error Protection in Individual Memory Devices 
US20070198890A1 (en) *  20051113  20070823  International Business Machines Corporation  Method for creating an error correction coding scheme 
US20080244353A1 (en) *  20051113  20081002  International Business Machines Corporation  Method for creating an error correction coding scheme 
US7797611B2 (en) *  20051114  20100914  International Business Machines Corporation  Creating an error correction coding scheme and reducing data loss 
US8321762B2 (en)  20051114  20121127  International Business Machines Corporation  Method for creating an error correction coding scheme 
US7562283B2 (en) *  20051227  20090714  D.S.P. Group Ltd.  Systems and methods for error correction using binary coded hexidecimal or hamming decoding 
US20070157064A1 (en) *  20051227  20070705  D.S.P. Group Ltd.  Systems and methods for error corrections 
US20100293443A1 (en) *  20061031  20101118  Josef Newald  Method for transmitting a data transfer block and method and system for transferring a data transfer block 
US8413017B2 (en) *  20061031  20130402  Robert Bosch Gmbh  Method for transmitting a data transfer block and method and system for transferring a data transfer block 
US8108759B2 (en) *  20061214  20120131  Regents Of The University Of Minnesota  Error detection and correction using error pattern correcting codes 
US20080148129A1 (en) *  20061214  20080619  Regents Of The University Of Minnesota  Error detection and correction using error pattern correcting codes 
US20080320364A1 (en) *  20070620  20081225  Texas Instruments Incorporated  Adding known data to crc processing without increased processing time 
US8127211B2 (en) *  20070620  20120228  Texas Instruments Incorporated  Adding known data to CRC processing without increased processing time 
US20090089646A1 (en) *  20071002  20090402  Masanobu Hirose  Semiconductor storage device 
US8151173B2 (en) *  20071002  20120403  Panasonic Corporation  Semiconductor storage device comprising memory array including normal array and parity array 
US8069392B1 (en) *  20071016  20111129  Integrated Device Technology, Inc.  Error correction code system and method 
US20100306632A1 (en) *  20090527  20101202  International Business Machines Corporation  Error detection using parity compensation in binary coded decimal and densely packed decimal conversions 
US8286061B2 (en) *  20090527  20121009  International Business Machines Corporation  Error detection using parity compensation in binary coded decimal and densely packed decimal conversions 
US8327249B2 (en) *  20090820  20121204  Broadcom Corporation  Soft error rate protection for memories 
US20110047439A1 (en) *  20090820  20110224  Broadcom Corporation  Soft error rate protection for memories 
US20110099451A1 (en) *  20091022  20110428  Arm Limited  Error control coding for single error correction and double error detection 
US8381083B2 (en) *  20091022  20130219  Arm Limited  Error control coding for single error correction and double error detection 
US9825761B2 (en) *  20100406  20171121  King Saud University  Systems and methods improving cryptosystems with biometrics 
US20110246768A1 (en) *  20100406  20111006  King Saud University  Systems and methods improving cryptosystems with biometrics 
US8335976B2 (en) *  20100524  20121218  Oracle America, Inc.  Memory system that provides guaranteed componentfailure correction with doubleerror correction 
US20110289381A1 (en) *  20100524  20111124  Oracle International Corporation  Memory system that provides guaranteed componentfailure correction with doubleerror correction 
US20120233521A1 (en) *  20110308  20120913  Kwok Zion S  Apparatus, system, and method for decoding linear block codes in a memory controller 
US8612834B2 (en) *  20110308  20131217  Intel Corporation  Apparatus, system, and method for decoding linear block codes in a memory controller 
US9569771B2 (en)  20110429  20170214  Stephen Lesavich  Method and system for storage and retrieval of blockchain blocks using galois fields 
US9037564B2 (en)  20110429  20150519  Stephen Lesavich  Method and system for electronic content storage and retrieval with galois fields on cloud computing networks 
US9361479B2 (en)  20110429  20160607  Stephen Lesavich  Method and system for electronic content storage and retrieval using Galois fields and geometric shapes on cloud computing networks 
US9137250B2 (en)  20110429  20150915  Stephen Lesavich  Method and system for electronic content storage and retrieval using galois fields and information entropy on cloud computing networks 
US20130139028A1 (en) *  20111128  20130530  Texas Instruments Incorporated  Extended Bidirectional Hamming Code for DoubleError Correction and TripleError Detection 
US8694872B2 (en) *  20111128  20140408  Texas Instruments Incorporated  Extended bidirectional hamming code for doubleerror correction and tripleerror detection 
US9785500B1 (en)  20130715  20171010  Rambus Inc.  Reducedoverhead error detection and correction 
US9569308B1 (en) *  20130715  20170214  Rambus Inc.  Reducedoverhead error detection and correction 
US20150098263A1 (en) *  20131003  20150409  Fujitsu Semiconductor Limited  Ferroelectric memory device 
US9190136B2 (en) *  20131003  20151117  Fujitsu Semiconductor Limited  Ferroelectric memory device 
US9529671B2 (en)  20140617  20161227  Arm Limited  Error detection in stored data values 
US9760438B2 (en) *  20140617  20170912  Arm Limited  Error detection in stored data values 
US20150363267A1 (en) *  20140617  20151217  Arm Limited  Error detection in stored data values 
US9891976B2 (en)  20150226  20180213  Arm Limited  Error detection circuitry for use with memory 
US9430443B1 (en) *  20150508  20160830  Norwegian University Of Science And Technology  Systematic coding technique 
US10211853B2 (en) *  20150817  20190219  Lattice Semiconductor Corporation  Method of transmitting and receiving audio signals and apparatus thereof 
US10552260B2 (en) *  20170612  20200204  Cirrus Logic, Inc.  Detection of double bit errors and correction of single bit errors in a multiword array 
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