JPS62137924A - Error position decision circuit of reed solomon coding and decoding system - Google Patents

Abstract

PURPOSE:To obtain an error position decision circuit capable of 3-symbol correction by using a shift register and a ROM so as to obtain each term of an error location polynomial while substituting a power to variables of the said polynomial in the ascending/descending order and obtaining the error location from the combined value. CONSTITUTION:Shift registers 1-4 are preset as shown in figure and shifted by a clock. The register 1 outputs '1' by the first clock, outputs alpha<3> by the next clock and then alpha<6>... by the suceeding clocks. It is equivalent to obtain (alpha<0>)<3>, (alpha<1>)<3>, (alpha<2>)<3>... and equivalent to substitute alpha<0>, alpha<1>, alpha<2>... to the term X<3> of the error location polynomial. As to the register 2, it is equivalent to sigma1(alpha<0>)<2>, sigma1(sigma<1>)<2>, sigma1(sigma<2>)<2>... and equivalent to the substitution to the term of sigma1X<2>. This is applied similarly as to the registers 3, 4, and the combination of each output is equivalent to the substitution of symbols in the ascending order from alpha<0> to the variable of the error location polynomial (X). Thus, zero output and the measurement of the clock number to be 0 decide what order number of symbol in the code block has an error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error position determination circuit in a decoding system for error-correctable Reed-Solomon codes used in digital audio equipment, and particularly for 3-symbol correctable codes.

[Conventional technology]

In digital audio equipment, as a countermeasure against random errors, information is encoded into codes that can be corrected.

For example, in digital audio disc players, CI (
C2(28,24) code and C2(28,24) code have been put into practical use as Reed-Solomon codes. Here, the first parenthesis is
The term is the number of symbols in the code block length, and the second term is the number of information symbols. The minimum distance of the C1 and C2 codes is 5 symbols, and the syndrome correction capability is capable of correcting 2 symbols at maximum. By the way, in digital audio tapes that are expected to be put into practical use in the future, codes with even longer distances and higher correction capabilities will be used.

[Problem that the invention seeks to solve]

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide an error position determination circuit as part of a Reed-Solomon code decoding system for a signal capable of correcting 3-symbol errors.

Decoding a Reed-Solomon code requires several steps, starting from calculating syndromes to performing correction operations. After the coefficients of the error locator polynomial are determined, the locator polynomial must be used to determine which symbol in the code block has an error.

[Means for solving problems]

The error locator polynomial σ(X) is usually expressed by the following equation.

Here α゛1　αj, α1 is an error symbol.

σ(X)=(1-α゛)(1-α')(1-α') (
1) -1+σ f
It is conceivable to find the i1 formula. However, factorization is complicated and almost impossible. Therefore, the error position is determined using the following algorithm Che 7.

When executing the algorithm of Che. 7, the following reciprocal polynomial is used instead of (2) form 2.

σ(X)=X″+σlX2+σ2X+σ, (3) α is the primitive light of the primitive polynomial, and each symbol is, for example, C
In a code with a block length of 3G, such as the I (36,30) code, α' (=1), α1 . It is expressed as a power of α, such as α2−..α35. Since α'', α4, and α6 are error symbols, sequentially input α0°α1− into σ(X), and when it becomes zero, the exponent of α determines which symbol in the code block is incorrect. I understand.The order of symbol insertion can be in ascending order like α0.α1.-・ or αM-
1. It may be in descending order, such as αM-2, - (M number of Nishinpol).

In the case of ascending order, the circuit of the present invention provides four shift registers driven by a common clock, and the first shift register has a constant that presets α' (=1) and then multiplies its output by α3. The second shift register is a ROM that has a constant that multiplies the output by α2 after presetting C1.
The third shift register has a shift circuit that returns to the input side via a ROM having a constant that presets C2 and multiplies its output by α, and a fourth shift register that feeds back to the input side via a ROM. The registers each constitute a shift circuit whose inputs are always long, and the outputs of the four shift circuits are combined and guided to a zero + constant circuit that outputs when the combined output becomes atmosphere, and the zero judgment circuit The error position is determined by latching the value of a counter that counts clocks having the same phase as the common clock of the shift register using the output pulse.

In the case of descending order, unlike the case of ascending order, the constants and preset values of the ROM are different, and the first shift register is C3.
(M-1), the second shift register presets C1α2(H-1) in a shift circuit that returns the output to the input side via a ROM having a constant that multiplies the output by α-3. After that, a shift circuit that feeds back to the input side via a ROM having a constant that multiplies the output by α-2 is connected to a third shift circuit.
The shift register is a shift circuit that presets σ2α (M-1 and then returns to the input side via a ROM that has a constant that multiplies its output by α″′), and the fourth shift register is always manually operated by C3. I am trying to configure a certain shift circuit.

[Effect]

A method of inputting C0 and C1° into the error locator polynomial in the order of yIl will be explained with reference to FIG. The four shift registers 1-4 are preset as shown and are softed by the clock. The shift register 1 outputs "1" at the first clock, C3 at the next clock, and C6, - at the next clock. This is (αO)3. (
α') 'J, (C2) 1. , -, which is equivalent to sequentially inserting C0°C1, C2, - into the ×3 term of the error locator polynomial. Regarding shift register 2, C1 (C0)2. σ, (C1)2°σl(C2)2.
-, and is input to the term σ X2.

The same can be said about the shift registers 3 and 4, and the output obtained by combining the above outputs in FIG. 2 is the result of adding symbols to X of the error locator polynomial σ(X) in ascending order from C0. Therefore, by measuring whether the output becomes zero and the number of clocks at which the output becomes zero, it is possible to determine which symbol in the code block causes an error.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit block diagram. This circuit is C0,
This circuit detects error positions in ascending order of C1, -. Further, FIG. 3 shows the operation of this circuit for the C1 (36, 30) code. In FIG. 1, multiplexer 1).
Shift register (single stage)12. σ(
The term X3 of X) is sent to multiplexer 14. Shift register (single stage)15. By ROM16, the term of X2 is
Multiplexer 17. Shift register (single stage) 18, R
OM19 converts the term of X into shift register (single stage) 2
0 gives a constant term σ3. ROM13 stores the coefficient value multiplied by α3, ROM16 stores the coefficient value multiplied by α2, and ROM1
9 has a coefficient value that is multiplied by α. Multiplexer l 1. ,
14. , 17. "l", C1, σ on the A side of
2, and C3 is input to the shift register 20 (multiplexer 1m 14.17 is 2
When 30 is "L", it switches to the A side, and when it is "H", it switches to the B side. Therefore, as shown in the time chart of FIG. 3, first, when E30 is set to "L" and the clock of E14 is input, the shift register 12, 15.18°20
are 1. C3, σ2. Outputs σ. When these outputs are combined by combining circuits 21, 22, and 23, signal 2
3a becomes 1+σl+σ2+σ3.

This is σ(C0)-(C0)3+σ,(C0)2+σ2
(C0)+σ3. E30 becomes "L" and multiplexer 1). 14,17. switches to the B side, E14
For each clock input, the values of σ(αl), σ(C2), and - are output as a signal 23a.

The zero determination circuit 24 inputs the signal 23a, and outputs a pulse to E35 when the signal 23a becomes "0". Each time a pulse of E35 occurs, a D-type flip-flop (hereinafter referred to as DFF) takes in the power, respectively.

The input of DFF28 is the clock of E14, which is input to the counter 27.
(directly. Karan Yu 27 is multiplexer 1). Since it is cleared by E30 which switches 14.17, σ(C0).

C0. which gives σ(C1)... It is counted simultaneously with C1, C2, and so on. Therefore, the count value of the counter 27 gives the number of digits of symbols in the ToSolomon code.

When an erroneous symbol is found, the number of digits is first latched in the DFF 28, and then when another erroneous symbol comes, the first number of erroneous digits is launched into the DFF 29, and the second number of erroneous digits is launched into the DFF 28.

When there are three error symbols in this way, the number of digits is latched in the DFFs 30, 29, and 28, respectively. Then, when P2O is input, α3. The number of digits αj, α″ (k>j>i) is latched.

In this circuit, the number of errors is also counted by the counter 25 at the same time, and the value is latched by the DFF 26.

FIG. 3 shows a case where an error occurs in symbols #L, #6° and #34. In the above embodiment, in ascending order, α0. α1
．． - and error positions are checked, but in descending order, αM-1.
It is also possible to investigate αM-2, -.... In this case, the ROM13. ROM16. By changing the constant of RO19 and the preset value, it is possible to check the error position using a similar circuit. However, the counter 27 is configured to count in descending order.

〔Effect of the invention〕

As explained hereafter, in the present invention, the value obtained by inputting αj to the variable
It can be easily obtained by finding each term in and composing them. This value is judged by a zero judgment circuit, and the pulse when it becomes zero is used to latch the value of the counter that counts the number of digits in ascending or descending order of j, thereby obtaining the error position. can.

The number of positions can be determined in all cases where the number of t'A ri is 1 to 3 symbols. A circuit for simultaneously measuring the number of errors is also added, but although the explanation will be omitted, this provides data for determining the execution policy when executing error patterns.

[Brief explanation of drawings]

The drawings relate to an embodiment of the present invention, and FIG. 1 is a circuit diagram, FIG. 2 is a diagram explaining the principle of the Chen algorithm, and FIG.
The figure is a time chart of the circuit of FIG. 1),. 14.17-・Multiplexer, 12.15,
18.20 --- Shift register, 13.16.19-
ROM. 21.22.23--Synthesis circuit, 24-Zero judgment circuit, 25.27--Counter, 2
6.28~33-・DFF (launch circuit).

Claims (4)

[Claims] (1) In decoding a Reed-Solomon code with 3-symbol error correction capability, the power α^j (j: integer) of the root α of the primitive polynomial is set as the variable X of the error locator polynomial
In this method, α^j is input in ascending order starting from j = 0, and is driven by a common clock. The first shift register is a ROM that has a constant that presets α^0 (=1) and then multiplies its output by α^3.
After presetting σ_1, the second shift register feeds back the shift circuit to the input side via α^
The third shift register is a shift circuit that feeds back to the input side via a ROM that has a constant that doubles the output, and the third shift register presets σ_2 and then feeds back the output to the input side via a ROM that has a constant that multiplies the output by α. and the fourth shift register constitute a shift circuit whose input is always σ_3, and synthesize the outputs of the four shift circuits,
It leads to a zero judgment circuit that outputs when the composite output becomes zero,
An error position in a 3 symbol error correction method characterized in that an error position is determined by latching a value of a counter that counts clocks having the same phase as a common clock of the shift register using an output pulse of the zero determination circuit. decision circuit. (2) Claim 1 further includes a counter that counts the output pulses of the zero determination circuit and calculates the number of errors.
Error position determination circuit as described in Section. (3) In the method of determining the error position, input of α^j is performed in descending order from j = M-1 (M: number of code symbols), and the configuration of the shift circuit using the four shift registers described in the first item is used. , the first shift register is α^3
After presetting ^(^M^-^1^), the second shift register is a shift circuit that returns to the input side via a ROM having a constant that multiplies its output by α^-^3.
After presetting α^2^(^M^-^1), the third shift register is a shift circuit that feeds back to the input side via a ROM having a constant that multiplies its output by α^-^2.
After presetting _2α^(^M^-^1), a shift circuit that feeds back to the input side via a ROM having a constant that multiplies its output by α^-^1, and a fourth shift register whose input is An error position determining circuit in a 3-symbol error correction system, characterized in that it constitutes a shift circuit that always has σ_3. (4) The error position determining circuit according to claim 3, wherein a counter is added to the circuit according to claim 3 to calculate the number of errors by counting the output pulses of the zero determination circuit.