JPS642293B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention is based on CRCC (Cyclic Redundancy Check).
This invention relates to an error correction device based on the Code), and particularly to improvements to its error position detection circuit.

[Technical background of the invention]

Recently, the development of digital audio equipment is progressing, and this type of equipment uses a CRCC code, also called a cyclic code, as an error correction code.

In other words, the principle of error correction using such a CRCC code is to use the remainder obtained by dividing the information bit by the generator polynomial as a check bit, and when decoding, the division is performed again and if there is no remainder, that is, if it is divisible, a code error ( Single error correction and double error detection are made possible by determining that there is no code error (error) and if there is a remainder, that is, if it is not divisible, there is a code error (error).

Now, as an example, the primitive polynomial G _(x) = 1 + x ⁵ + x ¹² +
Let's take a look at the decoding of a CRCC code with 80 information bits, 16 check bits, and a code length of 96 bits using ^x16 as the generator polynomial.

In this case, if the reception sequence r ₀ , r ₁ ... r ₉₅ is expressed by the reception polynomial (R _x ) as R _(x) = r ₀ + r ₁ x + r ₂ x ² + ... + r ₉₅ x ⁹⁵ , then this R _(x) above G _(x)
The presence or absence of an error and its contents are determined based on the syndrome given as the remainder after dividing by .

Here, the syndrome or remainder is given by R(α) if the root of G _(x) is α, and R(1), R
Due to (α), (1) There is no error when R(1) = 0 and R(α) = 0.(2) There is a single error when R(1) = 1 and R(α)≠0.(3) R(1) =0 and R(α)≠0, it is determined that there is a double error, and when it is determined that it is a single error (2), error correction is made possible by finding the error position. In addition, if it is determined that there is a double error in (3), it will be used to make appropriate corrections.

The detection of the error position in the case of _the above single error is based on the syndrome R(α)=
In the process of multiplying α95 ^-i by α an appropriate number of times, R
The number of multiplications when (α) = α ⁹⁵ , that is (i)
It is done in such a way as to seek.

FIG. 1 shows a conventional error position detection circuit configured based on the above principle. First, a received sequence is input to the divider circuit 11 via the input terminal IN, r ₉₅ ,
r ₉₄ , ... r ₆ are input in this order. Then, when all the received sequences are input, the output Q ₀ of the division circuit 11,
Q ₁ ...Q ₁₅ inevitably becomes syndrome R(α).

In this case, the division circuit 11 uses flip-flops FF ₀ to FF ₁₅ and exclusive ORs EX-OR ₁₁ to EX-OR ₁₃ to calculate the polynomial G _(x) =
Assuming that it is composed of linear shift registers connected in the form 1 + x ⁵ + x ¹² + x ¹⁶ , if this is shifted i times by the clock pulse described later, the contents R ₍ 〓 ₎ will be multiplied by αi. Become.

In other words, if a single error occurred at the (i)th position counting from r ₉₅ , then R(α) = α ^95-i would remain in the shift register that constitutes the division circuit 11; By shifting (i) times using the clock pulse from the clock terminal CK, R(α)= ^α95 .

Then, the outputs of the division circuit 11 are Q ₀ , Q ₁ , ...Q ₁₅
The pattern detection circuit 12 detects that α ⁹⁵ =(0010 1100 0010 0111) and outputs a latch pulse.

This latch pulse is supplied to a latch circuit 14 that latches the contents of a 7-bit counter 13 that counts the number of shifts by the clock pulse, and thereby an error position (i) output can be obtained from the latch circuit 14. .

[Problems with background technology]

However, in the conventional error position detection circuit as described above, the number of multiplications of α required to detect the error position is equal to the number of bits of the code length, which is up to 96 times in the above example. Since this method requires the same number of multiplications, there is a problem in that the processing time required for detection becomes longer.

[Purpose of the invention]

Therefore, the present invention has been made in view of the above points, and an object of the present invention is to provide an extremely good error position detection circuit that has been improved so as to be able to detect an error position in as short a time as possible. .

[Summary of the invention]

That is, the error position detection circuit according to the present invention includes a division circuit that divides a received sequence of code length N bits constituting a CRCC code by a linear shift register coupled to a predetermined generator polynomial, and a division circuit that divides a received sequence of code length N bits constituting a CRCC code by a linear shift register coupled to a predetermined generator polynomial. a pattern detection circuit for detecting a specific pattern giving an error position; means for shifting the register until the contents of the register of the division circuit match the specific pattern; and counting the number of shifts by this means to derive an error position output. and means for increasing the number of shifts (N) of the shift register to a maximum of N/m, assuming that the number of specific patterns detected by the pattern detection circuit is plural (m).
It is characterized by being configured to be able to reduce the number of times.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

That is, FIG. 3 shows a CRCC with information bits: 80, check bits: 16, and code length of 96 bits, with the primitive polynomial G _(x) = 1 + x ⁵ + x ¹² + x ¹⁶ as the generator polynomial, as in the case of FIG. 1 described above. This is an error position detection circuit applied to code decoding, and the received sequence from the input terminal IN is input to the division circuit 21 in the order of r ₉₄ , r ₉₅ . . . r ₀ . In this way, when all received sequences are input, the outputs of the division circuit 21 are Q ₀ , Q ₁ ...Q ₁₅
inevitably results in syndrome R ₍ 〓 ₎ .

Here, the division circuit 21 is composed of a linear shift register connected in the form of a polynomial G _(x) = 1 + x ⁵ + x ¹² + x ¹⁶ as shown in Fig. Therefore, if it is shifted (i) times, the content R ₍ 〓 ₎ will be multiplied by α ⁱ .

Then, the outputs Q ₀ , Q ₁ , ...Q ₁₅ of the division circuit 21
In this case, the pattern detection circuit 22 to which
Q ₀ , Q ₁ , ... Q ₁₅ is α ⁹⁵ = (0010 1100 0010
0111), α ⁶³ = (0000 0100 0010 1011), α ³¹ =
When it matches (0001 1001 1101 1000), α ⁹⁵ ,
The configuration is such that each output of α ⁶³ and α ³¹ becomes “1”. α ⁹⁵ of this pattern detection circuit 22,
The respective outputs of α ⁶³ and α ³¹ are supplied as the latch pulses of the 7-bit latch circuit 24 via the OR gate 23, and the outputs of α ⁶³ and α ³¹ are the set pulses of the upper two bits ²⁵ and ²⁶ of the 7-bit latch circuit 24. Supplied as.

Here, the 7-bit latch circuit 24 is configured such that the outputs ²⁰ to ²⁴ of the 5-bit counter 25, which counts the number of shifts of the division circuit 21 by the clock pulse, are input to the corresponding lower 5 bits ²⁰ to ²⁴ . There is.

Therefore, in the above configuration, the received sequence r ₉₅ ,
r ₉₄ ... r ₀ and i-th counting from r ₉₅ (0≦i≦95)
is incorrect, R ₍ 〓 ₎ = α ^95-i remains in the shift register constituting the divider circuit 21 at the time when the input of the received series is completed, and this is transferred to the clock terminal CK. By shifting the clock pulses from 0 to 1 a suitable number of times, the output is made to match α ⁹⁵ or α ⁶³ or α ³¹ .

In other words, if (i) is 0≦i≦31, then α with i shifts. If ³² ≦i≦63, then α with (i-32) shifts. If ⁶⁴ ≦i≦95, then (i-64) The pattern detection circuit 22 that detects this matches α ³¹ with each shift, and the α ⁹⁵ output is “1”.
, the latch circuit 2 is activated by this output.
The output of the 5-bit counter 25, which is latched at 4, directly provides the error position (i).

Furthermore, when the α ⁶³ or α ³¹ output becomes “1” in the pattern detection circuit 22, this output sets the ^25th or ^26th bit of the latch circuit 24, so that the 32nd or 64th bit is set by this output. 5
The sum added to the output of the bit counter 25 is derived as the error position (i) at that time.

In other words, in the above-described error position detection circuit, the pattern detection circuit 22 is designed to be able to detect not only α ⁹⁵ but also α ⁶³ and α ³¹ patterns. can be reduced to 32 times at most, so the processing time can be significantly reduced to 1/3 of the conventional time.

In general, this can reduce the maximum number of shifts required to detect error positions with a code length of N bits from the conventional N times to 2 ^m times (however, 2 ^m ≦N); The number of detected patterns (P) is P=N/2 ^m (when N/2 ^m is an integer) P=[N/2 ^m ]+1 (when N/2 ^m is not an integer [
] is a Gaussian symbol. It goes without saying that the present invention is not limited to the embodiments described above and illustrated, and that various modifications and adaptations can be made without departing from the gist of the invention.

〔Effect of the invention〕

Therefore, as described in detail above, according to the present invention, it is possible to provide an extremely good error position detection circuit that is improved so as to be able to detect error positions in as short a time as possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main part of a conventional error position detection circuit, FIG. 2 is a block diagram showing a specific example of the division circuit used in FIG. 1, and FIG. 3 is a block diagram of the error position detection circuit according to the present invention. FIG. 2 is a configuration diagram of main parts showing an example. IN...Input terminal, 21...Division circuit, 22...
...Pattern detection circuit, 23...OR circuit, 24...
...7-bit latch circuit, 25...5-bit counter, CK...clock terminal.

Claims (1)

[Claims] 1. A division circuit that divides a received sequence of code length N bits constituting a CRCC code by a linear shift register connected to a predetermined generator polynomial, and a pattern that detects a specific pattern that gives an error position from the output of this division circuit. An error location comprising a detection circuit, means for shifting the register until the contents of the register of the division circuit match the specific pattern, and means for counting the number of shifts by this means to derive an error location output. An error position detection circuit characterized in that the detection circuit is configured such that the number of specific patterns detected by the pattern detection circuit is plural (m) and the number of shifts (N) of the register can be reduced to a maximum of N/m times.