JPS5778608A - Decoding method of reed-solomon code - Google Patents

Decoding method of reed-solomon code

Info

Publication number
JPS5778608A
JPS5778608A JP55153419A JP15341980A JPS5778608A JP S5778608 A JPS5778608 A JP S5778608A JP 55153419 A JP55153419 A JP 55153419A JP 15341980 A JP15341980 A JP 15341980A JP S5778608 A JPS5778608 A JP S5778608A
Authority
JP
Japan
Prior art keywords
rom
dimensional vector
reed
address
solomon code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55153419A
Other languages
Japanese (ja)
Inventor
Tsuneo Hirose
Kenichi Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55153419A priority Critical patent/JPS5778608A/en
Publication of JPS5778608A publication Critical patent/JPS5778608A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13Linear codes
    • H03M13/15Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

Landscapes

  • Physics & Mathematics (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To make a calculation easy, to easily decode even in case when a distance between codes is >=4, and to easily change to hardware, by providing 2 specific ROMs, executing a specific conversion by each of them, and after that, executing the multiplication and addition. CONSTITUTION:In a Reed-Solomon code defined on a Galois body GF(2<k>), a k- dimensional vector on a Galois body GF(2) is made an address, and on its address position, the first ROM which has stored numerical information on the GF (2<k>) corresponding to this k-dimentional vector is provided. Also, the numerical information on the GF(2<k>) is made an adress, and on its address podition, the second ROM which has stored the k-dimensional vector information on the GF(2) corresponding to the number on said GF(2<k>) is provided. By use of a decoding circuit as shown in the fugure, the k-dimensional vector is converted to the number on the GF(2<k>) by the first ROM, and after that, multiplication is executed on the GF(2<k>), the number on the GF(2<k>) is converted to the k-dimensional vector by the second ROM, and after that, additon is executed on the GR(2).
JP55153419A 1980-10-31 1980-10-31 Decoding method of reed-solomon code Pending JPS5778608A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55153419A JPS5778608A (en) 1980-10-31 1980-10-31 Decoding method of reed-solomon code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55153419A JPS5778608A (en) 1980-10-31 1980-10-31 Decoding method of reed-solomon code

Publications (1)

Publication Number Publication Date
JPS5778608A true JPS5778608A (en) 1982-05-17

Family

ID=15562083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55153419A Pending JPS5778608A (en) 1980-10-31 1980-10-31 Decoding method of reed-solomon code

Country Status (1)

Country Link
JP (1) JPS5778608A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58219850A (en) * 1982-06-15 1983-12-21 Toshiba Corp Detecting circuit of error location
JPS58219848A (en) * 1982-06-15 1983-12-21 Toshiba Corp Multiplier of galois field
JPS595759A (en) * 1982-06-30 1984-01-12 Nec Home Electronics Ltd Read solomon code decoding system
JPS60232724A (en) * 1984-04-06 1985-11-19 アムペツクス コーポレーシヨン Error detection and correction of digital communication system
JPS6185677A (en) * 1984-10-02 1986-05-01 Nippon Columbia Co Ltd Error correcting device
JPS62188521A (en) * 1986-02-14 1987-08-18 Sony Corp Address generating circuit
JPH0637646A (en) * 1992-02-17 1994-02-10 Mitsubishi Electric Corp Error correction system and decoder using the same

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58219850A (en) * 1982-06-15 1983-12-21 Toshiba Corp Detecting circuit of error location
JPS58219848A (en) * 1982-06-15 1983-12-21 Toshiba Corp Multiplier of galois field
JPS638648B2 (en) * 1982-06-15 1988-02-24 Tokyo Shibaura Electric Co
JPS595759A (en) * 1982-06-30 1984-01-12 Nec Home Electronics Ltd Read solomon code decoding system
JPH0133055B2 (en) * 1982-06-30 1989-07-11 Nippon Denki Hoomu Erekutoronikusu Kk
JPS60232724A (en) * 1984-04-06 1985-11-19 アムペツクス コーポレーシヨン Error detection and correction of digital communication system
JPS6185677A (en) * 1984-10-02 1986-05-01 Nippon Columbia Co Ltd Error correcting device
JPS62188521A (en) * 1986-02-14 1987-08-18 Sony Corp Address generating circuit
JPH0637646A (en) * 1992-02-17 1994-02-10 Mitsubishi Electric Corp Error correction system and decoder using the same

Similar Documents

Publication Publication Date Title
Promhouse et al. The minimum distance of all binary cyclic codes of odd lengths from 69 to 99
JPS5778608A (en) Decoding method of reed-solomon code
JPS55161445A (en) Coding and decoding system
JPS5353205A (en) Decoder of error correcting code data
JPS542640A (en) Allocating circuit for microprogram address
JPS57209534A (en) Terminal controlling system
JPS54150905A (en) Decoding device
JPS5729155A (en) Error processing system
JPS5625851A (en) Coding method
GB882123A (en) Improvements in or relating to coding arrangements
JPS52119119A (en) Detection for error
JPS5357704A (en) Code detection circuit
JPS56159739A (en) Programable sequence controller
JPS5352307A (en) Band compression encoding system
JPS5399738A (en) Decoding system for variable length code
JPS51132048A (en) Computing circuit of cyclic code
JPS554775A (en) Generation and check circuit for hamming code for storage device
JPS51151037A (en) Dynamic decoder
Wallace Some techniques in universal source coding and during for composite sources
JPS5564456A (en) Error code generating circuit
Ramsey Readable erasures improve the performance of Reed-Solomon codes(Corresp.)
JPS5349904A (en) Binary code decoder
JPS5433639A (en) Information processor
Skattebol Further results on majority-logic decoding of product codes(Corresp.)
JPS56111349A (en) Encoding and decoding method