JPH0133055B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction decoding method using Reed-Solomon codes.

Reed-Solomon codes are one of the most powerful error correcting codes currently known for correcting random errors.

Regarding Reed-Solomon codes, the North Holland Publishing Company in the United States (NORTH-HOLLAND PUBLISHING
FJMACWILIAM, published in 1978 by COMPANY
and N.J.A. Sloan (N.J.A.
The Theory of Error Correcting Code (THE THEORY OF
ERROR CORRECTING CODES).

Since this code is a type of cyclic code, its encoding can be realized relatively easily using a well-known cyclic code encoder, but its decoding requires a general conventional method. This has the disadvantage that the device becomes very complex and the error detection ability of the code itself is not fully utilized.

The object of the present invention is to eliminate these drawbacks of the prior art.

In order to achieve the above object, the present invention provides a code length N (where M is a positive integer) that is generated from a generator polynomial obtained by the product of M (where M is a positive integer) first-order polynomials and is composed of N symbols. N is a positive integer larger than M) Reed-Solomon code is received, and each time each N symbol is received, the primitive element η _i (where η _i =α ⁱ , i= 0,...,M
-1, for i the syndrome S ₀ ,...S _i ,...
S _M-1 is given. ) by the received symbol,
The exclusive OR of this and the next received symbol is taken and stored in the shift register, and its output is branched and returned to the memory. This operation is performed for all N symbols, and the result is stored in the shift register. A syndrome calculation means that extracts the syndrome calculation output and a syndrome that is converted into a Galois field GF (2 ^y )
(where y is a positive integer) is expressed as a power of the atomic element α and calculates each corresponding exponent, and the power of the atomic element α corresponding to the syndrome obtained from the above calculation means. Exponent mod2 ^y −
1 addition and when this addition result exists, error position detection means detects it as an error position j; a syndrome obtained from the syndrome calculation means; and an error position j obtained from the error position detection means. and error correction execution means for executing error correction in response to the error correction.

Next, the present invention will be explained in detail with reference to the drawings.

FIG _. 1 is a block diagram showing an _embodiment of _the present invention.
..., S _M-1 arithmetic circuits 2, 3, 4, ..., 5, read-only memory (hereinafter abbreviated as ROM) for exponent calculation 6, 7, 8, ... 9, and mod255 addition circuit 1
0, 11, 12, ..., 13, error position (j) comparison judgment circuit 14, and syndrome zero judgment circuit 15
and an error correction execution circuit 16, in which syndromes S ₀ , S ₁ , S ₂ , ..., S _M-1 arithmetic circuit 2,
3, 4, ..., 5 correspond to the syndrome calculation means, and similarly, the following correspond to the index calculation means.
ROM 6, 7, 8, ... 9 and mod255 addition circuits 10, 11, 12, ..., 13, the error position (j) comparison judgment circuit 1 corresponds to the error position detection means.
4. The error correction execution circuit 16 corresponds to the error correction execution means.

Now, before explaining the details of the operation of this embodiment according to this block diagram, the principle of operation will first be explained.

Generally, in a Reed-Solomon code, N
symbols constitute one code block, and this one
M check symbols and N-
M information transmission symbols are included. Although there are various symbols used here, in this embodiment, an 8-bit code vector, which is generally widely used, is assumed. In order to make the explanation more concrete, it is assumed that the number of symbols (code length) in one code block is N, and the number of test symbols in one code block is M. Therefore, the number of information transmission data symbols in one code block is:
It becomes N-M.

Now, each of the N symbols in one code block is
A ₀ , A ₁ , A ₂ , ...A _M-1 , A _M , ..., Aj, ...
I will express it as A _M-1 . Any Aj is a 1-byte code and therefore represents one element out of 2 ⁸ =256 elements. Also, the symbol A _M ~
N-M of A _N-1 are symbols for information transmission data,
It is assumed that the remaining M symbols A ₀ to _{A M-1} are test symbols created based on A _M to _{A N-1} .

Now, in the Reed-Solomon code, during the encoding process, the test symbols A ₀ to _{A M-1} satisfy the following constraint relationship with the information transmission data symbols A _M to _{A N-1.} made in That is, A ₀ +A ₁ +A ₂ +...+Aj+...+A _N-1 =0 A ₀ +αA ₁ +α ² A ₂ +...+α ^j Aj+... +α ^N-1 A _N-1 =0 A ₀ +α ² A ₁ +α ⁴ A ₂ +...+α ^2j Aj +...+α ^2(N-1) A _N-1 =0 A ₀ +α ³ A ₁ +α ⁶ A ₂ +...+α ^3j Aj +...+α ^{3( N-1)} A _N-1 =0 〓 〓 〓 A ₀ +α ^M-1 A ₁ +α ^2(M-1) A ₂ +...+α ^(M-1)j ×Aj+...+α ^{(M-1) (N-1)} A _N-1 = 0 (1) In equation (1), in addition to the symbol Aj for each symbol, the symbol α is used, and the sum operation connected with + and α The calculations of the product between comrades (the power of α) and the product of the power of α and Aj are used. This α
represents a specific symbol, and the above-mentioned sums and products also mean special operations different from general binary sums and products. This will be explained below.

As mentioned above, in this embodiment, both Aj and α are code vectors made up of 8-bit "1" and "0" codes. Therefore, each represents one element out of 2 ⁸ =256 elements.

Now, select any two elements A and B from these 256 elements, and select the element A specified by the sum of these two elements.
Assuming that +B and the element AB specified by the product of two elements are each one of the original 256 elements, each can be defined as follows.

Sum: As shown in Figure 2, elements A and B are expressed in the form of code vectors, and the code vector resulting from the exclusive OR of each digit (each dimension) is expressed as A.
+B is defined. Because the sum operation is defined in this way, the sum of two same elements is always “0” (a code vector in which all the components of each dimension are “0”),
Further, the calculation of the difference as the inverse calculation of the sum is the same as the calculation of the sum.

Product: For example, if we have elements A and B as shown in Figure 3, we express them as a polynomial of χ: A = 1 + χ ² + χ ³ + χ ⁵ B = χ ² + χ ⁴ , and the product AB of this polynomial is AB = (1 + χ ² + χ ³ + χ ⁵ ) (χ ² + χ ⁴ ) = χ ² + (χ ⁴ +χ ⁴ ) + χ ⁵ +χ ⁶ + (χ ⁷ +χ ⁷ )+χ ⁹ . In this, terms of the same power of χ correspond to the same digit (dimension) of the code belt, so applying the above exclusive disjunction rule and rearranging the above equation, AB=χ ⁹ +χ ⁶ +χ ⁵ + χ ² . Since this polynomial includes a term greater than or equal to the seventh power of χ (ie, a term of χ ⁹ ), it is not possible to specify the corresponding 8-bit code vector as is.

Therefore, when defining the product, an irreducible polynomial f(χ) of degree 8 is determined in advance,
Using this, it is defined as follows.

If this f(χ) is defined as f(χ)=χ ⁸ +χ ⁵ +χ ³ +χ+1, then this f(χ) is used to divide the AB polynomial, and the resulting remainder is generated.

In this case, the remainder will always be a polynomial of degree 7 or lower than χ, so the corresponding 8
There is a code vector of bits. Product AB
It is defined as In this case, the polynomial of AB mentioned above is expressed as f
The quotient divided by (χ) is χ, and the remainder is χ ⁵ +χ ⁴ +χ (the above-mentioned exclusive OR rule is applied to this operation as well, and subtraction and addition are the same). From this, AB=χ ⁵ +χ ⁴ +χ, which is expressed as a code vector as shown in FIG. 32.

As described above, when the 8th-order irreducible polynomial f(χ) is specified, the sum and product are defined between each of the 256 elements, and the difference and quotient are also defined as their inverse calculations. Four arithmetic operations are performed consistently among 256 elements.

Now, by appropriately selecting the irreducible polynomial f(χ), all of the 256 elements except for "0" (an element in which all digit components are "0") can be solved. , can be expressed in the form of a power of some element α. In other words, the elements α, α ² ,
α ³ , . . . , α ²⁵⁵ can be made to go around all the elements except the aforementioned “0” and return to the identity element 1 again at α ²⁵⁵ .

Actually, if f(χ)=χ ⁸ +χ ⁵ +χ ³ +χ+1 is used as the irreducible polynomial f(χ), and χ in polynomial expression is used as α,
All elements of 255 are α ^j (where j=0, 1, 2,...
255). However, α ⁰ = α ²⁵⁵
=1. This α is called a primitive element, and the polynomial f(χ) having such properties is called a primitive polynomial. It is known that there are 16 8th-order primitive polynomials with such properties, including the ones mentioned above. In this example, it is assumed that operations between elements are defined by one specific primitive polynomial among these 16, and the primitive element α defined by this is used. Make it. This result is 0
Any element except α ^j (where j=0, 1, 2,...
..., 255), and therefore any element can be specified using only the index j. We will call this the original exponential representation. Using this exponential representation, the product of any two elements except “0” can be easily calculated by taking the exponential representation of each element and adding both modulo 255 as the exponential representation of the product of both. can do. If one element contains "0", the element of the result may be set to "0". In addition, when creating a quotient, the binary number in the original exponential representation that becomes the denominator is ``1'' for each digit,
Just invert "0" and then add 255 modulo as above.

Of course, when calculating the sum of two elements, it can be easily performed using code vector representation.

In this way, each element can be specified as a power of α, an exponential representation of α, a code vector representation, or a polynomial representation. Which of these expressions to use can be selected depending on the purpose of use.

Now, the operation of equation (1) has been defined in this way, but in reality, any information transmission data symbol A _M ~
To generate test symbols A ₀ to A _M-1 that satisfy the constraint condition of equation (1) from A _N-1 , do as follows.
Now, as the generator polynomial g(χ), g(χ)=(χ−
1) (χ−α) (χ−α ² ) (χ−α ³ )……(χ−
α ^M-1 ) is defined, and C(χ)=A _N-1 χ ^N-1 +A _N-2 χ ^N-1 +...+A _M χ ^M is defined as a one-sign polynomial C(χ). If the polynomial of the remainder obtained by dividing this C(χ) by g(χ) is R(χ), then R(χ) is M with respect to χ
- It is a polynomial of degree 1 or lower, so R
(χ)=b _M-1 χ ^M-1 +b _M-2 χ ^M-2 +...+b ₃ χ ³ +b ₂ χ ² +
It can be expressed as b ₁ χ + b ₀ . Thus determined b _M-1 , b _M-2 ,
……b ₃ , b ₂ , b ₁ , b ₀ are the inspection symbols, respectively.
When used as A _M-1 , A _M-2 , ..., A ₃ , A ₂ , A ₁ , A ₀ , these are inspection symbols that satisfy the constraint condition of equation (1) for the following reasons. It's summery.

Now, if we write the quotient of C(χ) divided by g(χ) as Q(χ), then C(χ)=g(χ)Q(χ)+R(χ), and from this, C(χ)+R (χ)=g(χ)Q(χ)
is derived (also in this case, subtracting R(χ) is R
(same as adding (χ)). Therefore C(χ)
+R(χ) is divisible by g(χ), A _N-1 χ ^N-1 +
A _N-2 χ ^N-2 ＋……＋A _M χ ^M ＋A _M-1 χ ^M-1 ＋A _M-2 χ ^M-2 ＋
...+A ₃ χ ³ +A ₂ χ ² +A ₁ χ+A ₀ = (χ-2) (χ-
2(χ−α)(χ−α ² )(χ−α ³ )……(χ−α ^M-1
)
Q(χ) holds true. By successively substituting 1, α, α ² , α ³ , . . . α ^M-1 into x on both sides of the above equation, the relationship in equation (1) is derived.

Now, the code blocks A ₀ , A ₁ , A ₂ , . . . that satisfy the constraint condition of equation (1) created on the transmitting side as described above are
…, A _N-1 , and they are A^ ₀ , A^ ₁ , A^ ₂ ,…
..., A^ _N-1 . It is assumed that an error occurs in only one symbol Aj among these. That is, for k other than j, A^ _K =A _K (2) holds true, and for Aj, A^j = Aj + ej (3). However, ej is an error occurring in the j-th symbol.

Now, on the receiving side, the received symbol A^ ₀ ,
Using A^ ₁ , A^ ₂ , ..., A^ _N-1 , perform the operation corresponding to the left side of each equation in equation (1), and calculate the results respectively.
S ₀ , S ₁ , S ₂ , ...S _M-1 . That is, S ₀ =A^ ₀ +A^ ₁ +A^ ₂ ...+A^j+...+A^ _N-1 S ₁ =A^ ₀ +αA^ ₁ +α ² A^ ₂ +…+α ^j A^j +… …＋α ^N-1 A^ _N-1 S ₂ =A^ ₀ ＋α ² A^ ₁ ＋α ⁴ A^ ₂ ＋……＋α ^2j A^j ＋……＋α ^2(N-1) A^ _N-1 S ₃ =A^ ₀ +α ³ A^ ₁ +α ⁶ A^ ₂ +...+α ^3j A^j +...+α ^3(N-1) A^ _N-1 〓 〓 〓 S _M-1 =A^ ₀ +α ^M-1 A^ ₁ +α ^2(M-1) A^ ₂ +... S _M-1 =A^ ₀ +α ^M-1 A^ ₁ +α ^2(M-1) A^ ₂ +... +α ^{j( M-1)} A^j＋……＋α ^(M-1)(N-1) A^ _N-1 (4)
shall be. If there is no error in reception, the left side of equation (4) will be exactly the same as the left side of equation (1), and therefore,
All of S ₀ to _{S M-1} should be "0". If there is an error in reception, the operation results corresponding to the left side of equation (4) will generally be non-zero values S ₀ , S ₂ , . . .
I will take S _M-1 . This is called a syndrome. This example uses the syndromes S ₀ to _{S M-1} and adds the
This method calculates the error amount from the constraint calculation relationship in equation (1) and corrects it.

Now, by substituting the relationships in equations (2) and (3) into equation (4) and using the relationship in (1), the result is as follows.

S ₀ = ej S ₁ = α ^j ej S ₂ = α ^2j ej S ₃ = α ^3j ej 〓 〓 S _M-1 = α ^(M-1)j ej ……(5) Transforming this equation (5), , the following formula is derived.

S ₀ ＝ej (6) α ^j ＝S ₁・S ₀ ^- ₁ (7) α ^2j ＝S ₂・S ₀ ^-1 (8) α ^3j ＝S ₃・S ₀ ^-1 (9) 〓 〓 〓 α ^(M-1)j = S _M-1・S ₀ ^-1 (10) Here, S ₀ ~ _{S M-1} is α under the condition of GF (2 ⁸ )
Expressed as a power of , and let α ^x0 to ^{α xn-1} , respectively, the above equations (7) to (10) become as shown in the following equations. Note that under this condition, α ^-x = α ^255-x .

j=(255−χ ⁰ )+χ ₁ …(11) 2j=(255−χ ⁰ )+χ ₂ …(12) 3j=(255−χ ⁰ )+χ ₃ …(13) 〓 〓 〓 (M −1) j=(255−χ ₀ )+χ _M-1 (14) The addition in these equations (11) to (14) is addition modulo 255, that is, mod255 addition. and,
Only when there exists a j value that satisfies the relationships in equations (11) to (14), error information ej is calculated for error position j.
= S ₀ can be used to correct it. Note that here, the error information ej is found as S ₀ from the above equation (6), and the error position j is found by calculating equations (11) to (14).

The configuration and operation thereof will be explained below using the embodiment of the present invention shown in FIG.

Transmission code blocks A _N-1 , A _N-2 ..., A ₂ , having N symbols transmitted from the transmitting side
A ₁ and A ₀ are as follows in the circuit of the present invention shown in FIG.
A^ _N-1 , A^ _N-2 ...A^ ₂ , A^ ₁ , A^ ₀ are input to the reception input terminal 1 in the order of M syndrome arithmetic circuits, that is, _S0 arithmetic circuit 2, S ₁ arithmetic circuit 3, S ₂ arithmetic circuit 4,
..., the syndromes S ₀ to S _M-1 shown in the above equation (4) are calculated by the _{S M-1} calculation circuit 5.

Incidentally, an example of an arithmetic circuit for calculating, for example, S ₁ is shown in FIG. 4. This is a 1-stage shift register 1
10, ROM111, and exclusive OR circuit 1
It consists of 12. Shift register 110 and exclusive OR circuit 112 each process 8 bits in parallel. The ROM 111 has 256 memory addresses that can be addressed by the output (8 bits) of the shift register 110, and has a capacity that can store 8 bits of data in each memory address. Data is read from the memory address of the ROM 111 specified by the output of the shift register 110, and the circuit 112 reads the data from the input terminal 1.
The exclusive OR is performed with the input data from , and this is read into the shift register 110 . ROM111 specified by arbitrary 8-bit binary number A'
αA′ (however, αA′ is this binary number
When the product of the code vector corresponding to A' and the primitive element α) is written, the ROM 111 operates as an α-times multiplier. Thus, if we first reset the shift register 110 and input the input data through the circuit 112 in the order of A^ _N-1 , A^ _N-2 , ...A^ ₀ as described above, then A When ^ ₀ is input, the contents of the shift register 110 are (...((A^ _N-1 α+A^ _N-2 ) α+A^ _N-3 ) α+...+
A^ ₁ )α+A^ ₀ =α ^N-1 A^ _N-1 +α ^N-2 A^ _N-2 α ^N-3 A^ _N-3 +…
…+αA^ ₁ +A^ ₀ , resulting in the desired syndrome S ₁ . By setting the contents of the ROM 111 to those corresponding to α ² , α ³ , ... α ^M-1 instead of α described above, each syndrome can be created using a similar circuit.
A circuit that calculates S ₂ , S ₃ , ...S _M-1 is obtained, and
By excluding the ROM 111 and feeding back the contents of the shift register 110 as is to the circuit 112, a circuit for calculating the syndrome _S0 can be obtained.

The syndrome S ₀ ~ _{S M-1} obtained in this way
are input as addresses to the above ROMs 6 to 9, and the exponents 255−χ ₀ , χ ₁ , shown in the above equations (11) to (14) are
χ ₂ ..., χ _M-1 are calculated respectively. This ROM6
~ ₉ is a kind of conversion circuit, which inputs the _above exponent 255− _χ0 ,
Data corresponding to χ ₁ , χ ₂ , ... χ _M-1 is stored, and by inputting S ₀ to _{S M-1} as addresses, the above indices 255−χ ₀ , χ ₁ , χ ₂ , ...χ _M-1 is what is output. Then, the 255−χ ₀ , χ ₁ , χ ₂ , ...χ _M-1 output in this way is supplied to the mod255 addition circuits 10 to 13, and the results are expressed as shown in equations (11) to (14) above.
Perform mod255 addition. That is, mod255 addition circuit 10
, receives 255−χ ₀ from ROM6 and χ ₁ from ROM7, performs mod255 addition shown in equation (11) above, calculates the result j, and uses this j as the error position (j). It is supplied to the comparison/determination circuit 14, and in the mod255 addition circuit 11, the 255−χ ₀ and
χ ₂ from ROM8 is received and shown in equation (12) above.
Perform mod255 addition to calculate 2j, supply this 2j to the error position (j) comparison judgment circuit 14, and in the same manner, in the mod255 addition circuit 13,
Receive 255-χ ₀ from ROM6 and χ _M-1 from ROM9, perform mod255 addition shown in equation (14) above to calculate (M-1)j, and calculate (M-1)j is supplied to the error position (j) comparison/judgment circuit 14. The error position (j) comparison/judgment circuit 14, which is thus calculated and supplied with j, 2j, 3j, ..., (M-1)j corresponding to the above equations (11) to (14), Error position information j is calculated from the information. This circuit not only calculates j from the above information, but also calculates 2j, 3j,...
..., (M-1)j is twice and 3 for j, respectively.
It is also confirmed that there is a relationship of times, . . . (M-1) times, and that each indicates the same error position j. Such a circuit can be easily realized by combining ordinary logic circuits, or by using a microcomputer or the like. The output signal of the error position j from the error position (j) comparison/judgment circuit 14 is supplied to the error correction execution circuit 16 to notify the error position.

The syndrome zero determination circuit 15
_{S0 , S1 , S2 , . _} This is a circuit that detects whether there are any errors in the received code block, or if S ₀ to _{S M-1} are not all zero but there is at least one zero, and there are two or more errors in the received code block. In the former case, that is, when S ₀ to _{S M-1} are all zero and there is no error in the received code block, an error-free signal is output on one output lead 400, and this error-free signal is output on one output lead 400. A signal is transmitted to the error correction execution circuit 16 to notify that there are no errors in the code block. Also, the latter, that is, S ₀ ~ _{S M-1}
If the received code block has at least one zero, but not all zeros, and there are two or more errors in the received code block, error 2 will be sent on the other output lead 500.
This signal is transmitted to the error correction execution circuit 16 to notify that there are two or more errors in the code block. In addition, if there is one error, S ₀ ~
S _M-1 is not all zero, but takes each value (11)
The values of j determined from equations (14) to (14) are all equal, and this is calculated as the j value to be compared by the error position (j) comparison and judgment circuit 14, and is supplied to the error correction execution circuit 16 for judgment. It will be done. At this time, S ₀ supplied from the S ₀ arithmetic circuit 2 is used as the error ej as shown in equation (6) above, the symbol at the error position j is corrected, and the symbol is output on the output lead wire 18. The corrected code block is sent out as data. Furthermore, at this time,
No error flag is sent out on the other output lead 17, indicating that the code block sent out from lead 18 is error-free. Further, when the code block has no errors and a no-error signal is supplied from the syndrome zero determination circuit 15 to the error correction execution circuit 16 via the lead wire 400, the code block supplied from the input terminal 1 is The error flag is output directly from the lead wire 18 via the error correction execution circuit 16, and at this time, no error flag is sent out at the same time. Further, if there are two or more errors in the code block and a signal of two or more errors is supplied from the syndrome zero determination circuit 15 to the error correction execution circuit 16 via the lead wire 500, error correction is not performed. Instead, the code block supplied from the input terminal 1 is directly output from the lead wire 18 via the error correction execution circuit 16 while containing errors, and at the same time is outputted from the syndrome zero determination circuit 15 via the lead wire 500. It is determined based on two or more error signals supplied, and an error flag is sent to the lead line 17 to notify that there is an error in the code block.

As explained above, according to the present invention, in a method for correcting one error occurring in a Reed-Solomon code in which N symbols form one code block, up to M check symbols can be used. It is possible to provide a highly reliable decoding method that effectively utilizes information on all the syndromes and achieves the objective with a simple circuit configuration. This makes it possible to improve reliability and economy. Furthermore, if two or more symbols of errors are detected in a code block, an error flag is sent to notify that there is an error in the code block.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a diagram for explaining the sum operation used in this example, Figure 3 1 is a diagram for explaining the sign polynomial for the operation used in this example, and Figure 3 2 is used in this example. FIG. 4, which is a diagram for explaining the product calculation, is a diagram showing an example of the internal circuit of the syndrome calculation circuit of this embodiment. 2-5... Syndrome calculation means, 6-9, 1
0 to 13... Index calculation means, 14... Error position (j)
Detection means, 15...Syndrome zero determination circuit,
16...Error correction execution means.

Claims (1)

[Claims] 1. Code length N (where N is greater than M) generated from a generator polynomial obtained by the product of M (where M is a positive integer) first-order polynomials and made up of N symbols. A large positive integer) Reed-Solomon code is received, and each time each N symbol is received, the primitive element η _i (where η _i =α ⁱ , i=
Syndrome S ₀ for 0,...,M-1,i,
...S _i , ...S _M-1 are given. ) is multiplied by the received symbol, exclusive ORed with this and the next received symbol, and stored in the shift register, and the output is branched and returned to the memory, and this operation is applied to all N symbols. syndrome calculation means for extracting the syndrome calculation output from the shift register ^; An exponent calculation means for calculating the corresponding exponent, and mod2 ^y −1 addition of the power exponent of the atomic element α corresponding to the syndrome obtained from the above calculation means, and when this addition result exists, it is used as the error position j. Error position detection means for detecting an error position; and error correction execution means for performing error correction upon receiving the syndrome obtained from the syndrome calculation means and the error position j obtained from the error position detection means. A Reed-Solomon code decoding method characterized by: