JPS63317837A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the data processing time by correcting the errors produced when data are read out of a recording medium concurrently with another process. CONSTITUTION:A read instruction and its object address on an optical disk are outputted from a microprocessor 14. When an address coincidence detecting circuit 8 has the coincident result, data are read out of the optical disk. These data are successively outputted to a 2-7 demodulation circuit 13 from a driving device with no interleaving to be stored temporarily in a buffer memory 15 and also to be given to an error syndrome calculation circuit 170. In other words, the data read out of the optical disk are stored in the memory 15 and at the same time the error syndrome is also calculated. As a result, the data processing time is shortened by an extent equivalent to at least a single sector.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a data processing device that performs all error corrections when reading data to which an error correction code has been added when writing data to a recording medium such as a disk. 1 (q) Conventional technology When transmitting digital data, a. It is essential to add an error correction code when transmitting data and to perform error correction when data money is received. In addition, all data can be recorded on various recording media, such as optical discs, magneto-optical discs, etc.
The same thing can be said about the successive editions.

Figure 4 shows all the standard formats of the data section for 17 digits when recording data on an optical disc, and Figure 5 shows the data section, the address section, and the 1 data section included in the data section. format of the entire sector)? That is, the data section includes original data D1 to D1024, control data P1.1 to P3.4, and cyclic redundancy check (CyClICRedundancy Check).
) result data area from CRCI to CRC4 and El,
Error correction code (Ili: C
C) The matrix data consists of 10 rows x 120 columns, and further includes sector marks 8B1 to SB.
3 and R3I to R859 f (1259 with YSYNC
A byte is formed, and l/FO (Vol.
stage Frequency 0scillator
) and 5YNC, which accepts the start position of the data.

-f This is an area in which various information that specifies all sectors is recorded in the address section (1 refi-1 maft section), including sector mark SM, VFO for synchronization detection, address mark AM, identification label ID, and its CFtC is composed of three sets □Each ID + CRC contains track address ゛rRKNO, sector address SgCT and these C
It is composed of RC. This address section and the data section described above constitute one sector of 1360 bytes of data.

Note that there is an 0DF (Off) for tracking control between the two.
set Detection Flag), gap 1
GAP, a light flag FLAG indicating whether or not data can be written to the data section, and an automatic laser power control ALPC for controlling the laser output during data writing are inserted.Furthermore, at the end of each sector, there is a light flag indicating whether data can be written to the data section. A buffer area BUFF is provided for dealing with errors in the rotational speed of the optical disc.

FIG. 6 is a block diagram showing the circuit configuration of an encoder for writing data to the optical disk having all the sector grooves described above.

1 in the figure shows a host system such as an optical disk file device,
2 is a puff-fame 7 IJ (RAM) that temporarily stores all signals such as data sent from the host system 1, 3 is a CRC calculation circuit that performs all cyclic redundancy checks, 4 is a control data addition circuit, and 5 is a buffer memory. 2. A first incremental buffer memory for temporarily storing the output data from the CRC calculation circuit 3 and the control data addition circuit 4 and interleaving it at the time of output; An error correction code (F:CC) calculation circuit for creating an interleave buffer memory 5 and z fi: a second interleaving buffer for interleaving the output data of the CG calculation circuit 10, ll 12 is a P/S conversion circuit that converts the baffle output data of the interleague buffer memory 9 into serial data, and 12 is a P/S conversion circuit K11 (1) output data 2-
□ This is a 2-7 modulation circuit that modulates the data and outputs it to a drive device (not shown) for writing data to an optical disk.
``Ma1, 6 is the control center of this encoder, 7 is the timing pulse generation circuit that generates the timing pulse of the 7rx encoder, and 8a is the address of the optical disk where the data is to be written, and the drive circuit is the address of the data. This is an address match detection circuit that completely detects whether or not the write location matches the write address.

In this simple encoder, as shown in the timing chart in FIG. 7, data will be written to the optical disk at the following timings.Data D1, D2...D102 is sent from the host system 1
When 4 (or more than a) are sent out sequentially, one shell is stored in these ho/<rahua memory 2. When a write command 4 is given from the micro 10 setter 6, one unit of data (Di~
D1024) is sequentially read out from the buffer memory 2, or the CRC calculation circuit 3 and control data addition circuit 4 process the data read out from the buffer memory 2.
1 to CRC4 and control data P1.1 to P3.4
and is stored in the interleague buffer memory 5. This interleave buffer memory 5 contains data D1 to D1024 of one sector worth of data area, CRCI
~ When CRC4 and control data P1.1 to P3.4 are taken in, the interleaf buffer ame-v=su5rc
D1. Dtx, D21-D1021, D2.012...
・The data is outputted sequentially while being interleaved. The data is directly input to the interleague buffer memory 9, and also to the ECC calculation circuit IO: Riefu correction codes E 1.1 to EI 0.16 are created. Then, the ECC calculation circuit 10i'! 7j For example, it is a circuit that creates a Reed-Solomon (R8) code as shown in FIG. 10, which can perform all error correction in 1-byte block units □In other words, the product of the parity check matrix and the data is the error syndrome 5O-815 69, if this error syndrome SO~S15 is 0, it completely indicates that no error has occurred □ At the time this ECC is calculated, the CRC calculation of the next sector and the addition process of control data are performed. □ Then, when the address coincidence detection circuit 8 detects that the address specifying the sector for data writing output from the micro 10 setter 6 matches the current position of the drive device, Data from interleave buffer memory 9 is Dl, D2, D3...D1024...El
, 1...EIO216... are interleaved again and read out sequentially in the original order, and the data synchronization signal 5
P/S with YNC or aRESYNC added
After being ECC-modulated by the 2-7 modulation circuit 12 via the K conversion circuit 11, it is sent to the drive device.At this point, the ECC of the next sector is being calculated, and the CRC of the next sector of the friend is being sent. calculations and addition of control data are being performed.

As described above, data is written to the optical disk in the format shown in FIGS. 4 and 5.

On the other hand, as shown in FIG.
FIG. 3 is a block diagram showing a circuit configuration of a decoder for reading out all data.

In the figure, 13 is a 2-7 demodulation circuit that demodulates the 2-7 signal read from the optical disk, and 15 is a 2-7 demodulation circuit installed in the drive device.
7 a buffer memory for temporarily storing all demodulated signals in the demodulation circuit 13; 17 a position of the error syndrome;
Error syndrome calculation circuit for calculating length, 1
8 is an error correction circuit that calculates the error syndrome detected by the F-syndrome calculation circuit 17; 19r;
X is a CRC calculation circuit, 14i is a micro 10 safety circuit that controls all of this decoder, and 16 is a timing pulse generation circuit that generates timing pulses for the decoder.

In this :tsuna decoder, data is read from the source disk at the following timings, as shown in the timing chart of FIG.

The read command and the target address on the original disk are output from the Micro 10 setter 14, and when the detection results of the address match check circuit 8 (shared with the encoder) match, data is read from the optical disk and the DI , D2・
...D1024, Pl, 1, PL, 2...El,
1...EIO516 are output from the drive device to the 2-7 demodulation circuit 13 in order, and the
Temporarily stored in 5 and set to 1. This bread 7 amemory 15 to 1
Once the sector worth of data has been stored, these data are transferred from the buffer memory 715 to the error syndrome ftXrl path 17.
I, Dll...D1021, R2,3, El, ■...
・El, 16, L) 2, Dl2...DI 022...
. . , and is read out and given to the error syndrome calculation circuit 17, where the error syndrome is calculated.

At this point, the next sector is being read.

If no error occurs here, that is, if the results of the error syndrome calculation are all 0, the bar 77 memory 15 outputs a tetator through the CRC calculation circuit 19t, while the error syndrome calculation circuit 17Vc outputs the error syndrome. When it is determined that there is no 7% OC, data is sent to the error correction circuit 18 to detect the position and t (length) of the error syndrome, and perform CRC calculation based on this. Output.

G=1 Problem to be Solved by the Invention Conventionally, when reading data from an optical disk, in order to calculate the error syndrome x, the data read from the optical disk is stored in the -EL puffer memory and dynleaved. Therefore, at least one sector's worth of data processing time is required. Therefore, it is expected that it will be difficult for conventional devices to smoothly cope with the large increase in the amount of data expected in the future. The invention was made in view of these two circumstances,
The object of the present invention is to provide a data processing device capable of processing data at a much higher speed than the conventional device having the above-mentioned configuration and capable of completely reading data from an optical disk. The invention is provided with an error syndrome calculation circuit comprising the predetermined number of circuits that interleaves matrix data and calculates a predetermined number of error syndromes for nine read rows or one column when reading data from a recording medium. In the data processing device, the error syndrome calculation circuit is provided with a row of the matrix data in each of the predetermined number of circuits! Is it possible to have a memory area equal to the number of columns, and to read the data in VC in the order of arrangement and store the error syndromes of each row and 7ti valleys sequentially in the above storage area? Features □ (1) In the data processing device of the present invention, when reading μ and f'-data (7) from the disk, a memory IJ such as RAM is added to the error syndrome calculation circuit and processing is performed in a time-divided manner. Specifically, the error syndrome is calculated at the same time as the data successively output from the optical disk is stored in the buffer memory.

(F) Embodiment A predetermined decoder for reading data from an optical disk of a data processing apparatus of the present invention will be described with reference to the program diagram of FIG. 1 showing its circuit configuration.

In the figure, a 2-7 demodulation circuit that demodulates the signal Tl-2-7 read from the F optical disc into the 13i drive device, and 2-7 demodulation circuit in 15
-7 There is a buffer that temporarily stores all demodulated signals in the demodulation circuit 13! J, 170 F-syndrome calculation circuit for calculating all the positions and lengths of H error syndrome, 180 e-syndrome) '0-me total 3E circuit 170
19 is a CRC calculation circuit; 14 is a microprocessor for controlling the entire decoder; and 16 is a timing pulse generation circuit for generating all timing pulses of the decoder.

In such a decoder, data is read from the optical disk in the following manner, as shown in the timing chart in FIG. 9 mentioned above.

A read command and the target address on the optical disk are output from the microprocessor 14, and when the detection result of the address match detection circuit 8 (shared with the encoder) matches, the data is read from the optical disk. D.I., D.
2...D 1024,)'t,t%P1.2...E
1, 1, . The error syndrome calculation circuit 170 is configured as shown in FIG. Incidentally, FIG. 3 is a timing chart thereof. That is, 16 individual circuits 171 to 186i are provided for determining the syndromes SO to S15 of the t Reed-Solomon code shown in FIG. 10, respectively.

It has almost the same configuration as a known circuit for calculating an error syndrome in each vfJ path 171 to 186 itself, and first a circuit 1 for installing a first error syndrome calculation circuit.
The data input to the circuit 71 is circulated through a roof made up of an adder A171, a latch circuit L171, and a coefficient multiplier C171, and the results are sequentially sent to the subsequent circuit 17.
2.173... are given as respective data inputs, but the outputs of the respective latch circuits L171-186? As in the case of the error correction code calculation circuit 100 described above, RAM171-RAM186 having all addresses 1 to 10
RA
M171 stores the error syndrome SO for each of the 10 rows of data in Figure 4, and RAM 172 stores SL, and so on, up to S15. □ Then, error correction is required. If so, each circuit 171 to 18
Syndrome read signals 5YO-8Y15 all, -! Each RAM171-RA
Is there a signal that specifies all 9 addresses Xi to 10 in M186? I'm glad to give it to you, xwo-shin)'1lff l
= Output the result kW, and give it to the error correction circuit 18 to perform all error correction □ To execute the above complicated operations: The data read from the optical disk is stored in the buffer 15, and at the same time the error is detected. Syndrome SO
Since the calculations in steps S15 to S15 are performed simultaneously, the processing time is reduced by at least one sector compared to the conventional method, as shown in the lower half of FIG.

Although the above embodiment describes an example of reading data from an optical disk as a recording medium, it goes without saying that the invention can be applied to other recording media. Is it possible to correct errors when reading data from a recording medium using the data processing device of the present invention that is more effective than it is effective? , conventionally, each process was performed independently, and the other process was performed simultaneously with other processes, which shortened the overall processing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the decoder of the data processing device of the present invention, FIG. 2 is a block diagram showing the configuration of the error syndrome calculation circuit, FIG. 3 is a timing chart showing its operating state, and FIG. 4 5 is a schematic diagram showing the 7t-matte data portion of one sector of an optical disk to be processed by the apparatus of the present invention, FIG. 5 is a schematic diagram also showing the format of one sector, and FIG. FIG. 7 is a schematic diagram showing the data processing state of this encoder in sector units when writing data to an optical disk. FIG. 8 is a block diagram showing the configuration 1 of a decoder of a conventional data processing device. Figure, No. 9
Figure a: Data processing status of the present invention device and the conventional device when data is extracted from an optical disk? FIG. 10 is an explanatory diagram of the Nireed-Solomon code, which is a schematic diagram shown in sectors. FCC...Error correction code, Dl, D2...: Data, SO~S15: Error syndrome °, L1~L1
6, L171-L, 186: Kufuchi circuit, RAM1-R
AMI 6, RAM171 to RAMI 86: Memory, 2: Buffer memory, 170: Error syndrome calculation circuit □

Claims (1)

[Claims] (1) Data processing equipped with an error syndrome calculation circuit consisting of the above-mentioned predetermined number of circuits that calculates a predetermined number of error syndromes for each row or column read by interleaving matrix data when reading data from a recording medium. In the apparatus, the error syndrome calculation circuit has a storage area equal to the number of rows or columns of the matrix data in each of the predetermined number of circuits, and calculates the error syndrome of each row or column by reading the data in the order of arrangement. A data processing device comprising: a memory for sequentially storing data in the storage area.