JPS58123144A - Decoding system of read solomon code - Google Patents

Abstract

PURPOSE:To use effectively the information on all syndromes of checking symbols and at the same time to simplify the circuit constitution, by applying a system which delivers an error flag after detecting an error by means of a read Solomon code. CONSTITUTION:For all positive values in which the shift clock number (i) delivered from a syndrome arithmetic controlling circuit is less than the symbol number forming a code block, an intermediate information all-zero deciding circuit 9 delivers no signal showing that intermediate informations M0-M2 are all 0. In such a case, an output showing that the coincidence is obtained between intermediate information ratios j' and j'' is supplied from an intermediate information ratio comparator 8 via a line 110 with an optional value of 1<=i<=32. At the same time, a signal showing that 0 is not contained in the informations M0-M2 is supplied to a correction execution driving circuit 13 from an intermediate information zero detecting circuit 10 via a line 109. In such a case, it is decided that two symbols are wrong. Both i and j' are supplied to an error correction executing circuit 14 via lines 115 and 116 respectively and in the form of error symbol positions.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction decoding method using Reed-Solomon codes.

Reed-Solomon codes are one of the most powerful error-correcting codes currently known for correcting random errors.

Regarding Reed-Solomon codes, North Holland Publishing Company (N0RTH-HO
Published in 1978 by LLAND PUBLISH ENGINEERING COMPANY
) F.A.A. Sloan (N, J, A, 5L
THE THEORY OF ERRORC
ORRKCTING C0DKS ) K detailed sale tale.

Since this code is a type of cyclic code, its encoding can be realized relatively easily using a well-known cyclic code encoder, but its decoding requires a general conventional method. This has the disadvantage that the device becomes very complicated.

The object of the present invention is to eliminate these drawbacks of the prior art.

The method of the present invention uses a Reed-Solomon code of length N (Ni1t, a positive integer greater than M) generated from a generator polynomial formed by the product of M (M is a positive integer) first-order length terms. A code is received and M syndromes So, Sl,
..., after calculating 5M-1 and detecting the syndrome, correct the error.JIS is 1,400 meters = ★4h spider
The received code-11 is output and errors of 3 or more symbols are detected. ...,
M-1 determined by preset calculation from 5M-1
an intermediate information calculation means for calculating intermediate information of pieces; an intermediate information all-zero determination means for determining whether each piece of the intermediate information is "0"; and at least one piece of molO intermediate information among the intermediate information. intermediate information zero detection means for determining whether or not the
intermediate information ratio calculation means for calculating M-2 intermediate information ratios from the intermediate information; intermediate information comparison means for determining whether all of these pieces of information are equal; and symbols that can be generated by the intermediate information calculation means. In response to the position and the output of the intermediate information all-zero determination means, it is determined whether or not error correction of 17 symbols should be performed according to a predetermined algorithm. In order to cope with this, a one-symbol error correction means that performs error correction on the symbol using the syndrome So as error zero-hand information, a symbol position that can be generated by the intermediate information calculation means, and the intermediate information zero detection means In response to the output and the output of the intermediate information comparison means, it is determined whether or not to perform two-symbol error correction according to a predetermined algorithm. By using the error symbol positions i y and j++5a, calculate the i information to be used for error correction for each of the specified symbol positions 1s and L. and correction means.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, 1... syndrome calculation circuit, 2... syndrome calculation control circuit, 3... syndrome storage circuit, 4...
- Intermediate information Mo calculation circuit, 5... Intermediate information M1 calculation circuit, 6... Intermediate information M2 calculation circuit, 7... Intermediate information ratio calculation circuit, 8... Intermediate information comparison circuit, 9... - Intermediate information all-zero determination circuit, 10... Intermediate information zero detection circuit, 11... Error correction information gi, Ej calculation circuit, 1
2...Constituted by Sindh.

Now, before explaining the details of the operation of this embodiment according to this block diagram, the principle of operation will first be explained.In general, in a Reed-Solomon code, N symbols constitute one code block, This one code block includes M check symbols and NM information transmission symbols. There are various types of symbols used here, but in this example, the commonly used 8 symbols are used.
Assume a code vector of bits. In order to make the explanation more concrete, it is assumed that the number of symbols (code length) in one code block is N-32, and the number of test symbols in one code block M=4. Therefore, the number of information transmission data symbols in one code block is NM=28.

Now, let each of the 32 symbols in one code block be represented by . Any Bj is a 1-byte code and therefore represents one element out of 28=-256 elements. Also, among these, there are 28 exemplary information transmission data symbols B4 to B31, and the remaining Bo-B3 are B4. Assume that the test symbol is created based on ThB5+.

Now, in the Reed-Solomon code, during the encoding process, the test symbol Bo = B3 td, h
It is created so as to satisfy the following constraint relationship with the lf reporting data symbols B4 to B13at. That is, in this equation (1), the symbol B for each symbol and 1 for 1 (crab symbol) are used, and the sum connected by tens is used.
1, the product of α (α of 1), and the product of 7 of α and Bj are used. This α represents a specific symbol, and the sum and product mentioned above are also general 2
Colors special operations different from sums and products of base numbers. This will be explained below.

As mentioned above, in this embodiment, both Bj and α are code pects made of 8-bit Jl, 101 code.

Therefore, each represents one element out of 2B=256 elements.

Now, select any two elements A and B from these 256 elements, and select the elements A + B and 2 specified by the sum of these two elements.
Any of the elements AB specified by the product of two elements is the original 25
Assuming that it is one of six elements, each of them is defined as follows.

昶：As shown in FIG. 2, elements A and B are represented in the form of code vectors, and the code vector resulting from taking the exclusive moral sum for each digit (each dimension) is defined as A+B. Because the sum operation is defined in this way, the sum of two same elements is always 101 (the components of each dimension are all “sign vector of OI +
Furthermore, the operation of the difference as an inverse operation of the sum has the remarkable result that it is the same as the operation of the sum.

Bond: For example, if we have =A and element B as shown in Figure 3, we can define this as a polynomial representative of X (current A = 1 + X2 + x3-) x5B = x2-1
-x4, and the product AB of this polynomial is AB=(1+x2+x3+x5) (x2+x4)
=x2+(X'+X4)+X5+X6+(X7+X
7) Make it like +X9. Among these, the terms of the same first power of X correspond to the same digit (dimension) of the code vector, so if we apply the above-mentioned exclusive sum rule and rearrange it, the above equation becomes A B = x9-1 −x6 +x5 +x2. Since this polynomial includes a term equal to or higher than the seventh power of X (that is, the term x9), it is not possible to specify the corresponding 8-bit code vector as it is.

Therefore, when defining the product, an irreducible polynomial f (X) of degree 8 is determined in advance and is used to define the product as follows.

Assuming that f(X) with is f(X)=X8+X5+X3+X+1, then f(X) with is calculated by ;1] to calculate the polynomial of AB, and the resulting remainder is created. In this case, the remainder will necessarily be a polynomial of degree 7 or lower than X, and therefore an 8-bit code vector will exist corresponding to this. This is defined as product AB. In this case, the quotient obtained by dividing the AB polynomial by f(x) is X9, and the remainder is subtraction and addition are the same). From this, AB=x5-1-x'+x, which is expressed as a code vector in Figure 3, 2
).

As described above, when the 8th degree irreducible polynomial f (X) is specified, sums and products are defined among 256 6-likelihoods, and their inverse calculations are also performed. The difference and quotient are also defined, and the four arithmetic operations are performed consistently among the 256 elements.

Now, by appropriately selecting the irreducible polynomial f (X), all 256 elements except 10'' (all digit elements are elements of llO'') can be It can be expressed as the first power of the element α. That is, by taking 1 as a unit light and multiplying it by α one after another, the elements α, α2 . α3. . . . α255 can be made to go around all the elements except the above-mentioned 101 and return to unit light 1 again at α255.

Actually, as the irreducible polynomial f (X), f(x)=
Using x8+x5+x3+x+1 and using polynomial expression X as α, all elements of 255 are αJ (however, j=o, i, 2...
, 255). However, αO=α2
55=1. This α is called a primitive light, and the polynomial f (X) having such properties is called a primitive polynomial.

It is known that the 8th order primitive polynomial having such properties, including the above-mentioned one, has a power of 161 vA. In this embodiment, the following examples are used: 6. ．． Assume that operations between elements are defined by a specific primitive polynomial among the elements,
Also, the primitive light α defined by this will be used. As a result, any element other than 0 is αa (however;
=o, 1, 2. ..., 254), and therefore any element can be specified using only the index j. We will call this the original exponential representation. Using this exponential representation, the product of any two elements except 'O1 is 6
By taking the exponential expression of each element and adding both of them modulo 255, it is possible to easily calculate the exponential expression of the product of both. If one of the elements contains @01, set the result element to "Ow".Also, when creating a quotient, change the binary number of the exponent representation of the original denominator to "Ow" for each digit. It is sufficient to invert l'"0" and then add 255 as a modulo in the same manner as described above.

Of course, when calculating the sum of two elements, it can be easily done by using a sign vector representation. In this way, each likelihood can be expressed as a sign vector, whether expressed as the first power of α or as an exponential representation of α. It can be specified either as a representation or as a polynomial representation. Which of these expressions to use can be selected depending on the purpose of use.

Now, the operation of equation (1) has been defined in this way, but in reality, from any information transmission data symbols B4 to B3+ (
1) Inspection symbols BO to B3 that satisfy the constraint conditions of Eq.
To generate , do the following:

Now, as the generator polynomial g), g(X) = (X-1) (X-a) (X-a2)
(X-a3), and on the other hand sign polynomial 2C) as C
(X)==B3. X31 +B3oX30+・・・・・
, -1-B4X4. If the polynomial of the remainder obtained by dividing this C(X) by gσ) is expressed as R), then RCx) is a polynomial of degree 3 or lower regarding X, so R(lK)=b3X3+b2X2+b1x+b.

It can be expressed as b3 determined in this way. b2. bl and b
O respectively as inspection symbols B3. B2. Bl and HiBO are the formulas for 1 and 2 are the following 01 reasons''c (3,
This is an inspection symbol that satisfies the 4o constraint conditions.

Now, if we write the quotient of CC1C) divided by g as Qσ), we get C
to)=gσ)Qσ)-1-R), and from this, 0
ward) + Rσ) = gσ) to Q) is derived (also in this case R
Subtracting ) from is the same as adding l). Therefore, C(X)+Rσ) is divisible by g(X) and Ba1
X"+B3oX"+-...10B4X'10B5X3+B
zX2+BIX+BO=(X-1)(X-α)(X-α
2) (x-α3)Q(X) holds true. Add 1. to X on both sides of the above equation. α.

By substituting α2 and α3 one after another, (
1) The relationship of equation is derived.

Note that when the generator polynomial g(X) is given, the above-mentioned division is executed to obtain the symbol Bo%B3 of B4~]3at.
It is also easy to determine the configuration of a cyclic code encoder that generates symbols, but this is omitted here.

Now, the code blocks Bo, B, , B2 that satisfy the condition of equation (1) created on the transmitting side as described above are
,......

△ △ △ △ Bank is received and they are BO + B1 + B2.・
- Assume that it is received as "" + Ba1. And for two of these, namely i and k other than J, BK = Bk・・・・・・・・・・・・・・・・・・
...(2) Bi:B1-1-Ei...
...(3) Perform the calculations, and each result is 5oS
IS2S3. In other words, let. If there is no error in reception, the left side of equation (5) will be exactly the same as the left side of equation (1), and therefore 5o
-83 are all ``If there is an error in the reception of Samurai Rumorji i0, the calculation results corresponding to the left side of equation (5) will generally take the respective values s, sl, s2., and B3 that are not O. This is called a syndrome.

This example uses this syndrome 5o=Sawo,
) This is a method in which the error is determined from the constraint calculation relationship of equation (1) added between the symbols in the -pronk on the transmitting side and corrected.

Now, by substituting the relationships in equations (2), (3), and (4) into equation (5) and using the relationship in (1), the result is as follows.

By transforming this equation, the following three equations are derived.

Here ai So+S, = MO α’S1+SZ””Ml ai　52-4-83=M2 Based on the relationship in equation (7), the following equation is derived.

y,=y,-(=αj)・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・(8) Morl
H Therefore, it can be found assuming a two-symbol error.

In addition, the error cluster information Ei and Ej for the error symbol position and j can be obtained from equation (6), and can be calculated using the following two equations.
The determined error 4'1=ffi information E1. Error correction of two symbols can be performed using equations (3) and (4) for E, 1 and error symbol positions i, j.

Now, in the case of a one-symbol error, if the position of the erroneous symbol is set to 1, then by setting 1=O in the method, the following three equations can be obtained. If the relationship of equation (10) is satisfied, it is nothing but a one-symbol error.

At that time, the error symbol E1 for the error symbol placement i
can be expressed by the following formula.

Ei=So . . . αυ Therefore, one symbol error correction can be performed from equation (3).

Next, details of the operation of this embodiment will be explained using FIG.

The code block of the received input signal is the data △
△ From input line 100, each symbol is B31 T B2
O1...

Mu The eyes are supplied to the syndrome calculation circuit 1 in the order of Bo. Ru. At the same time, it is also supplied to an error correction execution circuit.

In the circuit l, the calculation corresponding to the equation (5) is first executed, and the syndromes SQ, Sl, S2 . and S3 are obtained. An example of a circuit for obtaining the above syndrome 5o-83 is shown in FIG.

In FIG. 4, switches SW1 and S'91/2 are A
Connect it to the position. (The case where it is connected to position B will be described later.) This circuit consists of a one-stage shift register 30
, 31 , 32. 33, read-only memory (ROM)
25, 26, 27, 28, 29, and an exclusive OR circuit 21, 22, 23, 24. Shift registers 30, 31, 32, 33 and circuits 21, 2
2, 23, and 24 each process 8 bits in parallel. Also, ROM25, 26, and 28 are the same ROM, and ROM'25 is addressed by the output (8 bits) of shift register 30, and ROM26 is addressed by the output (8 bits) of shift register 30.
The address is specified by the output of 1 (8 bits). Similarly R
OM 27, 28 and ROM 29 are addressed by shift registers 32 and 33, respectively. Each ROM is 25
It has 6 memory addresses, and each memory address has a capacity to store 98 bits of data. Taking the circuit for calculating Sl as an example, data is read from the memory address of the ROM 26 specified by the output of the shift register 31, exclusive ORed with the input data by the circuit 22, and this is stored in the shift register 31. is loaded into. If αA' (where αA' is the product of the code vector corresponding to this binary number A' and the primitive element α) is written to the memory address of the ROM 26 specified by an arbitrary 8-bit binary number A', then , ROM26 operates as an α-times multiplier. Thus, first, the shift register 31 is reset, and the input data △ △ △ is changed to B31, "30 +...," as described above.
When inputted through the circuit 22 one after another in the order of BO, BO
is input α+B′0=α31B3. 10α30B30
＋・・・・・・＋αpick＋伶=s.

Therefore, the desired syndrome SL is obtained. By setting the contents of ROM# to be equivalent to α2 and α3 instead of α described above, a circuit for calculating syndromes S2 and S3, respectively, can be obtained using a similar circuit, and the shift register 31 except for the ROM 26 can be obtained. If the configuration is configured such that the contents of are directly clicked into the circuit 22,
A circuit for calculating the syndrome SO is obtained.

The syndromes SO to S3 thus obtained are supplied to the syndrome storage circuit 3, syndrome all zero,
Also, in order to perform the calculation corresponding to the above equation (9), error information E1. The signal is supplied to the Ej calculation circuit 11.

Also, the syndrome Sl stored by the circuit 3.

S2. S3 is provided to intermediate information MO calculation circuit 4, intermediate information Ml calculation circuit 5, and intermediate information M2 calculation circuit 6, respectively,
Again, it is assumed that the subsequent shift clock number 1 given by the syndrome calculation control circuit 2 is output to the output line 106 in the same manner as in the calculations for the syndromes SO to S3. R
Since OM 25, 26, and 28 all operate as α-times multipliers, the shift register 30 when the number of shift clocks is 1
, 31.32 are αl5O9αN S l, αi respectively
The calculation result represented by S2 will be output. Here, the outputs of the shift registers 30, 31.32 are sent to circuits 4 and 5 via lines 101 and 102, 103, respectively.
, are supplied to the circuit 6.

Circuits 4 and 5.6 are exclusive OR circuits, in which (113o + S 1 ("" MO) is calculated in circuit 4, αi S, -1-82 ("" Ml ) is calculated in circuit 5, and circuit 6 is Then, the intermediate information Mo, M, , M2 is (8
) is supplied to the intermediate information ratio calculation circuit 7 to perform the calculation corresponding to the equation. M 1/ of equation (8) in circuit 7
An example of a circuit for calculating M2y is shown in FIG. Bamboo shoots supplied: 25
It has 6 memory addresses, 1 for each memory address.
It has a capacity of 1 byte, but by storing the complement of b with the relationship A = αb in the memory address specified by an arbitrary binary number A, the above conversion from Mo to Ru. On the other hand, the supplied intermediate information Ml is converted by the read-only memory IJROM 41 into an index value t that satisfies the relationship Ml=αt. ROM41 is ROM4Q
By storing b in a memory address specified by an arbitrary 8-bit binary number A with a capacity similar to that of A and having the relationship A = αb, it is possible to perform the conversion Ml → t. can.

In this way, k obtained by converting MO-1 into an exponential representation and t obtained by similarly converting Ml into an exponential representation can be supplied to the MOD255 adder 44 and calculated in the same manner. For example, when calculating j〃, an exponent representation of M, -1 is required, but this is
Each pit of the index expression t of Ml is calculated by inverter 4.
It can be easily obtained by inverting using 3. and lROM
41, inverter 43, ROM42, and MOD25
Using the 5-Kashu unit 45, the exponential representation j of 2/M1 is obtained.

Thus, by the static arithmetic circuit of circuit 7 which does not use any clocks, from Mo, M, , M2, M1/M2/M
The exponential representations j', j'' of o'Ml can be obtained quickly and reliably.

(or j//) is sent to the correction execution control circuit 13 on line 1.
07.

The circuit 8 is a circuit that detects whether the supplied values of j' and j〃 match.

7), t8), (9J Equation-bj) As is clear, when there are two error symbols, the value of j corresponding to the error symbol position obtained as described above, that is, j' and j 〃 matches.

Therefore, in this case, circuit 8 will supply a coincidence output to correction execution control circuit 13 via line 110. At this time, two pieces of error number sub-information E1. The circuit that supplies Fi, 1 to the circuit 13 is incorrect - ffi information Fi, IJ calculation circuit 1
1 and perform the operation corresponding to equation 19) above? It is a circuit. That is, the intermediate information ratio calculation circuit supplies the calculation result of α'So+8+ (=Mo) converted into an exponential representation, and the syndrome storage circuit 3 supplies the calculation result to line 1.
B8 is supplied via 05, and intermediate information is also supplied,
Seven circuits are constructed from the syndrome calculation control circuit 2 to execute calculations.

A circuit example of the error information Ei, Ej calculation circuit 11 is shown in the sixth example.
Draw on the diagram.

The supplied shift clock number 1 is a read-only memory lJ
The ROM 51 converts the code vector (αi) from the exponential representation.
αAI=at memory address A for data A at t
The above conversion can be performed by storing the code vector B designated by Btr.

The ROM 52 is also a ROM similar to the ROM 51, and converts the supplied index code 4j/yoshi code vector (αj'). The code vectors αi and αj' are subjected to an operation of αi + αJ' by an exclusive OR circuit 55.

The ROM 53 is the same ROM as the ROMs 41 and 42 shown in FIG. 5, and converts the supplied code vector of αi + αj' into exponential representation.

Mo expressed exponentially from circuit 7 (=α1So + 8
s ) and αi + αj′, which is also expressed as an index, by MO
By supplying the signal to the D255 adder 57 and performing MOD255 addition, the exponential expression of Ej in equation (9) can be obtained.

In order to output this as error information Ej, the ROM
This is possible by converting from index representation to code vector using 54. The ROM 54 is the same as the ROMs 51 and 52. The error #壬 information Ei is obtained by adding the syndromes So and Ej supplied from equation (9) to the exclusive OR circuit 5.
6 and can be calculated.

In this way, the erroneous benshi information Ki and Kj are immediately calculated on the i output from the circuit 2.

Now, the aforementioned intermediate information MO, M1. M2 is supplied to the intermediate information all-zero determination circuit 9. This circuit 9 is Mg
, J, M2 is 101, an all-zero signal is supplied to the correction execution control logic circuit 13 via line 108.

Further, the intermediate information MO, Ml, and M2 are supplied to the intermediate information zero detection circuit 10. This circuit 10 includes Mg, M
I.

If even one piece of intermediate information 101 is included in M2, it is detected and its zero detection signal is supplied to the circuit 13 via line 109.

On the other hand, as described in tiff, syndromes 5o-63 are supplied to the syndrome all-zero determination circuit 12.

This circuit 12 covers all syndromes of 5o-83.
”, a syndrome all-zero signal is supplied to the circuit 13 via line 117.

Now, the correction execution control circuit 13 controls execution of error correction through the following control operations using the poet's force signal supplied as described above.

First, when the syndrome all zero signal is output to the output 117 of the circuit 12, that is, the syndrome So~S
3 are all 10", a signal indicating that there is no error in this code clock is output to the error flag output 200 for other poets. ≠≠≠; First, the syndrome calculation control circuit -83 At the time of the shift clock number i generated after the calculation, a signal indicating that the intermediate information MO, Ml, and M2 are all 101 is generated at the output 108 of the intermediate information all zero determination circuit 9 and is supplied to the circuit 13. 13 determines that there is a one-symbol error from the relationship in equation 1 [1]. Since the shift clock fii at the time of "hay" is at the position of the error symbol, the above 1 is sent to the error correction execution circuit 14 via the line 115k. supply to.

Moreover, the error number information E1 is nothing but the syndrome SO, as is clear from the relationship of the α9 formula. Since this So is supplied to the circuit 13, it is ### snow information Ei
The circuit 14 is controlled via line 113 to perform one symbol error correction. Further, in this case, a signal indicating that there is no error is outputted to the error flag output ronoku.

Next, the number of shift clocks 1 output by the circuit 2 described above is the number of symbols constituting the code block (here, the symbol BO
~32 of B31) For all the following positive values, the intermediate information all zero determination circuit 9 selects the intermediate information MO+
If a signal indicating that all M1 + M2 are "OI" is not output, it is determined that this code block has errors of two or more symbols, and the following operation is performed.

When the number of shift clocks 1 output from the circuit 2 is in the range of 1 described above, that is, any one value of 1≦i≦32, the intermediate information comparison circuit 8 outputs that the intermediate information ratios j' and j〃 match. is supplied via line 110, and the intermediate information zero detection circuit 10 sends a signal to the circuit 13 via line 109 indicating that the intermediate information MO, M, , M2 does not contain "0" at the above point in time. If supplied,
From the relationship in equation (8) above, it is determined that there is a two-symbol error 9. Then, the above 1 is used as the two error symbol positions.
and j′ (this can also be j), respectively, on line 115
, to the error correction execution circuit 14 via line 116.

Also, the error information Ei and Ej are error #=information Ei
.

Since they are calculated by E calculation circuits 11, they are supplied to the circuit 14 via line II3 and line 114, respectively.

In this case, a signal indicating that there is no error in this code block is output to the error flag output 200 as a result of correction of the two-symbol error.

Next, at the shift clock number i', a coincidence signal of j', j// is supplied from the circuit 8 via the line ISO, and at least one 101 When a signal indicating that j′ is included is supplied, the intermediate information ratio j′ calculated in the circuit
j/7 is completely meaningless.

That is, in order to perform the calculation of equation (8) in the circuit 7, conversion from code vector to exponential expression is executed by ROMs 40, 41, and 42 as shown in FIG. If it is "0", it is impossible to view the index table, and the memory addresses Mol of ROMs 40, 41, and 42 have meaningless index expressions C1 and C//, respectively.

Since the CIN is stored, their C/, C1
, C/// is used (7) intermediate information ratio jZ j
// also becomes completely meaningless.

Therefore, in this case, the number of shift clocks l′ and j
It is clear that ' does not indicate the error symbol position, and control is performed so that error symbol correction is not performed.

If none of the above-mentioned conditions of poet's power for one symbol error, poet's power condition for two symbol errors, and conditions of human power in the case of no error are satisfied, (1
1, (5), (6), (l), (8), and the relationship between equation α01, it is clear that the condition that the number of errors is 2 or less (including 0) does not hold true. Ru. Therefore, in this case, error correction is not performed, and a message indicating that an error is included in this code block is outputted to the error flag output 200.

Now, the error correction execution circuit 14 has a buffer for storing symbols B31°ΔB2O, . In the case of error correction of one symbol, the supplied error memory ↓ information E4 (SO ) is added using exclusive OR to perform error correction. Similarly, in the case of two-symbol error correction, for the symbols Bi, △ and BJ' at the positions specified by the error symbol position designation information i and j' among the symbols stored as described above, Error correction is performed by adding the supplied error number information E1 and Ej using exclusive OR. In the above embodiment, the code length N is 32. The number M of check symbols in a code block is 4, and the number of bits of each symbol is 8. Although the case in which a Reed-Solomon code such as the one shown in FIG. Further, the circuit examples for the 64 circuits used are shown as examples for realizing the circuits, and the present invention is not limited thereto.

As described above, when the present invention is used, one or two errors occurring in a Reed-Solomon code that forms one block of N symbols is corrected, and if three or more symbols are detected, an error flag is issued. In this method, it is possible to provide a highly reliable decoding method that effectively utilizes information on all syndromes of up to M test symbols and achieves the objective with a simple circuit configuration. This makes it possible to improve reliability and economy.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a diagram for explaining the sum operation used in this embodiment, and Fig. 3 (1) is a sign polynomial for the operation used in this embodiment. FIG. 3 (2) is a diagram for explaining the product calculation used in this embodiment. FIG. 4 is a diagram showing an example of the internal circuit of the syndrome calculation circuit of this embodiment. is a diagram showing an example of the internal circuit of the intermediate information ratio calculation circuit of this embodiment, and FIG.
Information Ei. FIG. 3 is a diagram showing an example of an internal circuit of an Ej calculation circuit. In 14, 1... syndrome calculation circuit, 2...
- Syndrome arithmetic control circuit, 3... Syndrome storage circuit, 4... Intermediate information MO arithmetic circuit, 5... Intermediate information J7 Tiger Corps Road, 6... Intermediate information M2 arithmetic circuit, 7
. . . Intermediate information ratio calculation circuit, 8 . . . Intermediate information hole comparison circuit, 9 . . . Intermediate information all zero judgment circuit, 10 .
, Ej performance 30.31, 32.33... Shift register, 21.22, 23, 24, 55.56... Exclusive OR circuit, 25.26, 27, 28, 29, 40, 4
1,42,51,52,53.54...Read-only memory (ROM), 44,45.57...2
Adder modulo 55 (MOD255 adder), 43
, 46...inverter. Patent applicant Shin Nippon Electric Co., Ltd. No. 2 A B AB Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] A Reed-Solomon code of code length N (where N is a positive integer greater than M) generated from a generator polynomial formed by the product of M (where M is a positive integer) first-order polynomials. is received and M syndromes S6, 81, . . .
..., s, -1 is calculated, and if one symbol error is detected in the received code based on the syndrome, the error is corrected, and if two symbol errors are detected, the error is corrected and the reception is performed. The code -゛ is output, and the previous syndrome So, sl,...l5M-1 is output for the three symbols.
intermediate information calculation means for calculating M-1 pieces of intermediate information determined by calculations set in advance; intermediate information all-zero determination means for determining whether each of the intermediate information is '()''; intermediate information zero detection means for determining whether at least one “0” intermediate information is included in the intermediate information;
M-2 intermediate comparison means based on the intermediate information, and detecting a one-symbol error according to a predetermined algorithm in response to symbol positions that can be generated by the intermediate information calculation means and the output of the intermediate information all-zero determination means. It is determined whether or not to perform correction, and if correction is to be performed, the symbol position corresponds to an erroneous symbol position, so that the syndrome So is erroneously determined for that symbol.
1-symbol error correction means for performing error correction as information; and 1-symbol error correction means for performing error correction as information; 2 according to the algorithm
Deciding whether or not to perform symbol error correction, and when performing correction! ! '] The seventh symbol position corresponds to one (1-)K of the two symbol error positions, and the output of the intermediate information ratio calculation means corresponds to the other one symbol error position (@
2-symbol error correction means for calculating error correction information to be used for error correction corresponding to ).