JP3071482B2 - Error correction circuit of packet receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction system used in a packet switching system for transmitting information such as data, voice and video signals in a packet form on a communication line without retransmission. It is.

[0002]

2. Description of the Related Art Conventionally, this type of packet switching system is used for transmitting a packet from a transmitting side to a receiving side via a packet switch. In this case, audio,
And an information signal such as a video signal, before the information signal,
A packet is formed by adding a packet header, and transmission is performed according to a non-high data link data control (HDLC) procedure. This packet header is used to specify the intended recipient. In such a system, since retransmission is not performed, it is necessary to ensure that a packet is received by a target receiving side. Otherwise, the information signal will be transmitted to the wrong receiver, which is undesirable. For this reason, the packet header must be transmitted more accurately than the information signal. Generally, for an information signal having a data length as short as several bits, use of a Hamming code or addition of a parity bit is considered. Thus, when the data length of the information signal is short, a single error or a double error can be corrected by using a Hamming code or a parity bit. On the other hand, the packet header usually has a long data length of several tens of bits, and it is not preferable to use a Hamming code or a parity bit. Further, packet switching systems are often used in noisy locations, so there are many opportunities for error correction. Considering this, it is considered desirable to be able to correct not only double errors but also multiple errors.

[0003]

However, conventionally,
In fact, no consideration is given to error correction of packet headers and correction of multiple errors.

[0004] Therefore, a technical problem of the present invention is to provide an error correction system which can be applied to a packet switching system and can correct various code errors. Another technical object of the present invention is to provide a packet transmitting apparatus which can transmit a packet header capable of correcting a multiplex error of two half bytes or more, and thereby does not transmit a packet to an erroneous receiving side. Still another technical object of the present invention is to provide a packet receiving apparatus which can correct a multiple error of two half bytes or more and can be realized by a small-scale circuit.

[0005]

According to the present invention, a packet is provided.
Packet header with an error correction code added to the
Is formed by the Reed-Solomon code, and
Packet data from the packet transmission device to which the
The packet header signal of the packet data
Error correction of the packet receiver that detects and corrects errors in the packet
Route, enter the packet header and
Calculate based on a predetermined expression defined for the code,
A syndrome operation circuit for outputting a number of syndromes,
The plurality of syndromes and the packet header
Register that stores each value of the packet header signal.
Output from the syndrome arithmetic circuit.
Enter multiple syndromes
Error in the packet header signal according to ROHM
Consists of an error detection circuit that detects the presence and a series of instructions
The error position of the packet header signal is detected and the
Storage circuit for storing an error correction program for correcting errors
And a plurality of registers by the plurality of gate means.
Connected to each other and based on the value stored in the register.
Performing the operations defined by the error correction program.
Number processing circuit and error correction program from storage circuit
Are read out sequentially and based on the contents specified in the program.
To open and close a plurality of gate means and process a plurality of arithmetic processing circuits.
Control instructions and control to control their timing
Means, and the error detection circuit detects an error
Activate the control means and store in multiple registers.
Of Error Location and Correction of Error in Packet Header Signal
Output of the packet receiver
An error correction circuit is obtained.

[0006]

According to the present invention, in a packet transmitting apparatus, a packet header is composed of a Reed-Solomon code, thereby enabling correction of a double error or more, while calculating a syndrome generated in the packet header in a packet receiving apparatus. The detection of the presence or absence of an error is configured by a hardware circuit, while the correction of the error is performed by a circuit operated by a microprogram, thereby enabling the processing of the Reed-Solomon code with a small circuit scale. .

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An error correction system according to one embodiment of the present invention will be described with reference to the drawings. 1 and 2 show a transmitting device and a receiving device used for an error correction method according to an embodiment of the present invention, respectively, and here, a case where each device is configured by a super LSI Is shown. In such an error correction method, data, audio and video signals are transmitted from a transmitting device as packet information signals, and the packet information signals are added to a packet header to form a packet, and the packet is transmitted via a communication line. Sending. In the packet header, destination information and the like regarding a target receiving device are arranged as a packet header information signal (hereinafter, simply referred to as a packet head signal).

More specifically, in the transmitting apparatus, a packet header is constructed by adding a redundant bit code (error correction code) for correcting an error of the packet header signal to the packet header signal. On the other hand, the receiving apparatus receives the packet header, and if there is an error in the packet header signal, corrects the error of the packet header signal with reference to the error correction code and outputs the corrected packet header signal as an output signal. . In this case, the packet header is a Reed-Solomon code RS (15, 11, 5), that is, the total symbol number (= 2 ⁴ -1); 15, the information symbol number; 11, the minimum Hamming distance; You are using Such a Reed-Solomon code can be generated using a polynomial having a maximum order of 14. The packet transmitting apparatus as a transmitting side shown in FIG. 1 is for transmitting a packet header composed of a Reed-Solomon code,
Through the packet header signal for each symbol, that is,
Using 4 bits (1 half byte) as one unit, a
5, a6, a7, a8, a9, and a10 are input in this order. Although a maximum of 15 half-byte symbols can be arranged in the packet header, the packet header in this example does not use 5 half-bytes of a0, a1, a2, a3, and a4, and a5, a6, a7, a8, a
Only the six half bytes 9 (and 24 bits) of a10 (that is, 24 bits) are set in the head information setting unit and supplied to the illustrated transmitting device. The transmitter is configured to send four half-byte error correction codes (r0, r1, r2, and r3) on output data lines 116, 117, 118, and 119. FIG. 3 shows a packet header transmitted from the transmission device. As is clear from the figure, the packet headers are a5, a6, a7, a
8, a9 and a10, a packet header signal;
16-bit error correction code r added after a10
It can be seen that it is composed of 0, r1, r2, and r3. The transmitting apparatus shown in FIG. 1 performs the algebraic arithmetic processing shown in Equation 1 to transmit an error correction code as shown in FIG.
03, 104, exclusive OR circuits 111, 112, 11
3 and 114, as well as first to fourth registers 106, 107, 108 and 109.
Here, the special multipliers 102, 103 and 104 assign different weights α to the symbols of the respective packet header signals.
¹² , an arithmetic unit for multiplying α ⁴ and α ⁶ , and first to fourth registers 105, 106, 107 and 108
Is for temporarily latching a 4-bit symbol. The illustrated transmitting device can perform the operation shown in Equation 1, and as a result, the output data lines 116, 1
Error correction codes r0, r from 17, 118, and 119
1, r2, and r3 can be transmitted.

[0009]

(Equation 1)

On the other hand, as shown in FIG. 4, the receiving device receives the transmitted packet headers a5 to r3, performs a decoding process, and receives the received packet headers b5, b6, b7, b8,
After obtaining b9, b10 and redundant bits (hereinafter referred to as reception error correction codes) t0, t1, t2, and t3, these received packet headers b5, b6, b7, b8, b9,
b10 is replaced with the reception error correction codes t0, t1, t2, and t3.
, An error correction process is performed, and b′5, b′6, b ′
7, b'8, b'9, and b'10 generate corrected packet headers.

Referring to FIG. 2, a packet receiving apparatus used in an error correction system according to one embodiment of the present invention will be described. Received packet header signals b5, b6, b7, b8,
b9, b10 and received error correction codes t0, t1, t2,
And t3 are input to the syndrome operation unit 21 as a received packet header, while the received packet header signal is stored in the registers b5 and b of the 4-bit register group 26.
6, sent to and stored in the registers b7, b8, b9, and b10. The syndrome calculation unit 21 is configured by a hardware circuit, and firstly, d0, d1, d
2, and d3 are obtained by algebraic processing, and then the syndromes S0, S1, S2, and S3 are calculated. Since it is easy for those skilled in the art to configure such an arithmetic circuit by a hardware circuit according to Equation 2, the description is omitted here.

[0012]

(Equation 2)

The syndromes S0, S1, S2, and S3 are sent to an error determination unit 23. Upon receiving the syndromes S0, S1, S2, and S3, the error determination unit 23 determines whether or not an error exists in the received packet header. 27 and a processing cycle generation unit 28. Here, the error determination unit 23 is also configured by a hardware circuit, like the syndrome calculation unit 21. As a result, the program counter 27 sends the count signal to the ROM 29 as an address signal.

The ROM 29 stores an error correction program (microprogram) formed by a series of instructions. Each instruction is sequentially read from the ROM 29 and sent to the first to fourth decoders 31 to 34. The first to fourth decoders 31 to 34 supply the decoded signals to the timing controller 36 controlled by the processing cycle generator 28 started by the error detector 23. In this example, the first decoder 31 is used to decode the order part of each instruction, while the second to fourth decoders 32 to decode the operands represented by X1, X2, and X0 described later. Used for

The timing control section 36 generates first to third gate control signals indicated by A, B, and C, and
The latch signal LA is sent to the register group 26, and the jump address signal JP is sent to the program counter 27. In this case, the jump address signal JP indicates the address of the ROM 29 to be jumped. The elements 27, 28, 29, 31 to 34 are controlled by a program, unlike the elements 21 and 23.
Further, the processing cycle generation unit 28 includes the timing control unit 3
6, an error correction processing cycle signal for error correction processing is output. With this configuration, the Reed-Solomon code can be processed by a small-scale circuit.

In the example shown in FIG.
The I, F, K, L, R1, R2, and R3 registers are provided, and these registers perform the operations described below with the registers S0 to S3 and b5 to b10. Registers I, F, K, L, R1, R2, R3, S0 to S3, b
5 to b10 are connected to the first and second buses 41 and 42 via gates indicated by A and B in the form shown in Table 1.

[0017]

[Table 1]

For example, the first to fourth syndrome registers S0 to S3 are connected to both the A and B buses through gates. Further, the first and second syndrome registers S0 and S1 are not connected to the C bus 43, but the third and fourth syndrome registers S2 and S3 are connected to the C bus 43. In any case,
These syndrome registers S0 to S3 serve to store the first to fourth syndromes. Third and fourth
Are used as work registers. Similarly, the registers b5 to b10 are connected to the A bus 41 and the A and C buses 41 and 43, but are not connected to the B bus 42. These registers b5 to b10 are used to store the received packet header or the corrected packet header. The I register is a register for storing an error position signal indicating an error position, while the F register operates as an index register when a specific order, for example, LF or LFR is transmitted. Further, the K and L registers are registers for storing constants, and the R1 to R3 registers operate as work registers.

Still referring to FIG. 2, the receiving device shown includes an operation conversion memory (ROM) 46, a ROM access unit 47, an exclusive OR unit 48, a load unit 49, and a comparator unit 50. . These are all configured by hardware and collectively constitute a processing circuit for processing the received packet header. As shown in FIG.
The ROM access unit 47 and the exclusive OR unit 48 are connected to the A and B buses 41 and 42, and are also connected to the C bus 43 via C gates C1 and C2. On the other hand, the load unit 49 and the comparator unit 50 are connected to the A bus and the C bus as illustrated. The corrected packet header signals b5 'to b10' are output from the registers b5 to b10 in an error-corrected form.

As described above, the receiving device can be divided into a logical operation unit such as the syndrome operation unit 21 and the error determination unit 23, and another microprogram control unit.

The operation conversion ROM 46 stores operation conversion microprogramming for error correction processing. The ROM access unit 47 receives a register content signal from the 4-bit register group 26, and
By accessing and reading the error correction processing conversion microprogramming with the OM 46 via the address line, the error correction processing conversion code is converted to C1.
Output to bus gate. On the other hand, when receiving the gate control signal from the timing control section 36, the C1 bus gate outputs an error correction processing operation conversion code to the C bus 43.
The exclusive OR unit 48 also controls the 4-bit register group 26
Receives the register contents signals via output data lines, performs an exclusive OR operation of these register contents signals, and outputs an exclusive OR operation result signal to the C bus 43 via the C2 bus gate. I do. Loading unit 49
Receives a register content signal from the 4-bit register group 26 via the A bus 41 and
And outputs a load signal to the C bus 50 via the C3 bus gate. The comparator unit 50
While receiving register contents signals from the 4-bit register group 26 via the A bus 41, receiving code constants from the timing control unit 36, comparing these signals, and outputting a comparison result signal to the C bus 43 via the C4 bus gate. Used to As a result, the 4-bit registers S2, S3, b5, b6, b7, b8, b of the 4-bit register group 26
9, b10, I, F, K, L, R1, R2, R3 are C
An error correction processing conversion code, an exclusive OR operation result signal, a load signal, and a comparison result signal are received via the bus 43, and error correction processing is performed by an operation described later.

Table 2 is stored in the ROM 29,
In addition, orders and operands used in the microprogram for detecting and correcting an error position are listed.

[0023]

[Table 2]

The 17 orders shown in Table 2 are the ROM access unit 47, the operation conversion ROM 46, and the exclusive OR unit 4.
8, is sent to the load unit 49 and the comparator unit 50 as described later. Here, each order instructs the operation shown in the meaning column, and X1, X2, and X0 represent values on the A, B, and C buses 41, 42, and 43, respectively.

The error correction operation will be described with reference to FIGS. Such an error correction operation is performed in the first step 20.
Starting from 1 according to the microprogram stored in the ROM 29. In the second step 202, the exclusive OR of the square of the syndrome S1 and the product of S0 and S2 is calculated using the exclusive OR unit 48, and the result of the exclusive OR is compared with 0 by the comparator unit 50. Is done. If the result of the exclusive OR is equal to 0, it is determined that a single error has occurred, and the operation shifts to a single error correction operation.
If not, it is determined that a double error has occurred, and the operation shifts to the correcting operation.

The operation for correcting a single error is performed in the third step 203.
As shown in the figure, the result of the division represented by S1 / S0 is
Start by populating one register. The division result at this time is represented by a vector expression.
In step 203, the contents of the R1 register are converted into a power expression. This conversion is performed using the ROM access unit 47 and the ROM 46 for calculation conversion. Further, an error position U is obtained by subtracting the converted value from 14. Where 1
Reference numeral 4 denotes the degree of the polynomial used when generating the Reed-Solomon code. In the fourth and fifth steps,
It is determined whether or not the error position U is between 5 and 10, that is, whether or not there is an error in the received packet header signal. If not, the process ends. On the other hand, when the error position U is between 5 and 10, the exclusive OR of the symbol at the position of U and S0 is calculated to find the corrected bi, and rewriting is performed using this bi.

On the other hand, in the case of double error correction, 0 and 5 are set in the F and I registers, respectively. In this case, the contents of the F register indicate the number of errors, and the contents of the I register indicate the position where the error should be detected. In the seventh step 207, the operation shown in the block 207 of FIG. 5 is performed, and the result is stored in the K register. This calculation is performed according to the algorithm in the Reed-Solomon code. In an eighth step 208, the power I of the alpha is converted into a vector representation and is stored in the R2 register. Next, the square of R2, the product of K and R2, and the exclusive OR of the L register are calculated, and the result is stored in the R2 register. In the ninth step 209, R2
The contents of the register are compared with 0, and if not 0, ie
If there is no error, the process proceeds to the tenth step 210. In a tenth step 210, the error detection position I is compared with 10, and if it is not equal to 10, the process proceeds to an eleventh step 211, where the position of I is incremented by one,
8, the same operation is repeated. Tenth step 21
If the value of I is equal to 10 at 0, the process proceeds to a twelfth step 212, where it is determined whether or not the content of the F register is 0. If the content of the F register is 0, the process ends as there is no error.

If the content of the R2 register is 0 in the ninth step 209, the content of the F register is incremented by 1 in a thirteenth step 213, and then the content of the I register is subtracted from 14 in a fourteenth step 214. And
The error location is stored as R (F). Next, it is determined in a fifteenth step 215 whether or not the content of the F register is equal to two.
If so, the operation of the tenth step 210 is performed.

If the content of the F register is equal to 2, the first
6 In step 216, after the error position is detected,
An error correction operation as shown in step 217 is performed, and subsequently, in an eighteenth step 218, it is detected whether or not the content of the F register is equal to one. If it is equal to 1, bi is rewritten as shown in a nineteenth step 219, thereby correcting the error. Also, the eighteenth
In step 218, if the contents of the F register are not equal to one, as shown in twentieth step 220,
After the contents of the I register are transferred to the F register, the operation of the sixteenth step 216 is performed. In this way, double errors are also corrected in this embodiment.

The error correction code according to one embodiment of the present invention is composed of a dedicated assembler code.

[0031]

As described above, according to the error-correctable transmission / reception system of the present invention, error correction processing of 2 bits or more is enabled, and even if an error of 2 bits or more occurs in the packet header to the receiving side. This has the effect that this can be corrected.

[Brief description of the drawings]

FIG. 1 is a block diagram of a packet transmission device used for an error correction method according to an embodiment of the present invention.

FIG. 2 is a block diagram of a packet receiving device used for an error correction method according to one embodiment of the present invention.

FIG. 3 is a diagram showing a packet header transmitted from the packet transmission device of FIG. 1;

FIG. 4 is a diagram illustrating a packet header received by the packet receiving device of FIG. 2;

FIG. 5 is a flowchart for explaining an error correction processing operation in the error correction type packet receiving apparatus according to one embodiment of the present invention.

[Explanation of symbols]

 In FIG. 1, 111, 112, 113, 114 exclusive OR circuit 101 input data line 102, 103, 104 special multiplier 106, 107, 108, 109 4-bit register 116, 117, 118, 119 output data line , 21 syndrome operation unit 23 error determination unit 27 program counter 28 processing cycle generation unit 29 ROM 31, 32, 33, 34 decoder unit 36 timing control unit 26 4-bit register group 41 A bus 42 B bus 43 C bus 46 Operation conversion ROM 47 ROM access unit 48 Exclusive OR unit 49 Load unit 50 Comparator unit

Continuation of front page (56) References JP-A-61-3528 (JP, A) JP-A-1-202947 (JP, A) JP-A-62-105554 (JP, A) JP-A-59-79658 (JP) , A) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H04L 11/20

Claims (1)

(57) [Claims] 1. A packet header in which an error correction code is added to a packet header signal is formed by a Reed-Solomon code, packet data from a packet transmitting apparatus to which the packet header is added is received, and a packet header of the packet data is received. In a packet receiver error correction circuit for detecting and correcting a signal error, the packet header is input, the packet header is operated based on a predetermined expression defined for the Reed-Solomon code, and a plurality of syndromes are output. A syndrome operation circuit; a register for storing a value of each of the plurality of syndromes and a packet header signal of the packet header ;
Register consisting of multiple registers for detection and correction operations
And group data, inputs a plurality of syndromes said syndrome calculating circuit outputs, an error detection circuit for detecting the presence or absence of an error in the packet header signals according to the plurality of syndromes, individual processing logic of error detection and correction operation a storage circuit for storing <br/> error correction program for defining the execution of the process of correcting the error by detecting an error position of the packet header signal by combining a set of instructions defining a plurality of gate means individual registration of the register group through
Is connected to static, the value stored in the register store
Based on Luo beforehand set calculation converted data, the processing logic each instruction of the error correction program defines hard
A plurality of arithmetic processing circuits executed by hardware logic; and sequentially reading each instruction of the error correction program from the storage circuit, and performing error detection and correction operations specified in the instructions.
Based on the contents of the arithmetic processing logic , the plurality of arithmetic processing
Command to execute the process on the road
Open and close the plurality of gate means to execute the instruction
And control means for forming a logical circuit necessary for the error detection circuit starts the control means and detecting an error, the presence and the error position of an error in the packet header signal stored in the register group Detect the error
Follow the processing logic specified for each instruction of the main program.
Error detection of said register group and said plurality of arithmetic processing circuit Te
And a plurality of registers for correction operation,
An error correction circuit for a packet receiver, which corrects and outputs an error in a packet header signal .