JPS613528A - Error correction circuit - Google Patents

Abstract

PURPOSE:To simplify the system constitution by adopting the hardware constitution to a code generation and syndrome operation having many repetitive processings and constituted with a simple circuit and adopting the software constitution for error pattern and error position calculation becoming complicated in the hardware constitution. CONSTITUTION:A digital information word group is arranged in a matrix, an error check bit is given in row and column directions and a circuit correcting an error is provided with circuits 57, 58 generating an error check bit, syndrome calculation circuit 59 and a memory 510 storing a bit and a calculation syndrome. Further, the 2nd memory 515 storing the 1st and 2nd programs executing a syndrome, code generating circuits 57, 58, a syndrome calculation circuit 59 and the 3rd memory 517 storing a program controlling the 1st memory are provided. Thus, the control of each memory is executed by microprocessors 516, 517, the hardware and software constitution are adopted to simplify the system.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to an error correction method performed on a Galois field GF(2''), and particularly relates to a method for error correction using a double encoding structure having an inner code and an outer code. [Prior art and problems] The Reed Solomon coding method is well known as a method with the highest correction ability among error correction coding methods.This method uses a Galois field cF(q
), and if q=2, the Galois fundamental field CF
It is encoded by the layer-order extension field CF(2'') derived from (2). Here, we will briefly explain the Calois field. The virtual root α that satisfies
When considering q = 211 different elements (0, 1, α
, α2. ...α surprise Q) constitutes the extension field CF(2”) of the Galois field CF(2). In this case, (!ship -ri-(!-0)(touw-t-1) is GF( 2
”), but the remaining elements (1, α, α2...α%Q) after removing the 0th order from this Galois field are elements of (, %4 = l). , (X%4-1) becomes a cyclic polynomial. In this way, 0F(2”) becomes GF(2)
It is a polynomial ring modulo the first-order irreducible polynomial P (violet) over . Here, α is called a primitive element, (iF(2
) is called a primitive polynomial if it has a primitive element of GF(2") as a root. (, v+ -1) has the element (1, α, α2, ... α village ) as roots, so it can be expressed by the following formula: (,14-1)=υX-αi ) (
+) 1m. Now, if the root of the primitive polynomial p(ri is α), then CF(2 lines)
The elements of are linear combinations (a, 1l-1--' 4p・-+Bl!+ flo
), so 0F(2”) is 0
It can be expressed as a vector (am-+ s...at +aO) on F(2). On the other hand, − Yuan (
! , α, C2, ...0 grains) form a cyclic group of order (2"-1), and these can be expressed as powers of the primitive element α. Using the above principle, any information can be When an error occurs in word U, it is possible to generate code word C at an inter-code distance d that allows the error to be corrected or detected. The inter-code distance d is the corresponding position of code word vectors CI and CJ. The number of mutually different components among the components in C
1. It is called the Hamming distance between CJ. Error correction and detection capabilities depend on this distance. The larger the distance d, the higher the probability that the two factors C1 and CJ can be distinguished. In other words, if C1 and Cj define the range t of variation caused by errors, and the received word C' falls within the range of either C1 or CJ, it can be estimated that the codeword is correct; If the distance is sufficiently far, the estimated value will be close to the true value. Generally, when d≧2t+1, error correction of t symbols and up to 2 error detection are possible. Error correction on the Galois field CF (28) will be explained using the above principle. First, generation of code word C(x) will be described. If we take the information word U(1), the generator polynomial 〇(ri), the code length n, and the information length, then the code word C(ri is C(ri, υ(ri, !r divided by G(ri). Then, add the surplus R(ri). Now, when the intersymbol distance is d=4, let us give the generator polynomial as the following formula: C(x)=6(tαi)・( x-IM!-α)(!-α
2)"=x3+a""x2-'+alQqx+a3(t
sod', C8+ a' + C3+ C
2+1) (3) In this case, a concrete example of a circuit for calculating R(ri) is shown in FIG. 1. Here, 1 is the vector al of the information word u4 on CF(2) = (a71... , ao), and the information word ul in this register 1 is (Oh-+, 1jh
-U, . . . J, Uo, 0,09O). 2-0~2-7.3-0~3-7.4-0~4-7 is 5
od2 addition, i.e. exclusive off circuit, 5
7 is an 8-bit register, and is a coefficient multiplier that multiplies the outputs of the exclusive off circuit groups 2-0 to 2-7.3-0 to 3-7.4-0 and 4-7. , this is R
It can be easily realized using OM or PLA (programmable logic array). Exclusive off circuit 2-0~2-7.3-0~3
-7.4-0 to 4-7, registers 1 and 5, respectively.
．． Find the exclusive OR of the contents (al), (ro), (rt) of 8 and the outputs of coefficient multipliers 8, 9.10 (rz ・α3), (r2 fist αAQ), (rz, αIQ9) . For example, if the constant α191 is the value of rz (rz) =
Multiplication when a”3 is included is performed by the following matrix operation. From Fig. 1, the residual disease polynomial can be found as R(x) = r, , x2 + r1.x + r6. Next, If we define the parity check matrix H in decoding, the syndrome S for error correction/detection is given by the following equation. Here, Ce is a codeword vector containing an error, and E is an error vector. Here, )l@C=0, so it can be seen that the syndrome Ski is determined only by the noise sequence of the communication system.When the check matrix H has three check words corresponding to the above generator polynomial 〇(x), , A concrete circuit for determining the syndrome S is configured as shown in Fig. 2, for example.Here, 11 is the received code word Cj
This is a register that stores the vector (a?,...,ao) of the received code word Cf is (Cn-1"IW'...
・Cs +C'o,) is input to the register 11 in the sequence. 12-D to 12-7 are exclusive off circuits whose outputs are stored in 8-bit registers. 14 is a coefficient multiplier that multiplies the contents (r) of the register 13 by α. Exclusive off circuit 12-0
~12-7, the contents of register 11 (a7..., a
o) and the output (r·α)) of the coefficient multiplier 14 is calculated. Syndrome S is found on register 13 as CI=O. l, 2). In this example, there are only three syndromes, so generally only one error can be corrected, but if the error position of the received code word C'(i) is known by some means, then in this case Only three errors can be corrected. Now, the received code group (α-1+C to 2...C; , Go
), the three error positions are LJ+k, and the error pattern is @1゜ej +I! If it is given, it will be given. If the position of W4 is known, the error pattern can be obtained from the following equation. Therefore, CB -C'l +el C, -C, +@j CI (up to three errors can be corrected by adding +lik to -c'. If the error position is unknown, from equation (8), error position i and Only the error pattern e1 can be found. Figure 3 shows the encoding structure, with information words (■
h−+−Us +UO) and the test word (Pt, Po)
constitutes an inner code, and information words (υv-1...Us
, Uo) and check words (P2, Pt, Po) constitute an outer code. The generator polynomial 〇(riha) is given for the inner code and the outer code. At this time, in the row direction and the column direction, the code word C (riha is given by Code words (υ1.-1...ul, υ., Pl,
(Po), one word error is corrected, an error flag is attached to each line that could not be corrected, and then the address of each line with an error flag is set as the error position by the outer code for each column. Correct up to three errors. In the inner code, the syndrome S is given by the following equation. The error position in the code word C (violet) is i, and the error pattern is e.
If l, S6 *el, Sl-a'-e5, a'-81
−/So (11), the power i of the primitive element α is the error position, and S is the error pattern. Therefore, the error is corrected from C1=CI+J. Here, (!j□ −0, Sl #0)−(So″R,
Os Ss -0) and (i)n-1), it means that there are two or more errors in the code word in that row,
An error flag is attached to the line as uncorrectable. After error correction for each row is completed, up to three errors are corrected for each column using the outer code. In this case, error position 1+J+' has already been given as the row address that could not be corrected using the inner code. Therefore, the error pattern ei +eJ +ek for each column can be calculated from equation (7), and the syndrome of the outer code is given by equation (5). Next, the general rules for operations in equations (?) and (11) will be described. αi+αj is an addition of od2 when the elements αl and αj are expressed as vectors, and can be realized by an exclusive OR circuit. On the other hand, αtg is the power of element α' + mo of j
This is addition/subtraction in d255, and can be realized with a decimal addition/subtraction circuit, but when Ami+j≧255, A=A-255 A=i-j (when 0, A=255-A. Also, αI, When either αj is 0 element, αtt3yo0 must be set.Syndrome so, s, J! and error position 1.j
. Depending on the calculation content, vector conversion and exponentiation vector conversion are performed, and modulo 2 addition is performed, and α1゜αj is ++J
is converted to a vector power and the modulo 255 addition is performed. As described above, although code word generation and syndrome calculations as in equations (2) and (5) involve a lot of repetitive processing, the circuit configuration is simple. Regarding this, it can be seen that implementing on a circuit an operation that needs to be calculated using a power of the primitive element α becomes quite complicated in terms of circuit scale and processing sequence. Therefore, if all these calculations are implemented using /1- code, the overall circuit configuration will become complicated. On the other hand, if all these calculations are implemented using software, the overall processing will be complicated due to the many repetitive operations. Speed decreases.

[Purpose of the invention]

Therefore, in the present invention, the frequency of requiring complicated processing such as calculation of error patterns and error positions is extremely low compared to code generation and syndrome calculation.

[Structure of the invention]

In order to achieve such an objective, in the present invention, the codeword generation and syndrome operations, which involve a lot of repetitive processing and can be configured relatively easily using only logic circuits and registers, are configured using hard circuits and are operated using powers of one element. The calculation of necessary error patterns and error positions is appropriately configured to be processed on a microprocessor program. 7 In other words, the present invention performs the first error correction on the inner code of a code word group configured to allocate an inner code in the row or column direction and an outer code in the column or row direction of the information word group. , an error correction circuit configured to correct errors that cannot be corrected with the inner code using the outer code, a circuit for generating code words for the inner code and the outer code, and a syndrome for the inner code and the outer code. a syndrome calculation circuit that calculates a syndrome, and a first syndrome calculation circuit that temporarily stores the generated code word and the calculated syndrome.
a memory; a first program for detecting error pattern positions and correcting errors in the inner code according to syndromes of the calculated inner code; and detecting error patterns and correcting errors in the outer code; a second memory that stores a second program to be executed according to the syndrome; a third memory that stores a program that controls the code generation circuit, the syndrome calculation circuit, and the first memory; controls the second and third memories, controls the code word generation circuit and the syndrome calculation circuit, and controls the first and second memories;
It is characterized by comprising a microprocessor that controls program execution. [Embodiment 1 of the Invention] Examples of the present invention will be described in detail below with reference to the drawings. FIG. 4 is a system configuration diagram showing an embodiment of the error correction circuit according to the present invention. Here, 51,53°55.51
1 is a three-state bus driver and a pass transceiver; 52, 54, and 518 are latch circuits;
8 is an and gate. 57 is a row direction check word generation circuit, 58 is a column direction check word generation circuit, and 59 is a syndrome circuit, which will be described later in FIGS.
As shown in the figure, it can be configured in the form of hardware. 51O is a buffer memory, 5!2 and 513 are multiplexers, and 514 is a counter. 515 is a ROM (read-on memory) in which microcodes for generating control signals for each part of the hardware including the check word generation circuits 57 and 58 and the syndrome circuit 58 are written, and 51B is the entire error correction circuit in the present invention. A microprocessor 517 executes a program for controlling and calculating error patterns and error positions, and 517 is a ROM that stores the program, that is, the calculation procedure of equations (7) and (11). ! i is a CPU bus, and 51111 is a command/status signal line. First, a configuration example of a hardware circuit that generates the code word of equation (8) will be described. When the microprocessor 516 receives a codeword generation command from an external device (not shown) via the bus transceiver 51 via the command/status signal line 519, the entire system is set to codeword generation mode and the command from the external device is set to the codeword generation mode. Data (no~D7) is clock CK2
is taken into the latch circuit 52 by. This data is supplied to the buffer memory 510 via the bus driver 55 and sequentially written to addresses designated by the address control signal ADC from the multiplexer 513. On the other hand, the same data is passed through the AND gate 5B to the remainder polynomial Rs (test word (P
Data in the direction of the 0th row (Oh-+,...U, ■0) is input to the check word generation circuit 57 in order to calculate
) is being input, the output enable signals 〈 and 〉 of the latch circuit 52 and the bus driver 55 are in a low level state, and the gate signal CG of the AND gate 56 is in a high level state. When the input of the digital signal u0 is completed, 0EI3 and OF2 become high level, and the gate signal CG becomes low level. Data to the test word generation circuit 57 (Uh +...u, +
When inputting the test word (Pl, Po
) is the latch circuit 57 shown in FIG.
It is found on 06.5705. This test word (Pl, Po
) is written to the address of the buffer memory 510 specified by the ADC signal. The above operation is performed for all row numbers (ma 1, ma 2, . . . mao, ma 0). When the code word generation in the row direction is completed as described above, the column number (k
-1) The data (Uv, = Ut. Uo) are sequentially read out via the bus driver 54 and the AND gate 56 to calculate the check words (Pt, Ps, Po) in the column-direction remainder polynomial RV (multiple). It is input to the test word generation circuit 58. During this time, ml of the latch circuit 54 is at a low level, and the latch circuit 52, bus drivers 53 and 55, and OH2 and OH2 of the AND gate 5B. OF2 and CG are in a high level state, and when the input of V pieces of data is completed, that is, data mark 0 has been input, the frame becomes a high level and CG becomes a low level state, and the check word generation circuit 58
data (Uv-+, -, U+, Uo, 0.0.0
), the test word (Pt, Pt, Po)
is the latch circuit 5809 of the check word generation circuit 58 shown in FIG.
．． It is found on 5808 and 5807. This test word (Pt
, Pt, Po) are written to the address of the buffer memory 510 specified by the ^DC signal. The above operations are performed using column numbers (h-1, h-2, ..., 1.O
, and inner code check sequences), and the code words shown in FIG. 3 are arranged on the buffer memory 510. Next, the microprocessor 51B converts the path transceiver
Handshaking is performed with an external device via the buffer memory 51, and data (Uh-+, . . .
, Ut , Uo +Pt *'O) as bus driver 5
3 and the latch circuit 54 to an external device. At this time, the number is low level OE2. OE9 is in a high level state. As a result of the above, the data (h+2) on the buffer memory 510
) The code word generation mode ends when all (ma ÷ 3) pieces have been transferred. Next, hardware processing for error correction in equations (11) and (7) will be described. When the microprocessor 516 receives an error correction command from an external device via the path transceiver 51, the entire system is set to the error correction mode, and data (Do to Dt) from the external device is taken into the latch circuit 52 by the clock CK2. It will be done. This data is transferred to the buffer memory 51 via the bus driver 55.
They are sequentially written to the addresses specified by the ADC signal of 0. On the other hand, the same data (no~D7) is data in the 0 row direction (Ilh-+, ``' , U+ , Uo +P1
, po ) are at input level, OH2, OH2 are low, m, tyrt, cc are at high level. After entering the last data PO, the syndrome (St
, So) are the latch circuits 5908, 599? of the syndrome circuit 58 shown in FIG. Since it is found above, this (Sl
. So) Write to the address specified by the ADC signal of the rubber rear memory 510. The above operations are performed using the line numbers (Mar 1. Mar 2..., l, 0)
and outer code checking). Next, in order to perform the syndrome in the column direction, the column number (
h-1) (7) Data (Uv-+, ..., IJ+
, Do +P2. P, +PO) are sequentially read out, and the syndrome circuit 5 is used to calculate the column direction syndrome (S2°St, 5(1)) according to equation (5) via the latch circuit 54.
Data in the 0 column direction input to 9 (Uv-+, -, IJ
+, 00, P2゜Pl, po) Power input level fill, ots, otz, ots, cc hum level,
The rice field is in a low level state. After inputting the last data P in the column direction, the syndrome (
S2 +SI +SO) is the latch circuit 59°0 in Figure 5.
11.5908.590? Find above. This syndrome (S2 +SI +SO) is written to the address specified by the AlIC signal in the buffer memory 510. The above operations are performed for all column numbers (h-1, h-2, . . . 1.0 and inner code check columns). When the syndromes for each row and column in the code word structure shown in FIG. The software begins calculation processing. To do this, the output enable signal OE[l of the bidirectional path transceiver 511 is brought to a low level state. First, in order to perform error correction in the row direction, the microprocessor 516 transmits the syndrome C5+, So) of the corresponding row from the address of the buffer memory 510 specified by the address signal Addr for each row to the pass transceiver 511.
The syndrome (S
l, So) into a power expression α11°α10, and calculate αl=α11to using equation (11), thereby specifying the error position i (-Sho1-Kaku.) in the corresponding line. This identified error position i is made into an address signal Add r and is supplied to the buffer memory 510, the code word Ci is read from the corresponding address, and the C! and So indicating the error pattern, and write the result to the same address in the buffer memory 510, thereby correcting one word in the corresponding line. In this embodiment, only one word can be corrected in the row direction, so for errors of two or more words, the microprocessor 51B corrects (So "0.St"-=Q) for each row. (S6 #0. Sl =0), (i) h-1+2
) When any of the conditions is satisfied, the corresponding line is stored as an error flag for the corresponding line. After completing the above processing for all the rows in FIG. 3, the microprocessor 51Ei next performs error correction in the column direction.
Syndrome (Sz, St J
O) is taken out via the path transceiver 511, and the error pattern of equation (7) is calculated while converting the vector expression to the power expression or vice versa as described above. Here, (j, j, k) is the address of an uncorrectable error row stored as an error flag as described above, and if these rows exist in four or more locations, it is no longer possible to correct them in the column direction. Thus, the entire code word of FIG. 3 is in an uncorrectable state, and upon this detection, microprocessor 516 notifies external equipment of this state via path transceiver 51. If there are three or less error lines, all of them can be corrected, and the error position (i, j, k) is expressed as a power of α, α1,
αj and α are shown. When the error pattern is calculated according to equation (7), the microprocessor 51B gives the error row (i, j, k) as an address to the address signal Addr, and stores the data 'Ci + Cj * C' k at that address in the buffer memory. Read from 510, ei, 8J+l! Exclusive OR is performed and each result is stored in the buffer memory 51.
By writing 0 or more to the same address as above, error correction up to 31s of the month is completed. After completing the above processing for all columns in FIG.
Among the error-corrected code words formed on the buffer memory 510 by handshaking with an external device via the
Addressing only the information word with the ADC signal, data (υh-1,...UI.tlo) is passed for each row to the transceiver 53 and the latch circuit 5.
4 to an external device. The processing in the microprocessor 51B is given by the program ROM 517, and the conversion between vector representation and exponentiation representation is possible by creating tables of 255 bytes each in advance in the case of 0F (2B), and by simply referencing the Can perform conversions. Further, since the processing of equations (7) and (11) can be realized using only decimal number addition instructions and logical operation instructions, it can be realized only with instructions that have a relatively fast processing time. Note that the test word p2. p1
．． p, and syndromes S, , S, , So are controlled by control signals SHV, PV, PH, OF3. OF2,0E5(
The contents of one register are written to the buffer memory 51G depending on the state shown in FIGS. 5 to 7). The SEL1 and sgL300 signals provide direction control for bidirectional path transceivers 511 and 51; the SEL2 signal provides line selection for multiplexers 512 and 513. SAD is the count initial value supplied to the counter 514 corresponding to the start address of ROW 515, and the input is the load signal, WRI, R[+1 and l1lR2, RD2
are a write signal and a read signal corresponding to the Add r signal and the ADC signal, respectively, and any set of these signals is selected by the SEL2 signal and taken out from the multiplexer 512 as a write signal i and a read signal dwarf, and is sent to the buffer memory. Add to 510. A that controls circuit control signals such as data transfer between external devices and the buffer memory 5!0, code word generation, syndrome calculation, etc., and address control of the buffer memory 510;
The DC signal is preset in the microcode R[1M515, and when the counter 514 starts operating in response to a command from the microprocessor 51B, ABC and control signals are generated from the ROM 515 and transmitted through the latch circuit 518 to the above-mentioned signals. performs circuit control. (Left space below) The syndrome circuit 58 can be configured as shown in FIG. 5, where 5901, 5902, and 5903 are arithmetic circuits configured as shown in FIG.
4 to 5909 are latch circuits, 5810 to 5812 are Nant gates, IJc and IJS are latch circuits, and IJc and IJS are latch circuits.
04 to 5909 +7) Clock, general is latch circuit 5
Clear signals to 804 to 580B, SHV are syndrome calculation processing mode designation signals, OE3 to OE5 are output enable signals, and these various signals are stored in ROM5.
15 through a latch circuit 518. The above-mentioned arithmetic circuit, for example 5803, has exclusive OR circuits 71 to 84 arranged as shown in FIG.
~P27, the calculation of vector (r)=vector (9+vector (α1.α2)) is performed in FIG. The other arithmetic circuits 5301 and 5802 can be similarly configured. The column-direction check word generation circuit 58 is configured as shown in FIG. Here, 5801 to 5803 are arithmetic circuits that can be configured with exclusive off circuits like the above-mentioned arithmetic circuit 5303. 5804 to 5808
is a latch circuit, 5810 to 5812 are Nant gates, a pv is a designation signal for the column direction check word generation processing mode, and the row direction check word generation circuit 57 is connected from the ROM 515 via the latch circuit 518 as shown in FIG. Here, 5701 and 5702 are arithmetic circuits that can be constructed from exclusive off circuits like the above-mentioned arithmetic circuit 5803. 5703-570B are latch circuits, 5707 and 57
08 is Nantes Gate. P is a designation signal for the check word generation processing mode in the row direction, and is supplied from the ROM 515 via the latch circuit 518. The control procedure for the various processes described above in the microprocessor 51B is determined, for example, as shown in FIG. First, in step SO, a reference table for conversion between vector expression and power expression is created. In step S2, a count value of the start address for the microcode for code generation or syndrome calculation is input to the counter 514 by a command from an external device. Preload. In this state, when a start command is received, step S3
Then, data (no "Dt) is input, and code generation or syndrome calculation is executed by the circuit with the hardware configuration shown in FIG. If it is determined, the process proceeds from step S4 to step S5. In step S5, it is determined from the completed microcode whether the processing executed by the hardware circuit until then is code generation or syndrome operation. When it is determined in step S5 that code generation is required,
Proceeding to step SB, the counter 514 is preloaded with the contents of the buffer memory 510, that is, the count value corresponding to the start address of the microcode of the process for transferring the code-generated data to the outside. Then, when a start command is received, step S7
Then, in the 0th order step S8 in which the buffer memory 510 is instructed to read such data, the buffer memory 5!
The code generation data stored in 0 is read out and transferred to the outside. In step S8, the microcode is monitored to determine whether the transfer has been completed. With the above steps, processing for one block is completed and step S is performed again.
Return to step 1 and repeat the same process. On the other hand, when it is determined in step S5 that it is a syndrome calculation, the process proceeds to step Sit, where the calculation is executed by the hardware configuration shown in FIG. 5 and the syndrome already stored in the buffer memory 510 is read out. In step S1, the equation (11) is calculated based on this syndrome, and step S1
3, errors in the data in the buffer memory 510 in the row direction are corrected. In step S14, an error flag is attached to the address of the uncorrectable row. The above steps Sll to S14 are repeatedly executed for the number of rows. Next, in step S15, the buffer memory 510
The syndrome is read out from , and the calculation of equation (7) is performed in step 91B.Furthermore, in step St? Now, errors in the data in the buffer memory 510 in the column direction are corrected. The processing of steps S15 to S17 is repeated for the number of columns. Next, the process proceeds to step S6, where data is read from the buffer memory 510 and transferred to the outside as described above. In this case, the transferred data is error-corrected data.

【Effect of the invention】

As described above, according to the present invention, code generation and syndrome calculations that require a lot of repetitive processing and can be configured with a simple circuit are processed by a hardware configuration, and error patterns and error positions that require few repetitive processes and are complicated in a hardware configuration are processed. Since the calculation of is executed by software, the system configuration can be simplified and the cost can be reduced. In addition, in the present invention, error positions and error patterns are processed by software using a microprocessor, so the processing speed is usually not very high if the overall system has a hardware configuration. However, the processing speed does not decrease much, there is no practical problem, and the overall effect is greater than the reduction in device cost.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a circuit that calculates the surplus of a generator polynomial, Figure 2 is a circuit diagram showing an example of a circuit that calculates syndromes, Figure 3 is a diagram showing the encoding structure of information words, FIG. 4 is a block diagram showing one embodiment of the error correction circuit of the present invention. FIG. 5 is a block diagram showing an embodiment of the syndrome calculation circuit, FIG. 6 is a block diagram showing an embodiment of the code word generation circuit in the row direction, and FIG. 7 is the code word generation circuit in the column direction. FIG. 8 is a circuit diagram showing a specific example of the arithmetic circuit in FIG. 5; FIG. 9 is a flowchart showing a series of control procedures in the error correction circuit of the present invention. 51. 53, 55, 511... Three-state bus driver (transceiver), 52. 54, 518... Latch circuit, 56... AND gate, 57... Row direction check word generation circuit, 58. ... Column direction check word generation circuit, 58 ... Syndrome circuit, 510 ... Buffer memory, 512.513 ... Multiplexer, 514 ... Counter, 515 ... ROM, 51B ... Microprocessor, 519...Command e status signal line. V2 f

Claims (1)

[Scope of Claims] Among a code word group configured to assign an inner code in the row or column direction and an outer code in the column or row direction of the information word group,
An error correction circuit configured to perform first error correction on an inner code and correct errors that cannot be corrected on the inner code using an outer code, comprising: a circuit for generating code words for the inner code and the outer code; , a syndrome calculation circuit that calculates a syndrome for the inner code and the outer code, a first memory that temporarily stores the generated code word and the calculated syndrome, and error pattern and position detection and error in the inner code. a first program that executes a correction process according to the calculated inner code syndrome;
and a second memory storing a second program for executing error pattern and error correction processing in the outer code according to the calculated syndrome of the outer code, the code generation circuit, the syndrome calculation circuit, and the first memory. A third memory storing a program to be controlled, and the first, second and third memories, and controlling the code word generation circuit and the syndrome calculation circuit and the execution of the first and second programs. An error correction circuit characterized in that it comprises a microprocessor that performs the error correction.