JPH10135847A - Parallel header error correction circuit and header error correction method for atm communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale of a delay circuit to be given to a main signal to control a memory capacity of a table to store a syndrome pointing out each error bit location in 40-bit and a correction timing of a discriminated error bit. SOLUTION: A full expansion type 40-bit CRC-8 arithmetic circuit 6 calculates a syndrome with respect to a header part of ATM cell data received in parallel in 8-bit, an error bit location is discriminated by collating a 1st byte error with data in a syndrome storage table 12 to correct the bit. As to correction of 2nd and succeeding bytes, after 8-bit parallel processing CRC-8 arithmetic operation is applied to the syndrome for each clock shift of received data S1, the result is collated with data in the syndrome storage table 12 to discriminate an error bit location to correct the bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a header error correction circuit on the receiving side of an ATM communication apparatus, and more particularly to a header error correction circuit and a method for realizing a reduction in circuit size.

[0002]

2. Description of the Related Art For 40 bits of an ATM cell header, C is used.
In a header error correction circuit for performing error correction using an RC-8 code and performing one-bit error correction, a CRC-
A calculation result (syndrome) using eight codes is calculated, and from the value of the syndrome, it is determined which byte among the first to fifth bytes (total 40 bits) of the header of the ATM cell is erroneous, It is necessary to invert the corresponding bit.

FIG. 3 shows a configuration of a conventional header error correction circuit. The header error correction circuit shown in FIG.
927 corresponds to the shift register circuit and the cell synchronization header error control circuit shown in FIG. The illustrated header error correction circuit includes five-stage shift registers 14 to 18, a fully expanded 40-bit CRC-8 operation circuit 19, a cell synchronization circuit 20, a syndrome verification circuit 21, and first to fifth byte syndromes. It comprises a storage table 22, four error bit inversion circuits 23 to 26, and three shift registers 27 to 29 functioning as delay circuits.

FIG. 4 shows data stored in the first to fifth byte syndrome storage tables 22.

In the prior art, the first of the ATM cell header is
It has a table 22 for storing 40 types of syndromes indicating the error bit positions of 40 bits from the byte to the fifth byte.
The error bit position is determined by checking the result of the C-8 operation.

Further, in the conventional technique, there are provided delay circuits 27 to 29 to be provided to a main signal corresponding to a syndrome collation (error bit determination process) time, and the main signal passes through the delay circuit to generate an error bit. Is controlled, and error bits are inverted.

[0007]

As described above, in the prior art, the CR of the header of the ATM cell is 40 bits.
In a header error correction circuit for performing error detection using a C-8 code and performing one-bit error correction, a CRC-8
A calculation result (syndrome) by a code is calculated, and from the value of the syndrome, it is determined which byte among the first byte to the fifth byte (40 bits in total) of the ATM cell header is erroneous. , The corresponding bit needs to be inverted.

Here, the CRC for the actual input data
To determine the error bit position from the -8 operation result (syndrome), the header error correction circuit requires an ATM
4 from the first byte to the fifth byte of the cell header
It is necessary to have a table 22 for storing 40 types of syndromes indicating the error bit positions of 0 bits, and to compare and match the syndrome of the operation result with the syndrome in the table. Therefore, the memory capacity for the table 22 becomes enormous.

Since the syndrome verification (error bit determination processing) at this time has a certain circuit delay, in order to control the correction timing of the determined error bit, the main signal is supplied to the delay circuits 27 to 27 corresponding to the delay. It is necessary to have 29. Therefore, the circuit scale becomes enormous.

The present invention has been made in such a background, and an object thereof is to store a syndrome indicating a 40-bit error bit position from the first byte to the fifth byte of the ATM cell header. Another object of the present invention is to reduce a memory capacity for a table to be executed.

Another object of the present invention is to reduce the circuit scale of a delay circuit to be provided to a main signal in order to control the correction timing of a determined error bit.

[0012]

According to the present invention, there is provided a parallel type header error correction circuit for an ATM communication device, comprising: a header for an ATM cell including an HEC (Header Error Control) byte in a cell synchronization detector on a receiving side of the ATM communication device. Performs an operation using a CRC-8 code on 40 bits, detects ATM cell synchronization, detects an ATM cell header error in an error detection mode,
The ATM cell header part error bit determination by the syndrome operation method in the error correction mode, and a cell synchronization detection unit that performs correction processing of the determined error bit.
Fully expanded 40-bit CR for detecting TM cell synchronization
A C-8 arithmetic circuit, a first byte syndrome storage table for storing a syndrome (a value indicated by a calculation result of CRC-8) indicating an error in the first byte of the ATM cell header, and a second byte of the ATM cell header. An 8-bit parallel processing type CRC-8 arithmetic circuit for easily calculating a syndrome indicating an (n-1) th byte error from a syndrome indicating an nth byte error, and a CRC-8 operation for actual input data A syndrome matching circuit for comparing and matching the resulting syndrome value with the syndrome value stored in the first byte syndrome storage table;
As the syndrome value of the RC-8 operation result, all expansion type 4
Comparison between the ATM cell header first byte timing generation circuit and the syndrome verification circuit, which selects one of the output of the 0-bit CRC-8 arithmetic circuit and the output of the 8-bit parallel processing type CRC-8 arithmetic circuit and supplies it to the syndrome verification circuit An error bit inverting circuit for correcting data at the determined error bit position in the input data based on the result.

[0013]

The syndrome is calculated by a fully expanded 40-bit CRC-8 arithmetic circuit for the header portion of the ATM cell data input in parallel with 8 bits, and for the error in the first byte, the syndrome is stored in the second byte. By comparing the data with the data in the first byte syndrome storage table, the error bit position is determined and the corresponding bit is corrected.

For corrections after the second byte, see "A
When an 8-bit parallel processing type CRC-8 operation is performed on a syndrome indicating an error at the n-th byte of the TM cell header,
It becomes a syndrome indicating an error of the (n-1) th byte ", and utilizes the feature of the code theory to
An error bit position is determined by performing an 8-bit parallel processing type CRC-8 operation on the syndrome at each clock shift and then comparing it with data in the syndrome storage table of the first byte in which the syndrome is stored. Correct the corresponding bit.

[0015]

Embodiments of the present invention will be described below in detail.

The parallel header error correction circuit of the ATM communication device includes a 40-bit fully expanded CRC-8 arithmetic circuit for detecting ATM cell synchronization, and a syndrome (CRC) indicating an error in the first byte of the ATM cell header. The first byte syndrome storage table for storing the value indicated by the calculation result of −8, and the syndrome indicating the error of the (n−1) th byte from the syndrome indicating the error of the nth byte of the ATM cell header. , An 8-bit parallel processing type CRC-8 arithmetic circuit for easily calculating, and a syndrome value of a CRC-8 operation result for actual input data and a syndrome value stored in the first byte syndrome storage table. The syndrome matching circuit for comparison and matching and the ATM cell header first byte timing generation circuit are Composed of an error bit inversion circuit for correcting data bit positions.

Next, the operation of the parallel type header error correction circuit will be described.

For the header part of the ATM cell data input in parallel with 8 bits, a fully expanded 40-bit CRC-8 is used.
The syndrome is calculated by the arithmetic circuit, and the syndrome matching circuit compares the calculated syndrome with the setting syndrome stored in the first byte sildrome table. When these syndromes match, the error bit inversion circuit performs error correction by inverting the corresponding bit at the first byte timing.

For the correction of the second and subsequent bytes, the 8-bit parallel processing type CRC-8 arithmetic circuit performs an 8-bit parallel processing type CRC-8 operation on the corresponding syndrome every clock shift of the input data. Then, the syndrome collating circuit performs collation with the set syndrome stored in the syndrome table of the first byte at each clock shift.

At the timing of detecting coincidence with the syndrome data in the syndrome table in the first byte, an error bit in the header portion (second byte to fifth byte) of the ATM cell to be corrected is detected by using an error bit inversion circuit. To correct.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a parallel type header error correction circuit according to one embodiment of the present invention. The illustrated parallel header error correction circuit includes five stages of shift registers 1-5.
And a fully developed 40-bit CRC-8 arithmetic circuit 6,
M cell header first byte timing generation circuit 7, selection circuit 8, register 9, 8-bit parallel processing type CRC-
8 operation circuit 10, syndrome verification circuit 11,
It is composed of a byte syndrome storage table 12 and an error bit inversion circuit 13.

First, five-stage shift registers 1 to 5 are prepared for ATM cell data to be input in parallel with 8 bits, and all expanded type 40-bit CRC-8 arithmetic circuits 6 perform CR-CR operations.
Perform C operation. Here, the generator polynomial of CRC-8 is X ⁸ + X ² + X + 1 by definition. This full deployment type 40
In the hunting state before the ATM cell synchronization is established, the bit CRC-8 arithmetic circuit 6
It works to find the position of the bit, and after the ATM cell synchronization is established, works to calculate the syndrome necessary to perform one-bit error correction among the 40 bits of the ATM cell header.

Fully expanded 40-bit CRC-8 arithmetic circuit 6
Then, since the ATM cell position is known when the ATM cell synchronization is established, the cell synchronization information S7 is stored in the first ATM cell header.
The data is transmitted to the byte timing generation circuit 7. After the ATM cell synchronization is established, the fully expanded 40-bit CRC-8 arithmetic circuit 6
Is a 40-bit fully expanded CR for 40-bit header
C-8 calculation is performed to calculate the syndrome S8. At this time, the selection circuit 8 controls the selector based on the first byte timing S9 from the ATM cell header first byte timing generation circuit 7, and calculates the fully expanded 40-bit CRC-8 arithmetic circuit 6 at the cell header first byte timing S9. The generated syndrome S8 is stored in the register 9.

Further, the value of the syndrome S11 is changed to the syndrome (the value shown in FIG.
The generator polynomial that defines the syndrome is X ⁸ + X ² + X
Each value in the table 12 storing +1) is collated by the syndrome collation circuit 11. Here, if there is an error in any bit of the first byte, there is a corresponding syndrome, and it is determined which bit is incorrect. At the same time, the main signal is at the timing when the first byte of the cell header comes to the register 5 immediately before the error bit inverting circuit 13. Therefore, the data at the determined bit position is inverted to perform one-bit correction. It is.

Next, regarding the error correction of the second and subsequent bytes, an 8-bit parallel processing type CRC-
8 arithmetic circuit 10 (generating polynomial is X ⁸ + X ² + X + 1)
Use 8-bit parallel processing type CRC-8 arithmetic circuit 1
0 is used for efficiently performing a CRC-8 operation by passing the circuit five times per byte for a 40-bit ATM cell header when normally handling 8-bit parallel ATM cell data. used.

However, in this case, in the syndrome defining the 1-bit error bit position, when the 8-bit parallel processing type CRC-8 operation is performed on the syndrome indicating the error of the n-th byte of the ATM cell header, the (n- 1) It becomes a syndrome that indicates an error at the byte. " For example, if an error bit exists somewhere in the second byte, 8
One pass through the bit parallel processing type CRC-8 arithmetic circuit 10 results in a match with the syndrome value indicating the same error bit position in the first byte.

At this time, the selection circuit 8 switches so as to select the output data of the 8-bit parallel processing type CRC-8 arithmetic circuit 10. In addition, since the above operation is performed within one clock, the main signal at this time is the timing at which the second byte of the cell header has just arrived at the register 5 immediately before the error bit inverting circuit 13, and the data at the determined bit position Are inverted to perform one-bit correction.

The 1-bit error existing somewhere in the third, fourth, and fifth bytes is also passed through the 8-bit parallel processing type CRC-8 arithmetic circuit 10 every clock shift, thereby obtaining the first bit error. It becomes a syndrome value indicating the same error bit position of the byte, and realizes error correction sequentially.

Here, differences from the conventional circuit example shown in FIG. 3 will be described. In a conventional circuit, an 8-bit parallel processing type CRC that calculates a syndrome for each error byte position is used.
Since there is no -8 arithmetic circuit, for the syndrome storage table, 40 syndromes indicating the error bit positions of 40 bits from the first byte to the fifth byte of the ATM cell header must be prepared. Therefore, the memory capacity for the storage table becomes large. When the error bit position is identified by the syndrome verification, the shift register 27 to 29 is determined as shown in FIG. 3 according to the byte of the ATM cell header.
, The corresponding byte position can be specified by shifting the main signal every clock, thereby realizing 1-bit correction. Therefore, in this case, a shift register for defining the corresponding byte position of the error bit is required.

On the other hand, an 8-bit parallel processing type CRC-
Since the 8-operation circuit 10 can be realized only by a simple exclusive OR logic circuit, the scale is very small. As a result, the memory capacity for storing the above-mentioned 40 types of syndromes can be reduced, and 1-bit error correction can be realized without having a shift register for defining the byte position of the main signal, thereby reducing the circuit scale.

The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the spirit of the present invention.

[0033]

As described above, according to the present invention, the AT
When implementing one-bit error correction of an ATM cell header in an M communication device, the circuit size can be reduced by reducing the memory capacity for storing syndromes and omitting a shift register that specifies the byte position of a main signal. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a parallel type header error correction circuit according to one embodiment of the present invention.

FIG. 2 is a diagram showing the contents of a syndrome storage table used in the parallel header error correction circuit shown in FIG. 1;

FIG. 3 is a block diagram showing a conventional header error correction circuit.

FIG. 4 is a diagram showing the contents of a syndrome storage table used in the header error correction circuit shown in FIG. 3;

[Explanation of symbols]

 1-5 shift register 6 fully expanded 40-bit CRC-8 arithmetic circuit 7 cell header first byte timing generation circuit 8 selection circuit 9 register 10 8-bit parallel processing type CRC-8 arithmetic circuit 11 syndrome verification circuit 12 first byte syndrome Storage table 13 Error bit inversion circuit S1 Input data S2 to S6 Transfer data S7 Cell synchronization information S8 Calculation syndrome S9 First byte timing S10 Calculation syndrome S11 Verification syndrome S12 Setting syndrome S13 Error bit position information

Claims (3)

[Claims] 1. An AT including a HEC (Header Error Control) byte in a cell synchronization detector on a receiving side of an ATM communication apparatus.
Performs an operation on the 40 bits of the header of the M cell using a CRC-8 code, detects ATM cell synchronization, detects an error in an ATM cell header in an error detection mode, and determines and determines an error bit in an ATM cell header in a syndrome operation method in an error correction mode. The cell synchronization detection unit for performing correction processing of the corrected error bit, a fully expanded 40-bit CRC-8 arithmetic circuit for detecting ATM cell synchronization from input data, and an error in the first byte of the ATM cell header. A first byte syndrome storage table for storing a syndrome (a value indicated by a calculation result of CRC-8), and a syndrome indicating an error of the (n-1) th byte from the syndrome indicating an error of an nth byte of an ATM cell header An 8-bit parallel processing type CRC-8 arithmetic circuit for calculating A syndrome matching circuit for comparing and comparing a syndrome value of a CRC-8 operation result with respect to the syndrome value stored in the syndrome storage table of the first byte, and a syndrome value of the CRC-8 operation result as: The output of the fully expanded 40-bit CRC-8 arithmetic circuit and the 8
An ATM cell header first byte timing generation circuit that selects one of the outputs of the bit parallel processing type CRC-8 arithmetic circuit and supplies the output to the syndrome verification circuit; and a comparison verification result of the syndrome verification circuit.
An error bit inverting circuit for correcting data at a determined error bit position in the input data. A parallel type header error correcting circuit for an ATM communication device. 2. A header error correction method for performing error detection on a 40-bit ATM cell header using a CRC-8 code and performing one-bit error correction, comprising the steps of: "error in the nth byte of the ATM cell header; When an 8-bit parallel processing type CRC-8 operation is performed on the syndrome indicating the error, a syndrome indicating an error in the (n-1) th byte is generated. " By providing a -8 arithmetic circuit, there is no table for storing 40 types of syndromes indicating the error bit positions of the 40 bits from the first byte to the fifth byte of the normally required ATM cell header. It has a table that stores eight types of syndromes that indicate an error in only the first byte of the ATM cell header. Header error correction method characterized by reducing the amount of memory required to. 3. A 40-bit fully expanded CRC-code for a header portion of 8-bit parallel input ATM cell data.
The 8 arithmetic circuit calculates the syndrome, compares it with the data of the table in which the syndrome indicating the error in the first byte is stored, and if the syndrome matches, inverts the corresponding bit at the timing of the first byte. Error correction is performed. For correction of the second and subsequent bytes, an 8-bit parallel processing type CRC-8 operation is performed on the syndrome every clock shift of the input data, and a match with the syndrome data in the table is performed. At the detection timing, the header part of the ATM cell to be corrected (2nd to 5th bytes)
Is controlled so that it is located at the position of the error bit inverting circuit, thereby reducing the delay circuit to be provided to the main signal in response to the error bit reflection processing time normally required. Characteristic header error correction method.