JPS6221137B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction decoding method using Reed-Solomon codes.

Reed-Solomon codes are one of the most powerful error correcting codes currently known for correcting random errors.

Regarding Reed-Solomon codes, the North Holland Publishing Company in the United States (NORTH-HOLLAND PUBLISHING
FJMACWILIAM, published in 1978 by COMPANY
N.A.A. Sloan (N.J.A.
SLOAN) The Theory of Error Correcting Cause (THE THEORY OF
ERROR CORRECTING CODES).

Since this code is a type of cyclic code, its encoding can be realized relatively easily using a well-known cyclic code encoder, but its decoding requires a general conventional method. This has the disadvantage that the apparatus becomes very complex and the error detection ability of the code itself is not fully utilized.

The object of the present invention is to eliminate these drawbacks of the prior art.

The present invention generates a Reed-Solomon code of code length N (where N is a positive integer larger than M) generated from a generator polynomial obtained by the product of M (where M is a positive integer) first-order polynomials. and M syndromes S ₁ , S ₁ , ......, S _M- for the received code.
₁ , and if it is detected that an error of only one symbol has occurred in the received code based on the syndrome, the error is corrected, and if an error of two or more symbols is detected, detection information indicating the existence of an error is generated. This relates to a method for outputting .

In particular, the present invention provides M number of the syndromes S ₀ ,
S ₁ , ......, S _M-1 are calculated, and the syndromes S ₀ , S ₁ , ... are calculated from M shift registers, respectively.
......, syndrome calculating means for individually generating S _M-1 , and after calculating the syndromes S ₀ , S ₁ , ......, S _M-1, this calculating means cuts off the input and shifts the Syndrome comparing means for determining whether the outputs of the M shift registers are equal or not each time a shift is performed when repeating an operation by repeating a shift operation of the registers;
an error position calculating means for counting the number of shift clocks applied to shift the shift register and calculating an error position from that value;
Syndrome all-zero determination means for determining whether all of S ₀ , S ₁ , ......, S _M-1 are "0", the output of the syndrome comparison means, the output of the error position calculation means, and the syndrome In response to the output of the all-zero determining means, it is determined whether or not to perform correction according to a predetermined algorithm, and when correction is to be performed, the above-mentioned The present invention relates to a Reed-Solomon code decoding system having an error correction means that detects syndrome S ₀ as error information to be corrected and performs the error correction.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment includes a syndrome calculation circuit 1, an S ₀ storage circuit 2, a syndrome comparison circuit 3, an error position calculation means 4, a syndrome all zero determination circuit 5,
It has a correction execution control logic circuit 6 and an error correction execution circuit 7.

Now, before explaining the details of the operation of this embodiment according to this block diagram, the principle of operation will first be explained.

Generally, in a Reed-Solomon code, N
symbols constitute one code block, and this one
M check symbols and N-
M information transmission symbols are included. There are various types of symbols used here, but in this embodiment, it is assumed that they are 8-bit code vectors, which are generally widely used. In order to make the explanation more concrete, it is assumed that the number of symbols (code length) in one code block is N=32, and the number of test symbols in one code block M=4. Therefore, the number of information transmission data symbols in one code block is N
−M=28.

Now, each of the 32 symbols in one code block will be represented by B ₀ , B ₁ , B ₂ , B ₃ , B ₄ , . . . , B ₃₁ . Any B _j is a 1-byte code and thus represents one element out of 2 ⁸ =256 elements. Also, symbol B ₄ in this
~B ₃₁ , 28 symbols are for information transmission data,
It is assumed that the remaining _B0 to _B3 are test symbols created based on _B4 to _B31 .

Now, in the Reed-Solomon code, during the encoding process, the test symbols _B0 to _B3 are created so as to satisfy the following constraint relationship with the information transmission data symbols _B4 to _B31 . That is, B ₀ +B ₁ +B ₂ +…………+B ₃₁ = 0 ………(1) B ₀ +αB ₁ +α ² B ₂ +…………+α ³¹ B ₃₁ = 0
………(2) B ₀ + α ² B ₁ + α ⁴ B ₂ +…… + α ⁶² B ₃₁ = 0
………(3) B ₀ + α ³ B ₁ + α ⁶ B ₃ +…… + α ⁹³ B ₃₁ = 0
………(4) In these formulas (1) to (4), the symbol B of each symbol
In addition to _j , the symbol α is used, and the operation of the sum connected with +, the product between α (power of α), and α
The calculation of the product of the power of and B _j is used. This α represents a specific symbol, and the above-mentioned sum and product also mean special operations different from the general sum and product of binary numbers. This will be explained below.

As mentioned above, in this embodiment, both B _j and α are code vectors made up of 8-bit "1" and "0" codes. Therefore, each represents one element out of 2 ⁸ =256 elements.

Now, select any two elements A and B from these 256 elements, and select the element A specified by the sum of these two elements.
Assuming that both +B and the element AB specified by the product of two elements become one element of the original 256, each of them is defined as follows.

Sum: As shown in Figure 2, elements A and B are expressed in the form of code vectors, and the code vector resulting from the exclusive OR of each digit (each dimension) is expressed as A.
+B is defined. Because the sum operation is defined in this way, the sum of two same elements is always “0” (a code vector in which all the components of each dimension are “0”),
Further, the calculation of the difference as the inverse calculation of the sum is the same as the calculation of the sum.

Product: For example, if there are elements A and B as shown in Fig. 3, then let them be expressed as polynomials of x A=1+x ² +x ³ +x ⁵ B=x ² +x ⁴ , and the product AB of this polynomial is AB= (1 + x ² + x ³ + x ⁵ ) (x ² + x ⁴ ) = x ² + (x ⁴ + x ⁴ ) + x ⁵ + x ⁶ + (x ⁷ + x ⁷ ) + x ⁹ . In this, terms of the same power of x correspond to the same digit (dimension) of the code vector, so if we apply the exclusive OR rule mentioned above and rearrange the above equation, AB=x ⁹ +x ⁶ +x ⁵ + x ² . Since this polynomial includes a term of x to the 7th power or higher (that is, ^x9 term), it is not possible to specify the corresponding 8-bit code vector as is.

Therefore, when defining the product, an irreducible polynomial f(x) of degree 8 is determined in advance and is used to define the product as follows.

Assuming that this f(x) is f(x)=x ⁸ +x ⁵ +x ³ +x+1, the polynomial of AB is divided using this f(x) and the resulting remainder is generated. In this case, the remainder will necessarily be a polynomial of degree 7 or less of x, and therefore there will be an 8-bit code vector corresponding to this. This is defined as the product AB. In this case, the polynomial of AB mentioned above is expressed as f
The quotient divided by (x) is x, and the remainder is x ⁵ + x ⁴ + x (the above-mentioned exclusive OR rule is applied to this operation as well, and subtraction and addition are the same). From this, AB=x ⁵ +x ⁴ +x, which is expressed as a code vector as shown in Fig. 3-2.

As described above, when the 8th degree irreducible polynomial f(x) is specified, the sum and product are defined between each of the 256 elements, and the difference and quotient as the inverse calculation thereof are also defined, Four arithmetic operations are performed consistently among 256 elements.

Now, by appropriately selecting the irreducible polynomial f(x), all 255 elements except "0" (an element in which all digit components are "0") among the 256 elements can be solved. , can be expressed in the form of a power of some element α. In other words, by taking 1 as the identity element and multiplying it by α one after another, the elements α, α ² ,
^{α3 , .}

Actually, if f(x)=x ⁸ +x ⁵ +x ³ +x+1 is used as the irreducible polynomial f(x), and x in polynomial expression is used as α,
All elements of 255 are α ^j (where j=0, 1, 2,...
......, 255). However, α ⁰ =α ²⁵⁵ =1. This α is called a primitive element, and a polynomial f(x) having such properties
is called a primitive polynomial. It is known that there are 16 8th-order primitive polynomials with such properties, including the ones mentioned above. In this example, these 16
It is assumed that operations between elements are defined by a specific primitive polynomial among the primitive polynomials, and the primitive element α defined by this is used. As a result, any element other than 0 can be expressed as α ^j (where j=0, 1, 2, ……, 254),
Therefore, any element can be specified using only the index j. We will call this the original exponential representation. Using this exponential representation, the product of any two elements except “0” takes the exponential representation of each element,
By adding both of them modulo 255, it can be easily calculated as an exponential expression of the product of both. If one element contains "0", the element of the result may be set to "0". In addition, when creating a quotient, it is sufficient to invert the "1" and "0" of each digit of the original binary number in exponential representation that becomes the denominator, and then add it modulo 255 as described above.

Of course, when calculating the sum of two elements, it can be easily performed using code vector representation.

In this way, each element can be specified as a power of α, an exponential representation of α, a code vector representation, or a polynomial representation. Which of these expressions to use can be selected depending on the purpose of use.

Now, the operations in equations (1) to (4) have been defined in this way, but in reality, any symbol for information transmission data can be used.
The test symbols B 0 to _{B 3} that satisfy the constraint conditions of equations ( ₁ ) to (4) are generated from B ₄ to B ₃₁ as follows.

Now, as the generator polynomial g(X), g(X)=(X-1)(X-α)(X-α ² )(X-α ³ ) is defined, and as the one-sign polynomial C(X), C Define (X)=B ₃₁ X ³¹ +B ₃₀ X ³⁰ +…………+B ₄ X ⁴ . If the polynomial of the remainder obtained by dividing this C(X) by g(X) is R(X), then R(X) is a polynomial of degree 3 or lower regarding X, so R(X)=b ₃ X It can be expressed as ³ +b ₂ X ² +b ₁ X+b ₀ . b ₃ , b ₂ , b ₁ and b ₀ determined in this way
The test symbols B ₃ , B ₂ , B ₁ and B ₀ respectively
When used as , these are (1) ~
It is an inspection symbol that satisfies the constraint condition of equation (4).

Now, the quotient obtained by dividing C(X) by g(X) is Q(X)
When written as, C(X)=g(X)Q(X)+R(X)
From now on, C(X) + R(X) = g(X)
Q(X) is derived (again, subtracting R(X) is the same as adding R(X)). Therefore, C(X)+ ^R ₍ ^X ) is divisible by g(X), and B ₃₁ X ³¹ +B ₃₀ X ³⁰ +…………+B _{4 X} ⁴ + _{B 3} X-1)(X-α)(X- ^α2 )(X- ^α3 )Q(X) holds true. For X on both sides of the above equation, 1,
By successively substituting α, α ² and α ³ , the relationships in equations (1) to (4) are derived.

Now, the code blocks B ₀ , B ₁ , B ₂ , . . . which satisfy the constraint condition of equation (1) created on the transmitting side as described above are created.
………, B ₃₁ are received and they are B ₀ , B ₁ , B ₂ ,…
Suppose that it is received as B ₃₁ . It is assumed that an error occurs in only one symbol B _j among them. That is, for k other than j, B _k =B _k (5) holds true, and for B _j , B _j =B _j +E _j (6) holds true. However, E _j is an error occurring in the j-th symbol.

Now, on the receiving side, the received symbol B ₀ ,
Using B ₁ , B ₂ , ......, B ₃₁ , α is added to the left side of equation (2).
²²⁴ and the left side of equation (3) is α ⁴⁴⁸ (=α
¹⁹³ ), and the left side of equation (4) is α ⁶⁷² (=α
¹⁶² ), and the results are respectively
Let them be S ₁ , S ₂ , and S ₃ . In other words, the result of this calculation is B ₀ +B ₁ +B ₂ +…………+B ₃₁ =S ₀ …………(7) α ²²⁴ (B ₀ +αB ₁ +α ² B ₂ +…………α ³¹ B ₃₁ ) =S ₁ …………(8) α ⁴⁴⁸ (B ₀ +α ² B ₁ +α ⁴ B ₂ +…………α ⁶² B ₃₁ ) =S ₂ …………(9) α ⁶⁷² (B ₀ + α ³ B ₁ +α ⁶ B ₂ +…………α ⁹³ B ₃₁ ) =S ₃ …………(10).

If there is no error in reception, S ₀ to S ₃ on the left side of equations (7) to (10) will all be zero due to the relationships in equations (1) to (4). If there is an error in reception, the operation results corresponding to the left-hand sides of equations (7) to (8) will generally be each non-zero value.
We will take S ₀ , S ₁ , S ₂ and S ₃ . This is called a syndrome. In this embodiment, using the syndromes S ₀ to _{S 3} , errors are calculated from the constraint calculation relationships of equations (1) to (4) added between symbols in one block on the transmitting side and corrected.

Now, by substituting the relationships in equations (5) and (6) into the left side of equations (7) to (10) and calculating using the relationships in equations (1) to (4), each syndrome S ₀ , S ₁ , S ₂ , S ₃ are It is expressed as

Below, when calculating the syndromes S ₀ , S ₁ , S ₂ , and S ₃ , the 32 symbols in the received code block are
An example will be explained in which B ₃₁ to B ₀ are input in the order of B ₃₁ →B ₀ . This is shown as an example in which error correction is performed using the obtained syndrome information S ₀ to _{S 3} with a relatively simple configuration, and the calculation speed is increased and reliability is improved. Therefore,
As another example of the present invention, the symbols corresponding to each of B ₃₁ to _{B 0} may be set to C ₀ to _{C 31} and input in the order of C ₀ →C ₃₁ .

The details of the operation of the above-mentioned example will be described below with reference to FIG.

First, the above 32 symbols are input in the order of B ₃₁ → B ₀ , so by transforming equation (11), S ₀ = E _j ......(12) S ₀ = α ^31-j S ₁ ... ...(13) S ₀ = α ^2(31-j) S ₂ …………(14) S ₀ = α ^3(31-j) S ₃ …………(15).

Further, in FIG. 1, the symbol block of the received input signal is supplied from the data input line 100 to the syndrome calculation circuit 1 in the order of symbols B ₃₁ , B ₃₀ , . . . B _{0 .} In this syndrome calculation circuit 1, calculations corresponding to the above-mentioned equations (7) to (10) are executed to obtain the syndromes S ₀ , S ₁ , S ₂ , and S ₃ . Figures 4 a to c show the syndromes in this
An example of a circuit for determining S ₁ to _{S 3} is shown. Example of a circuit for determining syndrome S ₁ Figure 4a shows a one-stage shift register 1
3, read-only memories (hereinafter referred to as ROM) 10 and 12, and an exclusive OR circuit 11. Shift register 13 and circuit 11 each process 8 bits in parallel. Also ROM1
0 is B ₃₁ input from the data line 100,
Each of B ₃₀ , . . . B ₀ (8 bits) has 256 memory addresses that can be addressed, and each address has a capacity to store 8 bits of data. The ROM 12 has 256 memory addresses that can be addressed by the output (8 bits) of the shift register 13, and each memory address has a capacity to store 8 bits of data. In the circuit shown in FIG. 4a, the memory address of the ROM 12 is designated by the output of the shift register 13, and
Data read from ROM12 and ROM10
The circuit 11 performs an exclusive OR with the data read from the shift register 13.
will be reloaded. Here, if the ROM 12 is expressed as an arbitrary 8-bit binary number A', the memory address of the ROM 12 specified by this A' is preset to αA' (however, αA' is the code vector corresponding to this binary number A' and the primitive By writing the multiplier with the element α, it operates as an α-times multiplier. Furthermore, if an arbitrary 8-bit binary number of the input data is expressed as B', the ROM 10 stores α in advance at the memory address of the ROM 10 specified by B'.
By writing ²²⁴ B' (where α ²²⁴ B' is the product of the code vector corresponding to the binary number B' and the element α ²²⁴ ), it functions as an α ²²⁴ multiplier. Thus, if we first reset the shift register 13 and input the input data through the circuit 10 one after another in the order of B ₃₁ , B ₃₀ , ...B ₀ as described above, then B ₀
At the time when is input, the contents of the shift register 13 are α ²²⁴ […………(((B ₃₁ α+B ₃₀ ) α+B ₂₉ ) α+…………+B ₃ ) α+B ₂ ) α+B ₁ ) α+B ₀ ] = α ²²⁴ {α ³¹ B ₃₁ +α ³⁰ B ₃₀ +……+αB ₁ +B ₀ }=S ₁ , and the desired syndrome S ₁ is obtained. ROM1
A similar circuit can be created by making the contents of ROM 10 correspond to α ² and α ³ instead of α described above, and the contents of ROM 10 corresponding to α ⁴⁴⁸ and α ⁶⁷² instead of α ²²⁴ described above. A circuit that calculates syndromes S ₂ and S ₃ , respectively, is obtained using . Furthermore, by feeding back the contents of the shift register 13 without change to the circuit 11 except for the ROMs 12 and 10, a circuit for calculating the syndrome _S0 can be obtained.

The syndrome S ₀ thus obtained is stored in the S ₀ storage circuit 2 and supplied to the error correction execution circuit 7 via the correction execution control logic circuit 6 . Further, the obtained syndromes _S0 to _S3 are supplied to the syndrome all-zero determination circuit 5.

Now, in the circuit for determining S ₁ to _{S 3} in FIGS. 4a to 4c, shift registers 13, 17, and 21 are currently outputting syndromes S ₁ to S ₃ . Therefore, the fourth
In the circuit for calculating S ₁ shown in FIG. Every time the shift clock is input, the ROM 12 operates as an α multiplier, and the output of the shift register 13 becomes α ⁿ S ₁ . Also,
Similarly, in the circuit for calculating S ₂ shown in FIG. 4B, if the number of shift clocks is n, the output of the shift register 17 will be α ²ⁿ S ₂ since the ROM 16 operates as an α ² multiplier. And Figure 4c
Similarly, in the circuit for determining S ₃ shown in FIG. 3, if the number of shift clocks is n, the output of the shift register 21 becomes α ³ⁿ S ₃ because the ROM 20 operates as an α ³ multiplier.

In this way, after the calculations of syndromes _S0 to _S3 , the data input to the shift registers 13, 17, and 21 are inhibited, and by inputting the same shift clocks as used during the calculations, α ⁿ S ₁ and α ²ⁿ are respectively input.
Three equations of S ₂ and α ³ⁿ S ₃ can be calculated.

In the above calculation, the n-th shift clock now has shift registers 13, 17, and 2.
Since the outputs of 1 are α ⁿ S ₁ , α ²ⁿ S ₂ , α ³ⁿ S ₃ respectively, each shift register 13, 17, 21
At the same time, the output satisfies α ⁿ S ₁ = S ₀ …………(16) α ²ⁿ S ₂ = S ₀ …………(17) α ³ⁿ S ₃ = S ₀ …………(18) Then, equations (13), (16), and (14)
From equations (17), (15), and (18), the relational equations n=31−j j=31−n (19) are obtained from the above (16), (17), ( 18) Equation 3 holds true. The fact that these three equations hold true indicates that there is a one-symbol error, and the position j of the error symbol can be found from equation (19). In the embodiment, the syndrome comparison circuit 3 compares the syndrome S ₀ supplied from the S ₀ storage circuit 2 and α ⁿ S ₁ supplied from the output 101 of the syndrome calculation circuit 1, and further compares the syndrome S ₀ and the output 102. A comparison with α ²ⁿ S ₂ supplied from the output 103 and a comparison between α ³ⁿ S ₃ (where n≧0) supplied from the output 103 and the syndrome S ₀ are performed. Therefore, if there is one error, all four data (S ₀ , α ⁿ S ₁ , α ²ⁿ S ₂ , α ³ⁿ S ₃ ) input to the syndrome comparison circuit 3 as described above are Match.
In this case, the syndrome comparison circuit 3 outputs the coincidence output 3.
00, which is supplied to the error position calculation circuit 4 and the correction execution control logic circuit 6.

When the error position calculation circuit 4 receives the coincidence output 300 from the syndrome comparison circuit 3, it calculates the above-mentioned error symbol position j (=31-n) and outputs the j value. The output 200 of the error position calculation circuit 4 is a shift clock for determining the error symbol position j using the shift register included in the syndrome calculation circuit 1 described above. The value of j output from the circuit 4 is supplied to the correction execution control logic circuit 6. A logic "1" is input to this circuit 6 from the output 500 only when the syndromes S ₀ to _{S 3} are all zero from the syndrome all zero determination circuit.

Now, the correction execution control logic circuit 6 controls the execution of error correction by the following logical operations based on the various input signals supplied as described above. First, when the output 500 of the circuit 5 is logic "1", that is, when the syndromes S ₀ to S ₃ are all zero, it is assumed that there is no error regardless of other input signals, and no error correction is performed. At this time, the circuit 6 outputs a signal indicating that there is no error in this code block by setting the error flag output 700 to be supplied to the subsequent stage circuit to logic "0".

Next, when the output 500 of the circuit 5 is logic "0", the following occurs. In this case, there must be an error, but if there is only one error, all of the syndromes S ₀ to S ₃ will not be zero due to the relationships in equations (1) to (10). In this case, when the above-mentioned comparison conditions (16) to (18) are satisfied, the syndrome comparison circuit 3 outputs a coincidence output 300, and the error position calculation circuit 4 outputs the position j of the error symbol. When these conditions are met, the error correction execution circuit 7 may be controlled to perform error correction on the j-th symbol using the error correction information S ₀ of equation (12). At this time, the error flag output 700 is set to logic "0" and a signal indicating that there is no error in this code block as a result of correction is output. If such a relationship does not hold, that is, if the coincidence output 300 is not obtained from the syndrome comparison circuit 3, the condition that the number of error symbols is one does not hold. Therefore, in this case, no correction is made and the error flag output 700, which means that this code block contains an error, is set to logic "1".

Now, the error correction information E _j (S ₀ ) subjected to the above control is supplied by the circuit 6 as an output 400, and the error symbol position information j is supplied as an output 401 to the error correction execution circuit 7.

This circuit 7 has a buffer that sequentially stores one block of symbols B ₃₁ , B ₃₀ . . . B ₀ input from the data input 100 into the next symbol position. Using exclusive OR, the supplied error correction information E _j (S ₀ ) is applied to the symbol B _j at the position specified by the error symbol position specification information j among the symbols stored in this way. Error correction is performed by adding. After error correction in this manner, each symbol is supplied as an output 600 to a subsequent circuit together with the error flag output 700.

In the above embodiment, in order to make the explanation concrete, the code length N is 32, the number M of check symbols in one code block is 4, and the number of bits K of each symbol is 8. Although the case in which a Reed-Solomon code is used has been described in detail, it is clear that the values of N, M, and K in the method of the present invention are not limited to these. Moreover, circuit examples of the various circuits used are shown as examples for realizing the circuits, and the present invention is not limited to these. In addition, the code block of the received input signal is exemplified in the case where each symbol is input in the order of B ₃₁ , B ₃₀ , ...B ₀ , but the syndrome S ₀
When calculating ~ _S3 , the symbols corresponding to each of the symbols _B31 ~ _B0 are _C0 ~ _C31 , and _C0 ,
You may input them in the order of C ₁ , ……C ₃₁ . In this case, when equations (16) to (18) are satisfied in the n-th shift of the shift registers 13, 17, and 21, j=n in equation (19). Therefore, in the circuit configuration in this case, n is counted down from 31 in the illustrated example, whereas n may be counted up from zero.

As described above, when the present invention is used, one error occurring in a Reed-Solomon code that is made up of one block with N symbols is corrected, and an error flag is issued when two or more symbols are detected. , by effectively utilizing the information of all syndromes up to the number M of test symbols, and simultaneously performing error detection when generating syndromes, the processing speed is increased, and the reliability of achieving the objective is achieved with a simple circuit configuration. It is possible to provide a highly efficient decoding method. This makes it possible to improve reliability and economy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a diagram for explaining the sum operation used in this example, Figure 3 1 is a diagram for explaining the sign polynomial for the operation used in this example, and Figure 3 2 is used in this example. FIG. 4, which is a diagram for explaining the product calculation, is a diagram showing an example of the internal circuit of the syndrome calculation circuit of this embodiment. DESCRIPTION OF SYMBOLS 1...Syndrome calculation circuit, 2... _S0 storage circuit, 3...Syndrome comparison circuit, 4...Error position calculation circuit, 5...Syndrome all zero determination circuit, 6...Correction execution control logic circuit, 7... Error correction execution circuit.

Claims (1)

[Claims] 1 Code length N generated from a generator polynomial obtained by the product of M (where M is a positive integer) first-order polynomials.
(where N is a positive integer larger than M)
A Solomon code is received, and M for the received code is
syndrome calculating means for individually outputting _the syndromes S ₀ , S ₁ , ......S _{M-1 ;}
Syndrome comparing means for determining whether each output of the calculating means is equal or not each time the repeated calculation is performed when the input of the received code is cut off after the calculation of S _M-1 and the calculation is repeated; Error position _calculation means for counting the number of shift _clocks given for repeated calculations and determining the error position from that value _; syndrome-all-zero determination means for determining whether or not correction should be performed according to a predetermined algorithm in response to the output of the syndrome comparison means, the output of the error position calculation means, and the output of the syndrome-all-zero determination means; When determining and correcting the error position, the syndrome S ₀ is detected as error information to be corrected for the symbol at the position determined by the error position calculation means, and the syndromes S ₀ , S ₁ , . . . …
...If it is detected that an error of only one symbol has occurred in the received code based on S _M-1, the error is corrected, and if an error of two or more symbols is detected, detection information indicating the existence of the error is transmitted. A Reed-Solomon code decoding system comprising an output error correction means.