JPS58169641A - Read solomon coding and decoding system - Google Patents

Abstract

PURPOSE:To increase the processing speed with simple circuit constitution, by using effectively the information of all syndromes up to the number of test symbols and detecting errors simultaneously with generation of syndromes. CONSTITUTION:A read Solomon coding/decoding system includes a syndrome arithmetic circuit 1, a storage circuit 2 of syndrome S0, syndrome comparator 3, an error position arithmetic means 4, a syndrome all-zero deciding circuit 5, a correction execution control logical circuit 6 and an error correction executing circuit 7. The circuit 1 delivers M units of syndromes S0-SM-1 to the received codes. The circuit 6 decides to execute or not a correction in accordance with the prescribed algorism and in response to the outputs of the comparator 3, the means 4 and the circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error and 4j correct decoding system using Reed-Solomon codes.

Reed-Solomon codes are one of the most powerful error-correcting codes currently known for correcting random errors.

Regarding Reed-Solomon codes, North Holland Publishing Company (N0RTH-HO
LLAND Pt1BLISHING C! OMPAN
Published in 1978 by F.J.
G.A. Sloan (N, J, A, S, LOAN
) Chopsticks The Theory Op Error Correcting
Korg (THE Tl0RY 0FEl(l(ORC(
Jl (RKCTING CODES).

Since this code is a type of cyclic code, its encoding can be realized relatively quickly using a well-known cyclic code encoder, but its decoding can be done using a general conventional method. This method has the disadvantage that the apparatus becomes very complex and the error detection ability of the code itself is not fully utilized.

The object of the present invention is to eliminate these drawbacks of the prior art.

The present invention is based on a Reed-Solomon code with a code length N ((υ, where N is a positive integer larger than M) generated from a generator polynomial obtained from a bond of M first-order polynomials (where M is a positive integer). A code is received, and M syndromes S for the received code are determined.
o, S, . This relates to a method of outputting a message indicating the existence of an error when an error is detected.

In particular, the present invention provides M number of the syndromes So, S,.

..., 5M-1, and calculate the syndromes So, S, , ..., 5 from M shift registers, respectively.
It is equipped with syndrome calculation means for individually generating M-1, and this calculation means generates syndromes So, s,
,..., after the calculation of SM-t, by cutting off the human power and repeating the shift operation of the previous d-pisisoto register (when repeating the calculation, the output of each of the M shift registers is syndrome comparison means for determining whether or not the syndrome SO
+SL+..., syndrome-all-zero determination means for determining whether all of 5M-1 are mol, output of the undromata scolding means, output of the error position calculation means, and output of the syndrome-all-zero determination and determination means. In response to this, a predetermined algorithm is set.
Then, it is determined whether or not to perform correction, and if correction is to be performed, the syndrome S is determined for the symbol at the position determined by the error position detection means.

was detected as the 16th error report that should be corrected, and this error correction 1F
The present invention relates to a Reed-Solomon code decoding system having an error correction means for performing the following.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of this research. This embodiment includes a syndrome arithmetic circuit 1, an So memory circuit 2, a syndrome comparison circuit 3, an error position calculation-H means 4, a syndrome all-zero judgment circuit 5, a logic circuit 6 for positive execution system, and an error correction execution circuit 7. have.

Now, before explaining the details of the operation of this embodiment according to this block diagram, the principle of operation will first be explained.

Generally, in a Reed-Solomon code, N symbols constitute one code block, and this one code block includes M test symbols and N-M information transmission symbols. . There are various types of symbols used here, but in this embodiment, it is assumed that they are 8-bit code vectors, which are generally widely used. In order to make the explanation more concrete, it is assumed that the number of symbols (code length) in one code block is N=32, and the number of symbols for detection in one code block M=4. Therefore, the number of information transmission data symbols in one code block is NM=28.

Now, BO! each of the 32 symbols in one code block!
It will be expressed as B11B2 +B3 +"4 + "' +B31. Any B, 1 is a 1-byte code, and thus represents one element among 2B=256111M elements. Also, 28 symbols B4 to B31 are symbols for information transmission data, and the remaining 13o-
Assume that B3 is a test symbol created based on B4 to B3I.

Now, in the Reed-Solomon code, the encoding J
At N, the test symbol Bo -B3 II'! ,
It is created so as to satisfy the following relationship between the information transmission data symbols B4 to B31. That is, Bo+
B++B2+・・・・・・-)−B3+=O−・□(
]) Bo+ αB, ) α2B2+...10α”'B
3+=0...(2)Bo 1α2B, 10αIB2
+・・・・・・10α62B31=0・・・・・・(3)
Bg + rt3B+ ++r6JJ3 +,,,-+
+ (293]33. =: 0...-14) This (
1) ~ (, In the 1j formula, m1 number Bj of each symbol
In addition to , the symbol ([ is also used, and the Oro 1 Jousan connected with tens, the performance of α Comrade 1 Shi (α's curtain), and the blow (Tora's calculation) between α's curtain and Bj are used. This α represents a specific symbol, and the above-mentioned sum and tsuke also represent the general two symbols.
, means a special operation different from the sum of base numbers and the sum of base numbers.

This will be explained below.

As mentioned above, in this embodiment, both Bj and α are 8-bit 111, and code pect 1 is made of Igl code.
□ Therefore, each represents one element out of 28=256 elements.

Now, select any two elements A and B from these 256 elements, redundancy A + B and 2 specified by the sum of these two elements.
Any of the elements AB specified by the product of two elements is the original 25
Assuming that it is one of six elements, each of them is defined as follows.

Sum: As shown in FIG. 2, elements A and B are expressed in the form of code vectors, and the code vector resulting from exclusive OR of each digit (each dimension) is defined as A + B. Because the sum operation is defined in this way, the sum of two same elements is always “0” (a sign vector with all the elements of the valley being 0), and the difference operation as the inverse calculation of the sum /'i It is the same as the operation of Honguchi.

Product: For example, if there are elements A and B as shown in Figure 3 (1), let this be a polynomial representation of X A = l + x2 + x3 - 1 - x5 B = x2 + 'x5) (x2-1-x')
=x2-4-(x4 +x4)+X5+X6+(X7
+X7) +X9. In this equation, terms of the same actuarial power of X correspond to the same digit (dimension) of the code vector, so if we apply the above-mentioned exclusive and one-order sum rule and rearrange it, the formula becomes AB=x9- 4-x6-)-x5-1-x2. Since this polynomial includes a term equal to or higher than the seventh power of X (that is, the term x9), it is not possible to specify an 8-pinto code vector corresponding to the distortion as it is.

Therefore, when defining the product, an irreducible Tanokai equation f (x) of order 8 is determined in advance, and this is used to define it as follows.

This f (x) is expressed as f (x)=x8-1- x5 +x3-1- x-1
-1, this f(x) is used to reduce the AB polynomial and produce the resulting remainder. In this case, the remainder will necessarily be a polynomial of degree 7 or lower than X, and therefore an 8-bit code vector will exist corresponding to this. This is defined as product AB. In this case, the quotient of dividing the AB polynomial above by f (x) is X,
The remainder is x5+x'-1-x (the above-mentioned exclusive OR rule is applied to this operation as well, and subtraction and addition are the same). From this, A B=x5+X4+X, and when this is expressed as a code vector, @Figure 3 (2)
It becomes as shown in .

As described above, when the 8th order irreducible polynomial f (x) is specified, oro and product are defined between each of the 2561 elements, and the difference and quotient are also defined as their inverse calculations, Four arithmetic arithmetic operations are performed without contradiction among 256 elements.

Now, by appropriately selecting the irreducible polynomial f'(x), all 255 elements of the 256 leapfrog elements except '0' (all digit elements are elements of 101) can be It can be expressed in the form of a curtain multiplication of a certain element α.In other words, the elements α, α2.α3..., α255, which are generated by taking 1 as a unit light and then multiplying it by α, are the above-mentioned 10
After going through all the elements except ``, the unit light is 1 again at α255.
It is possible to return to .

Actually, as the irreducible polynomial f (x), f' (x
)=x8 + x5 + x3 + x+1, α
Using a polynomial representation of X as The current α0=α255-1. This α is called a primitive element, and the polynomial f (x) having such properties is called a primitive polynomial. The 8th order primitive polynomial with such properties is 16 including the one mentioned above.
It is known that there are several. In this embodiment, it is assumed that operations between elements are defined by a specific one of these 16 primitive polynomials, and the primitive element α defined by this is used. As a result, 0
Any element except αj (where j=o, 1, 2...
, 254), and therefore, Ren Su's element can be specified using only the index J. We will call this the original exponential representation. Using this exponential expression, the product of any two elements except "0" can be easily expressed as an exponential expression of the product of both by taking the exponential expression of each element and adding both modulo 255. It can be calculated as follows. If one element contains 11, the element of the result may be 106. If you still want to create a quotient, just invert the 11 "O" of each digit of the original binary number in exponential representation that will be the denominator, and then add it modulo 255 as before.

Of course, when calculating the sum of two elements, it can be easily performed using code vector representation.

In this way, each element can be specified as a curtain power of α, an exponential representation of α, a code vector representation, or a polynomial representation. Which of these expressions to use can be chosen depending on the purpose of use.

Now, the calculations of equations (1) to (4) have been defined in this way, but in reality, any information transmission data symbols B4 to B3
1 to generate a test symbol BO-B3 that satisfies the constraint conditions of equations (1) to (4) as follows.

Now, as the generator polynomial g(X), g(X)=(X-1)(X-a)(X-B2)(X
-rt3) and one-sided code polynomial 2〇(X) as C(x) = B51X3' + B50X30+-+
Define B4X4. If the polynomial of the remainder obtained by dividing this 0(X) by gσ) is R(X), then R(x) is a polynomial of degree 3 or lower regarding X, so R(X) = b3X" -) b2X "ten"
JX+ b.

It can be expressed as B3 determined in this way. B2. bl and 6
゜ is the inspection symbol B3. B2. B1 and
When used as Bo, these are 1.1 for the following reasons.
) to (4) are test symbols that satisfy the constraint conditions of formulas.

Now, if we write the quotient obtained by dividing C(X)'r g(X)f as Q(X), then C(X) = g (X) to Q(X)FR), and from this, C(X) R(X)=gσ)Q(X)
is derived (also in this case, subtracting R(X) is R(X)
Therefore, 0 (X) + R area) is divisible by 6 area), so B51X31+B3oX30+,
・10B4X4+B5X3+B2X2+B, X1Bo-(
X -1) (X-α') (”αW) (X-43)
Q, (X) holds true. 1 for each side of X in the above equation
．． By successively substituting α, α2, and α3, the relationships in equations (1) to (4) are derived.

Now, the code blocks Bo, B, , B2 . ...!
B31△ △ Ha, △ are received, and they are BO, B,, B2.・・＋B31
Suppose that it is received as It is assumed that an error occurs in only one symbol Bj among these symbols. Oh, in other words,
For k other than J, △ Bk: Bk ・・・・・・・・・・・・・ (51 holds, and for Bj △ Bj= B,; −1−B5 ・・...(6). However, Ej is the error that occurred in the third symbol.

calculation, and α441'l (=α!9) on the left side of equation (3)
3) and α672 (=
α162), and the results are respectively S, , S2 . S3 and △ △ △ △ α672 (Bo+α3B, +α6B2+,,,α93B
31 )=S3...(Ill hit.

If there is no error in reception, all 5o-83 on the left side of equations (7) to 00 will be zero due to the relationships in equations (1) to (4). If there is an error in reception, the calculation results corresponding to the left-hand sides of (η~(8)) will generally take non-zero values So, S1, S2, and S3. This is called a syndrome. This example This syndrome 5
Using o-83, the error amount is determined from the constraint calculation relationships of equations H1 to (4) added between symbols within one block on the transmitting side and corrected.

Now, by substituting the relationships in equations (5) and (6) into the left side of equations (7) to 00) [7, and calculating using the relationships in equations (1) to (4), each syndrome So, S1. S2. S3 is expressed as follows.

Hereinafter, this syndrome So, S1. S2. During the calculation of S3, 32 symbols in the received code block are
△ △ △ B3□ to Bo, and an example of a platform input in the order of B3□→Bo will be explained. This has a relatively simple configuration, and if error correction is performed using the obtained syndrome information 5o-83, the calculation speed may be increased and the input may be made in the order of □.

Hereinafter, using Fig. 1, the operating force of the example mentioned above will be expressed, so if formula 00 is transformed, Sθ=EJ・・・−・・・・・・・・・・・・・・・・・・
・・・・04So=α3l−jsl・・・・・・・・・
・・・・・・(131So =ct2(3' ”82-
・-uiSo-α3 (31-j)s3 ・---(
15).

Further, in FIG. 1, the code block of the received human input signal is supplied from the data input line 100 to the syndrome calculation circuit 1 in the order that each symbol △ △ △ is "311 B2O+...Bo." This syndrome calculation circuit 1
, the calculation corresponding to the above equation (10) is executed to obtain the syndrome SO+SI+S2+S
3 is required. FIGS. 4(a) to 4(C) show examples of circuits for determining syndromes 81 to S3. The circuit I+ll for determining the syndrome S1 is shown in FIG.
) 10.12 and an exclusive OR circuit 11. Shift register 13 and circuit 11 each process 8 bits in parallel. Further, ROM10 is inputted from data lines 100△△△, 1133+, E30. . . . Each Bo (8 bits) has 256 memory addresses that can be addressed, and each address has a capacity to store 8 bits of data. R, C1M12 is 256 which can be addressed by the output (8 bits) of the shift register 13.
memory addresses, and each memory address has a capacity to store 8 bits of data. This figure 4 (a
) The circuit shown in FIG.
The memory address of M12 is designated, and the circuit 11 performs an exclusive OR of the data read from the ROM 12 and the data read from the ROM 10, and this is read into the soft register 13 again. Here R
When OM12 is expressed as an arbitrary 8-bit binary number A', the memory address of the ROM12 specified by this A' is preliminarily set to αA' (however, αA' is the code vector and primitive element α corresponding to this binary number A'). By inserting the multiplier, the multiplier operates as a multiplier of α times. Furthermore, if ROMIQ represents an arbitrary 8-bit binary number of input data as B', then α224B' (however, (t2
24) 3' is the code vector corresponding to the binary number B' and the element α
224) by -4, α22
Works as a 4x multiplier. Thus, if you input shift register △ first, when Bo is input, shift register △
△ △ △ ・・・・・・+Ba) α+B2) α10B+ ) α10BO
] To △ △ △ = α224 (α31B,, 10α30B3o + ...
...+αB, 10Bo):S.

Therefore, the desired syndrome S is obtained. A similar circuit can be used by making the contents of ROM12 correspond to α2 and α3 instead of α mentioned above, and the contents of ROM10 corresponding to α4 and α672 instead of α224 mentioned above. A circuit that calculates the syndromes S2 and S3, respectively, can be obtained.Furthermore, by feeding back the contents of the shift register 13 as is to the circuit 11, excluding the ROM12 and IO, the syndrome S2 and S3 can be obtained.
A circuit for calculating o is obtained.

The syndrome So obtained in this way is stored in the So storage circuit 2 and supplied to the error correction execution circuit 7 via the correction execution control logic circuit 6. In addition, the obtained syndrome S
o to S3 are supplied to the syndrome all-zero determination circuit 5.

Now, in the circuit for determining 81 to S3 in FIGS. 4(a) to 4(C), shift registers 13, 17, and 21 are currently outputting syndromes S, to S3. Therefore, Figure 4 (
In the circuit for calculating Sl shown in a), data input manually from the data input line 100 is prohibited, and the shift clock supplied from the error position calculation circuit 4 is input to the shift register 13, and the number of shift clocks is defined as n. , each time the shift clock is input, the ROM 12 is set to the α power N6
The output of the shift register 13 becomes αnS. Similarly, in the circuit for determining S2 shown in FIG. 4(b), if the number of shift clocks is n, the output of the shift register 17 becomes α2n B 2 while the ROM 15 operates as an α2 multiplier. Similarly, in the circuit for calculating S3 shown in FIG. 4(C), if the number of shift clocks is n, the output of the shift register 21 is α3n since the ROM 20 operates as an α3 power K circuit.
It becomes S3.

In this way, after calculating the syndrome SQ%S3,
By prohibiting data input to the shift registers 13, 17, and 21 manually and inputting the same shift clock as in the calculation, it is possible to perform the calculations of the three equations (t"Sl, α2"82, α"S3, respectively). can.

In the above calculation, at the n-th shift clock, the outputs of the shift registers 13, 17.21 are αn S l, α2 n S2, respectively. α3 n S 3
Therefore, each shift register 13, 17, 2]
At the same time, the output of αns, =:so...
・(+6) αznB2= So−・・−・・・・+17)
Assuming that α3nS3 = 5o--・(+81) is satisfied, from formulas 03) and 06), formulas 041 and (+71), and formulas (19 and (1&), n=3l-j j=31-n・...09) The above three equations 111i1.07) and a symbol position J
can be requested from the claimant. In the embodiment, the syndrome comparison circuit 3 compares the syndrome So supplied from the So storage circuit 2 and αns supplied from the output 1 old of the syndrome calculation circuit 1, and further compares the syndrome So supplied from the output 102. α2 n B
2 and α3n1 supplied from output 103
33 (however, n≧0) and syndrome s.

A comparison is performed. Therefore, if there is one error, the four word data (so, αnS, , α2 "1S2°α3" input to the syndrome comparison circuit 3 as described above)
n B 3) all match. In this case, the syndrome comparison circuit 3 outputs a coincidence output 300, which is supplied to the error position calculation circuit 4 and the correction execution phrase logic 1 path 6.

When the error position calculation circuit 4 receives the coincidence output 300 from the syndrome comparison circuit 3, the error position calculation circuit 4 calculates the above-mentioned error symbol position j.
(==31=n) and outputs the j value. The output h 200 of the error position arithmetic circuit 4 uses a shift register that can be used in the syndrome arithmetic circuit 1 described above.
This is the shift clock used to find the error symbol position j. The value of j output from the circuit 4 is the correction execution side ft1
ljM is supplied to the logic circuit 6. This circuit 6 has the syndrome 5o-8 from the syndrome all zero judgment circuit.
Logic Jl+ is input from output 500 only when all of 3 are zero.

Now, the correction execution control logic circuit 6 controls the execution of error correction by the following logical operation based on the input power signal supplied as described above. First, the output 50 of circuit 5
If 0 is logic 11'', i.e. syndrome So~S
If 3 is all zero, it is assumed that there is no error regardless of other input signals, and error correction iE is not performed. At this time, the circuit 6 outputs a signal indicating that there is no error in this code block by setting the error 7 run nog output cuff 00 to be supplied to the subsequent stage circuit to logic "0".

Next, if the output 500 of circuit 5 is logic 10'', then ↑
It becomes like ゛. In this case, there must be an error, but if there is only one error, +1) ~ 110)
According to the relationship in the equation, all syndromes 5o-83 are not zero. In this case, the above comparison 06) ~ When the betting conditions are met, the syndrome comparison circuit 3 outputs a coincidence output 30
0 is output, and the error symbol position j is output from the 1 leakage position calculation circuit 4.

When these conditions are met, the error correction execution circuit 7 may be controlled to perform error correction on the j-th symbol using the 021-format error correction information So. At this time, the error flag output cuff 00 is set to logic "0" to output a signal indicating that there is no error in this code block as a result of correction.

If such a relationship does not hold, that is, if the coincidence output 300 is not obtained from the syndrome comparison circuit 3, the condition that the number of error symbols is one does not hold. Therefore, in this case, no correction is performed, and the error flag output cuff 00, which means that this code block contains an error, is set to logic "1".

Now, the error correction information Ej (So) subjected to the above control is supplied by the circuit 6 as an output 4oo, and the error symbol position information J is supplied as an output 401 to the error correction execution circuit 7.

It has a buffer to store at the symbol position. Adding the supplied error correction information Ej (So) to the symbol Bj at the position specified by the error symbol position specification information j among the symbols stored in this way using exclusive OR. Error correction is performed by After error correction in this manner, each symbol is supplied as an output 600 to a subsequent circuit together with the error flag output cuff 00.

In the practical example below, in order to make the explanation more concrete,
We have described in detail the case of using a Reed-Solomon code in which the code length N is 32.1, the number M of check symbols in a code block is 4, and the number of bits in each symbol is 8. It is clear that the inventive scheme is not limited to the values of N, M and K. In addition, circuit examples of various circuits that have been used in the past are shown as examples that cannot be realized, and the present invention is not limited to these. Still, the code block of the received input signal is △
△ △ Each symbol is B31 + B2O! ...You may input them in the order in which they are input in the first order of Bo. In this case, (16
) ~ α When the hammer equation is satisfied, equation (19) becomes j=n. Therefore, in the circuit configuration in this case, n is counted down from 31 in the illustrated example, whereas n may be counted up from zero.

As described above, when the present invention is used, 1
In a method that corrects an error of 1fA and issues an error flag when an error of 2 or more symbols is detected, all syndrome information up to the number of test symbols (M u + s) is effectively used to detect errors when generating syndromes. By performing these functions simultaneously, it is possible to provide a highly reliable decoding method that increases the processing speed and achieves the purpose with a simple circuit configuration. As a result, reliability and cost efficiency can be improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a diagram for explaining the sum of 1lxs used in this embodiment, and Fig. 3 (11 is the sign requirement expression of the operation used in this embodiment). FIG. 3(2) is a diagram for explaining the product calculation used in this embodiment, and FIG. 4 is a diagram showing an example of the internal circuit of the syndrome calculation circuit of this embodiment. l...Syndrome calculation circuit, 2...So storage circuit, 3...Syndrome comparison circuit, 4...Error position calculation circuit, 5...Syndrome all zero determination circuit, 6
... Correction execution control logic circuit, 7... Error correction execution circuit. Patent applicant: Shin Nippon Electric Co., Ltd. 2nd generation. ::・ A B AB Figure 3

Claims (1)

[Scope of Claims] A lead code having a code length of N (where N is an integer greater than M + E) generated from a generator polynomial obtained by the product of M (where M is a positive integer a) first-order polynomials. After receiving the Solomon code, M syndromes SO+Sl for the received code are obtained.
+...5M-1, and this computing means individually outputs syndromes So, Sl,...5.
A syndrome in which it is determined whether the outputs of the arithmetic means are equal or not each time the arithmetic operation is performed by cutting off the human power of the Ail code receiving code after the M-1 operation. a comparison means; an error position calculation means for counting the number of shift clocks given to perform the repetitive calculation and calculating the error position from the value; and whether the syndromes So, Sl, . . . SM-t are all zero syndrome-all-zero determination means for determining whether or not correction should be performed according to a predetermined algorithm in response to the output of the syndrome comparison means, the output of the error position calculation means, and the output of the syndrome-all-zero determination means; When determining and correcting the error position, the syndrome So is detected as error information to be weighed against the symbol at the position determined by the error position calculating means, and the syndrome So,
1 in the receiving number 41 based on S, ,...5y-t
A Reed-Solomon code decoding system comprising an error correction means which corrects the error when it detects that an error occurs in only one symbol, and outputs detection information indicating the existence of an error when an error of two or more symbols is detected.