KR100215807B1 - Error correcting apparatus and method for digital signal - Google Patents

Abstract

The present invention relates to an error correction apparatus and method for a digital signal that improves an erasure method using an error pointer, thereby reducing memory usage and improving an erasure correction capability. In particular, a memory having an 8-bit or 16-bit data width in one address is provided. By dividing the data storage area and the C2 error pointer area and storing the data and the C2 error pointer in separate addresses, respectively, and accessing them in their respective address spaces for error correction and transmission to the host computer, it improves practicality and eliminates waste of memory. If the error position is not located within the Q codeword and the number of P error pointers is not 2, the Q series error pointer corresponding to the currently processed Q codeword is set. While processing the word, the error position is not located within the P code word. If the number of Q error pointers is not 2, the P series error pointer corresponding to the currently processed P codeword is set, and then the process of processing the next codeword is repeated by a specified number of repetitions, thereby improving the eraser correcting ability.

Description

Device and method for error correction of digital signals

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to error correction of digital signals, and more particularly, to an apparatus and method for error correction of digital signals that improves an eraser method using an error pointer, thereby reducing memory usage and improving efficiency of erasure correction.

In a CD-ROM which records digital data on a disc for a compact disc (CD) reproducing apparatus, high reliability is required as the bit error rate is 10 ^-12 or less.

At this time, since the bit error rate of the CD itself is about 10 ^-9 , the CD-ROM has another error correction code which is completed in block units of 98 frames of the CD in addition to the error correction function of the CD itself. This other error correction code is an enemy code consisting of the P series and the Q series.

Error correction of such a conventional digital signal is disclosed in Japanese Laid-Open Patent Application No. 90-413508 (Domestic Application No. 91-23287) as shown in Figs.

Fig. 1 shows an example of a CD-ROM drive device, in which an appropriate code consisting of C1 series and C2 series of CD itself is added to each block data, and as a result, a signal subjected to EFM modulation or the like is transmitted to the CD reproducing apparatus 10. FIG. Is recorded on the disc 11 of FIG.

The signal recorded on the disc 11 is reproduced as an RF signal by the optical header 13, and the reproduced RF signal is output to the servo circuit 14 and the CD decoder 17 via the RF amplifier 15, respectively. .

The CD decoder 17 performs error correction of the CD itself by using the CIRC formed of the C1 code and the C2 code, and sets the C2 pointer corresponding to the data estimated that the error is not corrected to '1', thereby setting the CD-ROM. Output to the decoder 21 is for.

The CD-ROM decoder 21 is called 'Layered ECC' using the first corrected data and the C2 error pointer, the P series parity and the Q series parity outputted from the CD decoder 17. After the second error correction, the data estimated that the error cannot be corrected is set to '1' and the error detection is finally performed using the CRC code.

Then, the data after error correction, the pointer information, and the error detection result by the CRC code are transmitted to the external host computer through the interface (I / F) circuit 26.

Here, the buffer memory 22 is an external memory that stores one byte of data and a one-bit C2 error pointer corresponding thereto.

FIG. 2 is a flowchart showing a series of error correction operations performed between the decoder 17 for CD, the CD-ROM decoder 21, and the I / F circuit 26 mentioned in FIG. In step 17), the C2 series correction is made after the C1 series correction (steps 201 and 202) (steps 203 and 204), and the C2 error pointer (bits indicating the byte determined to have an error after the correction) and data are generated. -Supply to ROM decoder 21 (step 205).

The CD-ROM decoder 21 corrects the Q series and the P series based on the C2 error pointer (steps 206 to 209), and finally changes the C2 error pointer again according to the result. A detection operation is performed (step 210). The result is then transferred to the host computer with the C2 error pointer (step 211).

3 is a flowchart illustrating a conventional error correction method of the Q series, and FIG. 4 is a flowchart illustrating an error correction method of the P series, both of which are positions of the error calculated in the error correction step and an error correction result of the previous step. The error byte to be finally corrected is determined by using the position of the error pointer.

In particular, the Q series error correction strictly compares the position of the calculated error with the position of the C2 error pointer supplied by the CD-ROM decoder 21, and when the two positions coincide or there is no C2 error pointer in other data. Only 1 byte of error correction is required. In other cases, an error pointer is set so that a maximum of 2 bytes can be corrected during error correction of the P series. As a result, the Q series operates mainly on error detection and the P series operates on error correction.

In addition, the C2 error pointer supplied from the CD decoder 17 is used in the error correction process of the Q series and the P series, and the original error pointer value is changed according to the error correction result.

However, the conventional error correction apparatus described above has an optimum correction efficiency when the buffer memory 22 has a data width of 9 bits (8 bits data + 1 bit C2 error pointer).

That is, since the C2 error pointer is allocated 1 bit for 1 byte of data, when the data and the corresponding C2 error pointer are stored in one address space using a memory having a 9-bit data width, an error correction circuit is constructed. Is convenient, but in today's CD-ROM drivers that use a large amount of data buffer memory (typically 256K bytes or more), obtaining 256K bytes of memory with 9 bits of data width is of course costly and of this type. Semiconductor companies that produce memory are also rare and therefore not practical.

In addition, using a memory having a data width of 16 bits instead of a 9-bit memory causes a waste of memory and a price increase.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to use a Q series and P series error pointer while using a memory having a data width of 16 bits to access 8 or 2 bytes at a time in one address at a time. An error correction apparatus and method for effectively performing erasure correction and iterative correction by using

A feature of an error correction apparatus according to the present invention for achieving the above object is that the address of the data storage area and the C2 error point storage area is divided into an external buffer for storing the correction data and the C2 error pointer at each address. With memory,

A memory interface for providing a read / write signal and a corresponding address to the buffer memory, a codeword for outputting a read / write signal to the memory interface and generating an address, and an order within each codeword. A controller for outputting an index, a memory address for receiving a codeword type and an index from the controller of the data storage area and the C2 error pointer storage area of the buffer memory, and generating an address required for the buffer memory and outputting it through a memory interface; An address generator, a syndrome calculation unit for calculating a syndrome when all data bytes in a codeword are read from a buffer memory through the memory interface, and a one error position discriminator for determining one error position using an output of the syndrome calculator. , The sind The error value generator that generates the error value using the output of the calculator, and the process of setting and storing the error pointer in the P codeword corresponding to the data for which the C2 error pointer is set is performed for all the codeids. The P series error discrimination unit for summing the 2 error positions and determining the 2 error positions to use for erasure correction of the Q codeword, and the error positions obtained by the 1 error position discriminator at the time of Q codeword error correction are not present in the codeword. If the number of error pointers obtained by the P series error discriminating unit is greater than 2, the process of setting and storing the Q series error pointers according to the codeids of the Q codewords is performed for all the codeids, and then the number of the error pointers is summed and 2 error positions A Q series error discrimination unit for discriminating the P codeword by erasing the P codeword, and If the data of the corresponding address is read from the buffer memory by outputting the information to the memory address generator using the index information, the error corrector performs an exclusive OR with the error value, corrects the error, and stores the data in the corresponding address of the buffer memory. When error correction is completed for the codeword, the process of repeating the same operation for the P codeword is repeatedly performed a specified number of times.

In addition, when the number of error pointers obtained by the P series error discriminating unit does not exist in the codeword when the error position determined by the first error position discriminator is present in the Q codeword error correction, two errors corresponding to two error positions. After each value is obtained from the error value generator, an exclusive laser OR is sequentially performed on the data of the corresponding address stored in the buffer memory to perform erasure correction.

In addition, when the error position determined by the first error position discriminator does not exist in the codeword at error correction of the P codeword, if the number of error pointers obtained by the Q series error discrimination unit is 2, two errors corresponding to two error positions are obtained. After each value is obtained from the error value generator, an exclusive laser OR is sequentially performed on the data of the corresponding address stored in the buffer memory to perform erasure correction.

A feature of the error correction method of digital data according to the present invention is a method of error correction of digital data which reads data from an optical disk, performs error correction on C1 series and C2 series, and outputs correction data and a C2 error pointer. If all data bytes in the Q codeword are read from an external buffer memory in which the addresses of the data storage area and the C2 error point storage area are separated, calculating a syndrome to determine an error, and if there is no error, the next Q Proceeding with the codeword and determining that there is an error, obtaining an error position; determining whether the error position obtained in the step belongs to a position in the codeword; and in this step, the error position exists in the Q codeword. If it is determined that 1 error location and error value are obtained, correct 1 error and Storing in the memory; determining whether the number of P error pointers is two if the error position is not present in the Q code word; and if the number of P error pointers is two, Obtaining an error value, correcting 2 errors and storing them in a buffer memory, and if it is determined in the above step that the number of P error pointers is not 2, sets a Q series error pointer corresponding to the Q codeword currently being processed, and then It includes the step of performing a word processing, if the error correction is completed for the Q code word is to repeat the same operation for the P code word.

A feature of the error correction method of digital data according to the present invention is a method of error correction of digital data which reads data from an optical disk, performs error correction on C1 series and C2 series, and outputs correction data and a C2 error pointer. If all data bytes in the P codeword are read from an external buffer memory in which the addresses of the data storage area and the C2 error point storage area are separated, calculating a syndrome to determine an error, and if there is no error, the next P Proceeding to the codeword and determining that there is an error, obtaining an error position, determining whether the error position obtained in the step belongs to the codeword, and determining that the error position exists in the P codeword in the step. 1 error position and error value is calculated, 1 error is corrected and then stored in the buffer memory. Storing; if determining that the error position does not exist in the P codeword, determining whether the number of Q error pointers is two; and if the number of Q error pointers is two in this step, two error positions and error values. Obtain a 2 error, correct the error, and store it in the buffer memory; and if it is determined in the step that the number of Q error pointers is not 2, the P series error pointer corresponding to the currently processed P codeword is set, and then It comprises a step of performing a process.

1 is a block diagram showing a conventional error correction device for digital signals

2 is a flowchart showing the overall operation of the conventional method for error correction of digital signals.

3 is a flowchart illustrating an error correction process of a Q series codeword of a conventional digital signal.

4 is a flowchart illustrating an error correction process of a P series codeword of a conventional digital signal.

5 is a block diagram illustrating an error correction apparatus of a digital signal according to the present invention.

Fig. 6 is a diagram showing an error correction data structure in the data format for CD-ROM.

Fig. 7 shows the relationship between codewords and addresses in the case of a CD-ROM;

8A shows the structure of a Q codeword when codeid = 0

8B shows the structure of a P codeword when codeid = 0

9 is a detailed block diagram of the decoder for CD-ROM of FIG.

FIG. 10 is a diagram illustrating an example of a map structure of a buffer memory of FIG. 9.

11 is a flowchart illustrating an error correction process of a Q series codeword of a digital signal according to the present invention.

12 is a flowchart illustrating an error correction process of a P series codeword of a digital signal according to the present invention.

13 is a flowchart showing the overall operation of the error correction method of a digital signal according to the present invention.

Explanation of symbols for the main parts of the drawings

50: host interface 51: optical disk

52: optical pickup 53: RF amplifier

54: CD decoder 55: D / A converter

56: spindle motor 57: servo circuit

58: control microcomputer 59: CD-ROM decoder

60: buffer memory 61: memory interface

62: memory address generator 63: P series error pointer setter

64: P series error pointer register

65: Q series error pointer setter

66: Q series error pointer register

67,70: 2 Error position discriminator

68,69: error pointer adder 72: syndrome calculator

73: 1 error position discriminator 74: error value generator

75: exclusive OR circuit 76: controller

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a schematic diagram of a CD-ROM drive system according to the present invention, including an optical disk 51, an optical pickup 52 for irradiating a light beam to the optical disk 51 and converting the reflected beam into an RF signal; An RF amplifier 53 for amplifying the RF signal output from the pickup 52, a CD using a Cross Interleaved Reed Solomon Code (CIRC), which receives the signal amplified by the RF amplifier 53 and becomes a C1 code and a C2 code. The decoder for CD 54 which performs its own error correction and sets the C2 error pointer corresponding to the data estimated that the error is not corrected to '1', and the data corrected by the CD decoder 54 are analog. Digital / analog (D / A) converter 55 for converting the power to an audio output terminal and supplying it to the audio output terminal, the spindle motor 56 for rotating the disk 51, and the spindle motor 56 for controlling optical Rotate the disk 51 and remove the optical pickup 52 at the same time. For example, a servo circuit 57 for supplying a necessary signal to the RF amplifier 53, a control microcomputer 58 for controlling servo and error correction, data output from the CD decoder 54, and a C2 error pointer are input. CD-ROM decoder 59 for performing error correction called 'layer ECC', data storage area and address of C2 error point storage area are distinguished, and data provided through the CD-ROM decoder 59 and C2. A buffer memory 60 for storing an error pointer, and a host interface 50 for transmitting the data corrected by the CD-ROM decoder 59 to a host computer.

In FIG. 5 configured as described above, an appropriate code consisting of the C1 series and the C2 series of the CD itself is added to the optical disk 51, and as a result, a signal subjected to EFM modulation or the like is recorded.

The signal recorded on the disc 51 is reproduced as an RF signal by the optical pickup 52, and the reproduced RF signal is amplified by the RF amplifier 53 and then output to the CD decoder 54.

The CD decoder 54 performs error correction of the CD itself by using a CIRC (Cross Interleaved Reed Solomon Code) consisting of a C1 code and a C2 code, and sets a C2 pointer corresponding to data estimated to have not been corrected. ', And output to the D / A converter 55 and the CD-ROM decoder 59.

The D / A converter 55 converts the error-corrected data from the CD decoder 54 into an analog output to an audio output terminal, and the CD-ROM decoder 59 is 1 in the CD decoder 54. Second-order error correction, called 'Layered ECC', is performed using the second corrected data, the C2 error pointer, the P series parity, and the Q series parity.

At this time, the CD-ROM decoder 59 stores the data and the C2 error pointer supplied by the CD decoder 54 to an external buffer memory 60 in which the addresses of the data storage area and the C2 error point storage area are separated. The data is stored and used for error correction, and the result is transmitted to the host computer through the host interface 50.

The map structure of the buffer memory 60 is as shown in FIG.

That is, the memory map is largely divided into two areas, one as a data storage area and the other as a C2 error point storage area.

The data storage area is stored in units of 2352 bytes (the unit of one sector recorded on the optical disc is 2352 bytes in the CD-ROM). The first address to be stored is indicated by SECBASE.

The C2 error point storage area is stored in units of 294 bytes (one C2 error pointer is input per 1 byte of data, so 294 bytes of data are required for 2352 bytes of data). Point to C2POBASE.

At this time, the SECBASE and C2POBASE can be supplied from the control microcomputer 58 or the like.

Thus, data and C2 error pointers necessary for error correction and transfer to the host computer can be accessed in the respective address spaces of the buffer memory 60.

On the other hand, the servo circuit 57 controls the spindle motor 56 to rotate the optical disk 51 and at the same time to control the optical pickup 52 to supply the necessary signal to the RF amplifier 53, the control microcomputer 58 ) Controls servo and error correction.

At this time, the configuration of data processed by the CD-ROM decoder 59 is as shown in FIG. That is, one block of the CD-ROM is composed of 2352 bytes of data, and the details of the data are initially except for 12 bytes of sync data (addresses 0 to 11), for example, data from addresses 12 to addresses 2351. Contains the original data and Q and P parity for error correction.

At this time, the parity of the data from the address 12 to the address 2075 is recorded from the address 2076 to the address 2247, and the parity of the data from the address 12 to the address 2247 including the P parity is from the address 2248 to the address 2351. Is recorded until.

This configuration corresponds to Mode 1 and Mode 2 Form 1 of the type of CD-ROM data, and this type of data is error correctable data.

FIG. 7 shows a correlation between the structure of the error correction codeword and the remaining address space except for the sync 12 byte space in the case of the CD-ROM.

Since the sync 12 bytes are excluded, P and Q parity are generated using the same type of algorithm for each, starting with address 12 and divided into even-numbered address space and odd-numbered address space.

In this case, the P codeword is addressed from top to bottom as shown in FIG. 7, the Q codeword is addressed in an oblique direction (from the upper left to the lower right), and FIG. 8 shows an example of the P codeword and the Q codeword. It is showing.

In this case, the P codewords are each column of 24 rows x 43 columns, and the Q code words are sequences that diagonally transverse the array of 24 rows x 43 columns. That is, two bytes of P parity are added to 24 bytes of normal data for each of those 43 columns, and two bytes of Q parity to 43 bytes of data (including two bytes of P parity) in the oblique direction. Is added.

This codeword produces the following result:

Q codewords: 26 in all (codeid = 0, .., 25), length of codeword is 45 (index = 0, .., 44)

P codewords: all 43 (codeid = 0, .., 42), codeword length 26 (index = 0, .., 25)

In this case, since the Q codeword and the P codeword include two bytes of Q and P parity, respectively, an error of one byte can be corrected correctly, and the position of the error is known in advance by a pointer even for an error of two bytes. Can correct these errors accurately.

Syndrome S0 and S1 can be obtained by performing the same operation as the following Equation 1 on the codeword.

In Equation 1, r denotes byte data in each codeword, and i, which indicates the order of data, is the same as an index in the codeword structure of FIG. 8, i = 0 is equal to the case where the index is 0, and i = n -1 corresponds to the case where the index is 44 (Q codeword case) or the index is 25 (P codeword case) in FIG.

In this way, when the syndromes S0 and S1 are obtained, error correction can be performed as follows.

When both S0 and S1 are 0: no error

When S0 is not 0 or S1 is not 0: If there is an error

If there is an error in the above, an error value and an error position can be obtained as in Equation 2 below.

Error value = S0, error location = S1 / S0

At this time, if the obtained error position does not exist in the codeword, the state cannot be corrected, or if two error positions in the codeword are known by the C2 error pointer, the error equation is X1 and X2. Use 3 to get the error value.

In this way, the error location and error value can be known, and error correction can be performed. All the four arithmetic operations so far are arithmetic operations defined in a mathematically defined aggregate called Galois Field.

The error correction described here is basically described in detail in the Yellow Book (ISO / IEC 10149), which is an international standard of the CD-ROM, and a general textbook on error correction, and thus a detailed description thereof will be omitted.

9 is a detailed block diagram of a decoder for a CD-ROM according to the present invention.

9, a memory interface 61 for providing a read / write signal and a corresponding address to the buffer memory 60, and a codeword for outputting a read / write signal to the memory interface 61 and generating an address. A controller 76 for outputting an index indicating the type of codeid and an order within each codeword, and a head of a data storage area and a C2 error pointer storage area of the buffer memory 60 output from the control microcomputer 58; A memory address generator 62 which receives the type and the index of the codeword from the address and the controller 76 and generates an address necessary for the buffer memory 60 and outputs it through the memory interface 61; A syndrome calculation unit 72 for calculating a syndrome when all data bytes in one codeword are read from the buffer memory 60 through 1 error position discriminator 73 for determining 1 error position using the output of the calculator 72, an error value generator 74 for generating an error value using the output of the syndrome calculator 72, and C2. A P series error pointer setter 63 for setting an error pointer to a P codeword corresponding to data in which the error pointer is set, and a P series error for storing the error pointer set in the P series error pointer setter in a corresponding bit. A two error position discriminator 67 for discriminating two error positions by using a pointer register 64, a P series error pointer stored in the P series error pointer register 64, and outputting the two error positions to the controller 76; An error pointer number adder 68 that adds the number of P series error pointers stored in the series error pointer register 64 to the controller 76, and the first error position discriminator 73 at the time of Q codeword error correction;Q series error pointer setter which sets the Q series error pointer according to the codeid of the Q code word if the number of error pointers obtained by the error pointer number adder 68 exceeds 2 when the position is not present in the code word. ), A Q series error pointer register 66 for storing the error pointer set in the Q series error pointer setter 65 in a corresponding bit, and a Q series error pointer stored in the Q series error pointer register 66. 2 error position discriminator 70 for determining the 2 error positions and outputting the result to the controller 76 and the number of Q series error pointers stored in the Q series error pointer register 66 and outputting the result to the controller 76. The pointer number summer 69 is comprised.

In this configuration shown in Fig. 9, the memory interface 61 receives signals supplied from the decoder 54 for CD according to the input timing signals BCLK and LATCH supplied from the control microcomputer 58, that is, data and C2 error pointers. 60).

In this case, the controller 76 requests a write signal through the memory interface 61, and the memory address generator 62 supplies a storage address of the buffer memory 60 through the memory interface 61.

The head address necessary for storing data and the C2 error pointer in the buffer memory 60 is supplied from the controlling microcomputer 58, where the data storage area is data from SECBASE, and the C2 error pointer storage area is C2POBASE to C2 error pointers. Save as.

Then, the controller 76 receives the correction start command (ECCSTART) from the control microcomputer 58, stores a codeid indicating the type of codeword to be corrected, and an index indicating an order within each codeword. ), The memory address generator 62 generates the address of the buffer memory 60 using the codeid and the index output from the controller 76 and then the buffer memory 60 through the memory interface 61. To feed.

At the same time, a read request signal is output from the controller 76 to the memory interface 61, and the memory interface 61 reads the data stored at the address provided by the memory address generator 62 from the buffer memory 60 to the syndrome. Output to calculator 72.

The syndrome calculator 72 calculates syndromes S0 and S1 when all data bytes in one codeword are read and supplies them to one error position discriminator 73 and error value generator 74 to obtain the error position and error value, respectively. .

At this time, the error value obtained by the error value generator 74 is input to the exclusive OR circuit 75 to perform a corrective operation, and the error position obtained by the one error position discriminator 73 is input to the controller 76 to obtain It determines whether the location of the error belongs to the codeword.

If the location of the obtained error is within the codeword, the controller 76 outputs the address to the memory address generator 62 using the obtained error location as index information, and outputs the address that the memory address generator 62 attempts to correct. And a read request signal to the memory interface 61 at the same time.

The memory interface 61 reads data from the corresponding address of the buffer memory 60 and outputs the data to the exclusive OR circuit 75.

The exclusive OR circuit 75 corrects the data by performing an exclusive OR on the error value output from the error value generator 74 and the data read from the buffer memory 60, and the corrected data is stored through the memory interface 61. It is stored in the buffer memory 60 again.

That is, when the exclusive OR is obtained from the exclusive OR circuit 75, the controller 37 outputs a write request signal to the memory interface 61, and a memory address generator (B) through the memory interface 61 to the buffer memory 60. The correction data output from the exclusive OR circuit 75 is stored in the address output from 62.

If the above operation is performed for all Q codewords, the same operation is repeated for the P codeword. If the repeat correction mode is not set, the entire error correction operation is terminated. If the repeat correction mode is used, the error correction operation is performed for a specified number of repetitions. Perform.

At this time, the RPTON signal input to the controller 37 indicates the presence or absence of the repeat correction mode, the RPTCNT signal indicates the number of repeat correction times, and is provided from the control micom 58.

Accordingly, the controller 37 outputs control signals to perform the above-described error correction operation by the specified repetition correction number RPTCNT if the repetition correction mode RPTON is active.

On the other hand, when data and a C2 error pointer are input from the CD decoder 54, the P series error pointer setter 63 sets one error pointer to the P codeword to which the data to which the C2 error pointer is set corresponds. The P series error pointer register 64 stores this.

For example, in the data shown in Fig. 6, the CD decoder 54 with the C2 error pointer set at the first data (corresponding to address 12 in one sector) and the third address (corresponding to address 14 in one sector) after 12-byte sync. Input from the P series error pointer setter 63, the P series error pointer setter 63 determines that the first data corresponds to a P codeword with codeid = 0, so that the first bit of the P series error pointer register 64 An error pointer is set at, and it is determined that the third data corresponds to a P codeword having codeid = 1, so that the error pointer is set at the second bit of the P series error pointer register 64.

Here, the third data is codeid = 1 because data including parity is divided into even and odd layers to generate P and Q parity using the same algorithm for each.

Therefore, when the C2 error pointer is set and the C2 error pointer is also set, the codeid of the P codeword to which the data pointed to by the C2 error pointer belongs is determined, and the corresponding P series error pointer register 64 is determined. Set an error pointer to the bit of).

In this case, when it is determined that the error position, which is the output of the one error position discriminator 73, does not exist in the codeword at the time of error correction of the above described Q codeword, the number of bits set in the P series error pointer register 64 When the output of the error pointer number adder 68 that sums up is 2, it is possible to perform erasure correction to correct two error bytes.

That is, when the output of the error pointer number adder 68 is 2, two error positions X1 and X2 can be known from the 2 error position discriminator 67, so that the controller 76 applies the error correction method described above. After obtaining two error values corresponding to the two error positions, the error positions are supplied to the memory address generator 62 as index information so that the memory address generator 62 generates the address of the buffer memory 60 to be corrected.

In addition, the obtained error value is output to the exclusive OR circuit 75 through the error value generator 74, and the process is sequentially applied to the two error positions and the two error values. 2 error correction can be performed in the same process.

On the other hand, if the error position that is the output of the one error position discriminator 73 does not exist in the codeword and the output of the error pointer number adder 68 is also not 2, it is determined that error correction cannot be performed. The Q series error pointer setter 65 controls the error pointer to be set in the bits of the Q series error pointer register 66 according to the codeid of the Q code word.

The result is used for erasure correction of the P codeword after all Q codeword correction operations are completed.

The error correction processing of the P code word is also performed in the same manner.

That is, when it is determined that the error position that is the output of the one error position discriminator 73 does not exist in the codeword at the time of error correction of the P codeword, the number of bits set in the Q series error pointer register 66 is added up. When the output of the error pointer number adder 69 is two, it is possible to perform erasure correction for correcting two error bytes.

The difference is that in the error correction of the above Q codewords, the number of error pointers of the P codewords used in the erasure correction step is 43 (assuming that only error corrections for even addresses are assumed for convenience and all error corrections for odd addresses are included. The error correction method is 86 times that of 2 times, and the error correction method is exactly the same as that of the even address case, and is not necessary for the detailed description of the error correction method. Is composed of 43 bit registers. However, in error correction of P codewords, the total number of Q codewords is 26 (as is 52 in the case of odd address cases), so that the Q series error pointer register 66 is a 26 bit register. It is composed.

If an error cannot be corrected, the error pointer is set to a bit corresponding to the codeid of the P codeword processed by the P series error pointer register 64 through the P series error pointer setter 63. .

The error pointer thus set is used as an eraser when the Q codeword is corrected again in the case of repeat correction.

The error correction method described so far does not read the C2 error pointer from the external buffer memory 60 when erasing the error. Instead, each codeword (45 bytes for the Q codeword and 26 for the P codeword) is used. By providing an error pointer of 1 bit corresponding to each byte), it is possible to have an erasure correction effect without accessing the external buffer memory 60 each time.

11 is a flowchart illustrating an error correction method of a Q-series codeword according to the present invention, and shows a circuit configuration of FIG.

First, when all data bytes in one Q codeword, i.e. 45 bytes, are read (step 501), syndromes S0 and S1 are calculated (step 502).

If it is determined in step 502 that the syndrome S0 = S1 = 0, it is determined that there is no error, and the process proceeds to the next Q codeword.

That is, if it is determined in step 504 that all Q codewords have been processed, and if it has been determined that all Q codewords have been processed, the error correction for the Q codeword is finished, and if it is determined that the processing is not finished for all Q codewords. Returning to step 501, the data bytes of the next Q codeword are read to calculate syndromes S0 and S1.

On the other hand, if it is determined in step 503 that syndrome S0 = S1 = 0, 1 error position discriminator 73 is operated to obtain an error position (step 505).

In this case, the error position may be obtained by the syndrome S1 / S0 calculated in step 502.

It is discriminated whether or not the error position obtained in the step 505 falls within a position in the codeword, that is, the error position falls from 0 to 44, which is the index range of the Q codeword (step 506).

If it is determined in step 506 that the error position exists in the Q codeword, an error value is obtained according to the above-described one error correction method, and one error is corrected (step 507).

That is, if it is determined that the error position exists in the Q code word, the error value generator 74 generates the error value by applying the above equation (3), and then performs an exclusive OR on the original data in the exclusive OR circuit 75 to determine the error. Correct it.

The data thus corrected is stored in the external buffer memory 60 through the memory interface 61 under the control of the controller 76.

On the other hand, if it is determined in step 506 that the error position does not exist in the Q codeword, that is, if the error position is 45 or more, the number of P error pointers is determined (step 508).

If the number of P error pointers is two in step 508, two error positions and two error values are obtained according to the two error correction methods described above (step 509).

That is, when the output of the error pointer number adder 68 is 2, two error positions X1 and X2 can be known from the 2 error position discriminator 67, so that the two error positions correspond to the two error positions using Equation 3 described above. After obtaining two error values, the error position is provided as index information to the memory address generator 62 to generate an address to be corrected, and the obtained error value is output to the exclusive OR circuit 75 through the error value generator 74. do.

Applying this process sequentially to two error locations and two error values allows two error corrections to be performed.

The corrected data is again stored in the external buffer memory 60 via the memory interface 61.

On the other hand, in step 508, if the number of P error pointers is not two, it is determined that error correction cannot be performed, and after setting the Q sequence error pointer corresponding to the currently processed Q code word (step 510), Processing is performed (step 504).

The Q error pointer set in the Q codeword is used for erasure correction of the P codeword after the Q codeword correction operation is completed.

That is, Fig. 12 is a flowchart showing an error correction method of a P series code word according to the present invention. When all data bytes, that is, 26 bytes in one P code word are first read (step 601), syndromes S0 and S1 are shown. Is calculated (step 602).

If it is determined in step 602 whether the syndrome S0 = S1 = 0, it is determined that there is no error, and the process proceeds to the next P codeword.

That is, if it is determined in step 604 that all the P codewords have been processed, and if it has been determined that all of the P codewords have been processed, the error correction for the P codeword is finished, and if it is determined that the processing has not been completed for all the P codewords Returning to step 601, the data bytes of the next P codeword are read to calculate syndromes S0 and S1.

On the other hand, if it is determined in step 603 that the syndrome S0 = S1 = 0, it is determined that there is an error, and 1 error position discriminator 73 is operated to obtain an error position (step 605).

In this case, the error position in step 605 may be obtained by S1 / S0 of syndromes S0 and S1 calculated in step 602.

It is discriminated whether or not the error position obtained in step 605 belongs to a position in the codeword, that is, the error position falls from 0 to 25, which is the index range of the P codeword (step 606).

If it is determined in step 606 that the error position exists in the P codeword, an error value is obtained according to the one error correction method described above, and one error is corrected (step 607).

That is, if it is determined that the error position exists in the P codeword, the error value generator 74 generates the error value by applying the above equation (3), and then performs an exclusive OR on the original data in the exclusive OR circuit 75 to determine the error. Correct it.

The data thus corrected is stored in the external buffer memory 60 through the memory interface 61 under the control of the controller 76.

On the other hand, if it is determined in step 606 that the error position does not exist in the P codeword, that is, if the error position is 26 or more, the number of Q error pointers is determined (step 608).

If the number of Q error pointers is two in step 608, two error corrections are performed by calculating an error value according to the two error correction methods described above (step 609).

That is, when the output of the error pointer number adder 69 is 2, the two error positions X1 and X2 can be known from the 2 error position discriminator 70 and thus correspond to the two error positions using Equation 3 described above. After obtaining two error values, the error position is provided as index information to the memory address generator 62 to generate an address to be corrected, and the obtained error value is passed to the exclusive OR circuit 75 through the error value generator 74. Output

Applying this process sequentially to two error locations and two error values allows two error corrections to be performed.

The corrected data is again stored in the external buffer memory 60 via the memory interface 61.

On the other hand, in step 608, if it is determined that error correction cannot be performed when the number of Q error pointers is not two, the P series error pointer corresponding to the currently processed P code word is set (step 610), and then Processing is performed (step 604).

The P error pointer set in the P codeword is used for erasure correction of the Q codeword after the P codeword correction operation is completed.

Fig. 13 is a flow chart briefly showing the overall operation of the error correction method according to the present invention. When the error correction start signal ECCSTART is input to the controller 76 from an external control device such as a control microcomputer 58, the Q series error pointer. After all of the set Q series error pointer registers 66 are cleared (step 701), Q codeword processing is performed as shown in Fig. 11 (step 702).

Here, the reason for clearing all currently set Q series error pointers is to eliminate the error pointers for the codewords that are corrected according to the iteration correction.

After all processing for the Q codeword is completed, the P series error pointer register 64 in which the P series error pointer is set is similarly cleared (step 703), and then P code word processing is performed as shown in FIG. 704).

Then, when the processing for all P codewords is finished, error detection is performed (step 705) to determine whether an error exists (step 706).

If it is determined in step 706 that no error exists, all error correction processes are terminated. If it is determined that an error exists, it is determined whether the error is in the repeat correction mode (step 707).

If it is determined in step 707 that the process is not in the repeat correction mode, if all errors are present, the process of error correction is completed. If it is determined that the repeat correction mode is performed, it is determined whether the error correction has been performed by the number of iterations. If the number of times has not been repeated, the process returns to the step 701 (step 708).

That is, the number of repetitions increases by one when both error correction of the Q series codeword and error correction of the P series codeword are performed.

At this time, the Q codeword refers to the P series error pointer when erasing the eraser, and the P codeword refers to the Q series error pointer when erasing the eraser, and the number of repetitions corrects the error and clears the P and Q series error pointers. Repeat the setting.

As described above, according to the error correction apparatus and method for digital data according to the present invention, a memory having a data width of 16 bits is used to access 8 bits or 2 bytes at a time in one address. The data is divided into a data storage area and a C2 error pointer area, and data is stored in a 2352 byte unit in the data storage area, and a C2 error pointer is stored in a 294 byte unit in the C2 error pointer area. By accessing data and C2 error pointers from each address space of the buffer memory, the CD-ROM driver using a large data buffer memory (typically 256K bytes or more) increases the practicality and eliminates the waste of memory. Saves.

In processing Q codewords, one codeword is read and a syndrome is calculated to determine an error position. If the error position is located within the codeword, one error is corrected according to the one error correction method, and the error code is not located within the codeword. If the number of P error pointers is 2, two error corrections are performed according to the 2 error correction method.If the number of P error pointers is not 2 and the number of P error pointers is not 2, after setting the Q series error pointers corresponding to the currently processed Q codewords, After the processing of the Q codeword, when the processing of the P codeword is completed, one codeword is read and the syndrome is calculated to determine the error position. 1 Correct the error, and if the number of Q error pointers is not 2 within the codeword, perform 2 error corrections according to the 2 error correction method. If the number of Q error pointers is not 2 and not located within the word, the P series error pointer corresponding to the P codeword currently being processed is set, and the process of processing the next codeword is repeated by a specified number of repetitions to correct the error. Improve the eraser correction ability.

Claims (14)

With optical disc, An optical pickup for irradiating the optical disk with light and detecting reflected light to read data; A CD decoder for performing error correction on the C1 series and the C2 series of data read out from the optical pickup to output correction data and a C2 error pointer; A control microcomputer for controlling the optical disk rotation and error correction; A CD-ROM decoder which receives data and a C2 error pointer from the CD decoder and performs error correction on a P codeword and a Q codeword; A digital signal comprising an external buffer memory for storing the data provided through the CD-ROM decoder and the C2 error pointers at respective addresses, the addresses of which are stored in the data storage area and the C2 error point storage area. Error correction device. The decoder of claim 1, wherein the decoder for CD-ROM is A memory interface for providing a read / write signal and a corresponding address to the buffer memory; A controller for outputting a read / write signal to the memory interface and outputting a codeid required for address generation and an index representing an order within each codeword; A memory address generator that receives a head address of a data storage area and a C2 error pointer storage area from the control micom, receives a codeword type and an index from a controller, and generates an address required for a buffer memory and outputs the address to a memory interface; , A syndrome calculation unit for calculating a syndrome when all data bytes in one codeword are read from the buffer memory through the memory interface; A 1 error position discriminator for discriminating 1 error position using an output of the syndrome calculator, An error value generator for generating an error value using an output of the syndrome calculator; If the error position determined by the first error position discriminator belongs to the codeword, the controller outputs the error position as index information to the memory address generator. When data of the corresponding address is read from the buffer memory, an exclusive logical sum is performed with the error value. An error corrector for correcting the error and storing the error at a corresponding address in the buffer memory. And error correction for the Q codeword is repeated for the P codeword. The method of claim 2, A P series error pointer which performs the process of setting and storing an error pointer in the P codeword corresponding to the data in which the C2 error pointer is set, for all codeids; An error pointer number adder for adding up the number of error pointers stored in the P series error pointer unit and outputting the sum to the controller; It is further provided with a 2 error position discriminator for determining the 2 error position using the output of the syndrome calculator to output to the controller, An error correction apparatus for digital signals characterized in that an error is corrected according to the output of the error pointer number adder if the error position obtained by the one error position discriminator does not exist in the codeword during error correction of a Q codeword; . The method of claim 3, wherein If the error position obtained by the first error position discriminator at the time of Q codeword error correction is not present in the codeword and the output of the error pointer number adder is 2, it corresponds to the two error positions obtained by the second error position discriminator. And calculating two error values from the error value generator and sequentially performing exclusive OR with the data of the corresponding address stored in the buffer memory to perform erasure correction. The method of claim 3, wherein If the error position obtained by the 1 error position discriminator does not exist in the codeword when correcting the Q codeword error, and the output of the error pointer number adder is not 2, the Q series error pointer according to the codeid of the Q codeword is set. Q series error pointer section which performs the memorization process for all codeids, An error pointer number adder for adding up the number of error pointers stored in the Q series error pointer unit and outputting the sum to the controller; It is further provided with a 2 error position discriminator for determining the 2 error position using the output of the syndrome calculator to output to the controller, And an error correction operation is performed according to the output of the error pointer number adder if the error position obtained by the one error position discriminator does not exist in the codeword at the time of error correction of the P code word. The method of claim 5, If the error position obtained by the first error position discriminator at the time of error correction of the P codeword does not exist in the codeword and the output of the error pointer number adder is 2, it corresponds to the two error positions obtained by the second error position discriminator. And obtaining two error values from the error value generator, and correcting the error by sequentially ORing the data with the corresponding address stored in the buffer memory. The method of claim 5, When the error correction of the P codeword does not exist in the codeword, the error position obtained by the 1 error position discriminator does not exist in the codeword, and the output of the error pointer number adder is not 2. And setting and storing the P series error pointers according to the codeids for all the codeids to be used for the next Q codeword erasure correction. The method of claim 2, wherein the controller And a control signal is output to perform error correction on the Q codeword and the P codeword by the specified number of repetitions in the repetitive correction mode. An error correction apparatus for digital data that reads data from an optical disk, performs error correction on the C1 series and C2 series, and outputs correction data and a C2 error pointer. An external buffer memory in which the addresses of the data storage area and the C2 error point storage area are divided to store the correction data and the C2 error pointer at respective addresses; A memory interface for providing a read / write signal and a corresponding address to the buffer memory; A controller for outputting a read / write signal to the memory interface and outputting a codeid required for address generation and an index representing an order within each codeword; A memory address generator for generating an address required for a buffer memory by receiving a head address of a data storage area of the buffer memory, a head address of a C2 error pointer storage area, and a codeword type and an index from a controller, and outputting an address required through a memory interface; A syndrome calculation unit for calculating a syndrome when all data bytes in one codeword are read from the buffer memory through the memory interface; A 1 error position discriminator for discriminating 1 error position using an output of the syndrome calculator, An error value generator for generating an error value using an output of the syndrome calculator; After setting the C2 error pointer and setting the error pointer to the corresponding P codeword for all codeids, add the number of error pointers and determine the 2 error positions to correct the erasure of the Q codeword. P series error discrimination unit to be used for, Q sequence error pointer according to the codeid of the Q codeword if the error position obtained by the 1 error position discriminator at the time of Q codeword error correction does not exist in the codeword and the number of error pointers obtained by the P sequence error discriminating unit is not 2. A Q series error discriminating unit for performing the process of setting and storing the memory for all codeids, summing the number of error pointers and determining 2 error positions to use for erasure correction of P code words; If the controller reads the address of the corresponding address from the buffer memory by outputting the error location as index information to the memory address generator, the controller corrects the error by exclusive OR with the error value and stores the data in the corresponding address of the buffer memory. Consist of When the error correction is completed for the Q codeword, the error correction apparatus for a digital signal, characterized in that for repeating the process of repeating the same operation for the P codeword a specified number of times. The method of claim 9, If the error position obtained by the first error position discriminator at the time of Q codeword error correction does not exist in the codeword and the number of error pointers obtained by the P series error discriminating unit is 2, two error values corresponding to two error positions are returned. And erasing correction by sequentially exclusive ORing the data of the corresponding address stored in the buffer memory after obtaining each of the error value generators. The method of claim 9, If the error position obtained by the 1 error position discriminator at the time of error correction of the P code word does not exist in the code word and the number of error pointers obtained by the Q series error discriminating unit is 2, two error values corresponding to the two error positions are returned. And erasing correction by sequentially exclusive ORing the data of the corresponding address stored in the buffer memory after obtaining each of the error value generators. In the error correction method of digital data which reads data from an optical disk, performs error correction on the C1 series and C2 series, and then outputs the correction data and the C2 error pointer. A first step of determining an error by calculating a syndrome when all data bytes in the Q codeword are read from an external buffer memory in which the addresses of the data storage area and the C2 error point storage area are separated; A second step of processing the next Q codeword when it is determined that there is no error in the first step and obtaining an error position when it is determined that there is an error; A third step of determining whether the error position obtained in the second step belongs to a position in a codeword, In the third step, if it is determined that the error location exists in the Q codeword, a fourth step of obtaining one error location and an error value, correcting the one error, and storing the result in a buffer memory; A fifth step of determining whether the number of P error pointers is two, if it is determined in the third step that the error position does not exist in the Q codeword; In the fifth step, if the number of P error pointers is two, a sixth step of obtaining two error positions and error values, correcting the two errors, and storing them in the buffer memory; In the fifth step, if it is determined that the number of P error pointers is not two, a seventh step of setting a Q sequence error pointer corresponding to the currently processed Q codeword and then performing the next codeword processing is performed. When the error correction is completed for the Q code word, the same operation for the P code word is repeated, the error correction method of a digital signal. The method of claim 12, The method of error correction of a digital signal, characterized in that in the iterative correction mode, the error correction of the Q codeword and the error correction of the P codeword are repeated once a specified number of times. In the error correction method of digital data which reads data from an optical disk, performs error correction on the C1 series and C2 series, and then outputs the correction data and the C2 error pointer. A first step of determining an error by calculating a syndrome when all data bytes in the P codeword are read from an external buffer memory in which the addresses of the data storage area and the C2 error point storage area are separated; A second step of, if it is determined in the first step that there is no error, proceeds to processing for the next P codeword, and if there is an error, obtaining an error position; A third step of determining whether the error position obtained in the second step belongs to a codeword, In the third step, if it is determined that the error location exists in the P codeword, a fourth step of obtaining one error location and an error value, correcting the one error, and storing the same in the buffer memory; A fifth step of determining whether the number of Q error pointers is two, if it is determined in the third step that the error position does not exist in the P codeword; In the fifth step, if the number of Q error pointers is two, a sixth step of obtaining two error positions and error values, correcting the two errors, and storing them in the buffer memory; And if it is determined in step 5 that the number of Q error pointers is not two, a seventh step of setting a P sequence error pointer corresponding to a P codeword currently being processed and performing processing of the next codeword may be performed. Error correction method of digital signal to perform.

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