JPH0834441B2 - Error position calculation method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device such as a magnetic disk, and more particularly to an error position calculation circuit suitable for error correction processing using a Reed-Solomon code.

[Prior Art] The Reed-Solomon code is well known as a kind of error correction code. The codeword of Reed-Solomon code is Galois field
BCH (Bose−Chaudhuri−) composed of GF (2 ^m ) elements
Hocqenghem) code. The Galois field is, to put it simply, a set in which the original numbers (orders) are finite among a set of numbers that can perform four arithmetic operations. The Galois field is generally represented by GF (q) or GF (2 ^m ) when the original number is q = 2 ^m . For all non-zero elements of Galois field GF (q), if some kind of irreducible polynomial is chosen, its root α is a power number α ⁰ , α
^1, α ^2, ..., it can be represented by alpha ^q-2. Such a polynomial is called a primitive polynomial, and its root is called a primitive element of GF (q).

For details of the Reed-Solomon code, Galois field, etc., edited by Japan Industrial Technology Center, "Points of Error Correction Coding Technology," March 20, 1986, pages 32-36, Hiroshi Miyagawa, Hiroshi Harajima , Hideki Imai, "Theory of Information and Code," Iwanami Shoten, pages 118-123, 170, 171 issued August 2, 1985.

Conventionally, regarding the calculation of the error position in the error correction using the Reed-Solomon code, as described in the above-mentioned “Points of Error Correction Coding Technology”, pages 160 to 163, for example, the Galois field GF (2 ⁸ ) In the above calculation, the correction device is equipped with a table for obtaining all original exponent parts of GF (2 ⁸ ), and this is done by referring to this table.

[Problems to be Solved by the Invention] According to the above conventional technique, for example, when a Reed-Solomon code is generated on GF (2 ⁸ ), at least 2 ⁸ = 256 bytes of memory are required for error position calculation. become. This memory capacity grows exponentially as the number of originals increases.

An object of the present invention is to eliminate such memory occupation by the error position calculation table.

[Means for Solving Problems] In order to achieve the above object, the present invention uses an error using a Reed-Solomon code on a Galois field GF (2 ^m ) (m: positive integer) whose primitive element is α. In an error position calculation circuit in correction processing, an m-bit multiplication circuit that is sequentially multiplied by α by a shift operation, a register in which m-bit data can be set, and the output of the register and the output of the multiplication circuit are compared. However, it has a coincidence detection circuit for detecting a coincidence between both outputs and a counter for counting the number of shifts of the multiplication circuit until the coincidence detection circuit detects a coincidence.

The multiplication circuit can be configured by, for example, a feedback register including m delay elements obtained by applying feedback to the position of the term where the coefficient of the primitive polynomial on the Galois field GF (2 ^m ) is 1.

The coincidence detection circuit may be configured, for example, to output the kth bit (k: 1,2 ..., m) of the register and the kth bit of the multiplication circuit.
M exclusive OR gates that receive the output of the bits,
It can be configured by an OR gate that receives all outputs of the m exclusive OR gates.

[Operation] Two types of syndromes (residues obtained by dividing the received word by the generator polynomial) are S ₀ and S _1, and if both are expressed by the element of GF (2 ^m ), α ₀ ^k 1 (1 Multiplying ≦ k ₁ ≦ 2 ^m −2) matches the pattern of S ₁ . Utilizing this fact, if the above multiplication is performed by the shift operation of the multiplication circuit (shift register) until they match, the error position can be obtained from the number of shifts k ₁ .

Similarly, if the two types of syndromes are S ₀ and S ^-1, and both are expressed in terms of GF (2 ^m ), then S ^-1 is α ^k2
Multiplying by (1 ≦ k ₂ ≦ 2 ^m −2) matches the pattern of S ₀ . By utilizing this fact, the above multiplication is performed by shifting the multiplication circuit (shift register) until they match each other, and the error position is obtained from the number of shifts k ₂ .

If the number of shifts k ₁ and k _{2 in} both processes match, it can be determined that the error is a single symbol error.

The pattern of the syndrome S ₀ , S ₁ , S _-1 is α ¹
Since it takes any of ~ α ^2m-1 , 2 ^m bytes are required as memory when using the operation table. When m = 8, 2 ⁸ = 256 bytes are enough, but when m = 16, 2 ¹⁶ = 65
It requires K bytes of memory, which is a practical problem.

On the other hand, according to the present invention, as will be described later, since the error position l ≦ data length ≦ 2 ^m −1, if data length = 2 ^m −1, then m = 16 and l + 1 ≦ 65536. Therefore, the number of shifts required for error calculation increases,
It is possible to eliminate the conventional error position calculation table. Further, since the error position, that is, the number of shifts is limited to the data length or less, if the data length is shortened, the number of shifts also decreases.

As for the time required to calculate the error position, it is considered that it is faster to do it by software with reference to a table, but when it is not necessary to make correction in real time as in the magnetic disk device, The present invention is useful.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings.

The primitive polynomial of the Galois field GF (2 ⁸ ) given here is P (x) = x ⁸ + x ⁴ + x ³ + x ² +1 and the primitive element is α.

^Assuming that a single error having a pattern of α ^m occurs in the l-th symbol of the data, according to the conventional error correction method, the syndromes S ₀ , S ₁ , and S are obtained when x + 1, x + α, x + α ⁻¹ are divisors. _{As -1} , the following relation is obtained.

S ₀ = α ^m (1) S ₁ = α ^{m + l + 1} (2) S ₋₁ = α ^{m- (l + 1)} (3) Here, as a general method, S ₁ / S It is determined that there is a single error by satisfying ₀ = S ₀ / S _-1 = α ^{l + 1} (4), and the error position can be known from the quotient α ^{l + 1} .

FIG. 1 shows a circuit for calculating the error position 1 from two types of syndromes according to the equation (4). This circuit consists of a feedback register (8 delay elements and 8 exclusive OR (EOR) gates) that feeds back the position of the term where the coefficient of the primitive polynomial on the Galois field GF (2 ⁸ ) is 1. Of the Galois field GF (2 ⁸ ) multiplied by α, a register 2 in which 8-bit data can be set, and outputs of corresponding positions of the multiplication circuit 1 and the register 2, respectively. It comprises eight EOR gates 5 for receiving, an OR gate 3 for receiving all outputs of these gates, and a clock counter 4 for counting clock signals for performing the shift operation of the multiplication circuit 1.

Next, an operation procedure for calculating an error position by the circuit of FIG. 1 will be described with reference to FIGS.

First, as shown in the flowchart of FIG. 2, let us consider obtaining the error position l ₁ by using the syndromes S ₀ and S ₁ .

First, the count value of the counter 4 is initialized (here, reset to 0) (step 21). Next, the 8-bit syndrome S ₀ is S ₀ = b ₇ α ⁷ + b ₆ α ⁶ + b ₅ α ⁵ + b ₄ α ⁴ + b ₃ α ³ + b ₂ α ²
Since + b ₁ α ¹ + b ₀ (5) is expressed, the respective input terminals of b _{0 to} b ₇ are passed,
As the initial value of the multiplication circuit 1, S ₀ is set, and at the same time, the syndrome S ₁ is set in the register 2 via a load input terminal (not shown) (step 22). After that, the multiplication circuit 1
With the inputs b _{0 to} b ₇ of 0 set to 0, the multiplication circuit is shifted by the clock signal (step 23). At this time, the value of the counter 4 is also incremented at the same time. Therefore, it is determined whether the output of the OR gate 3 has become "low", that is, whether the pattern of the multiplication circuit 1 matches the pattern of the register 2 (step 24). If the two patterns do not match, the process returns to step 23, and if they match, the process proceeds to step 25, and the error position l ₁ is obtained from the value (shift count) k ₁ of the counter 4 at that time.

Expressing this processing as an expression, S ₀ = α ^m , Therefore, the following equation is obtained.

As can be seen from this equation, the number of shifts k ₁ until the pattern of the multiplication circuit 1 matches the pattern of the register 2 is l ₁
+1. Therefore, the number of shifts until pattern matching k ₁
The error position l ₁ is obtained by counting and subtracting 1 from the value.

Next, with reference to the flowchart of FIG. 3, a procedure for obtaining an error position by the syndromes S ₀ and S _-1 will be shown. Similar to the previous procedure, this procedure initializes the counter 4 (step 31), then sets S _-1 as the initial value in the multiplication circuit 1 and S ₀ in the register 2 (step 32), and the OR gate 3 The error position l ₂ is obtained by repeating the shift of the multiplication circuit 1 (steps 33 and 34) until the output of the signal becomes low (step 35). This process is expressed by the following equation.

Therefore, as shown in the flowchart of FIG. 3, the error position l ₁ obtained from the syndromes S _0, S _1, syndrome
The error position l ₂ obtained from S ₀ and S _-1 is compared (step 4
1) When they match, the error is determined to be a single symbol error, and the error position l ₁ (or l ₂ ) is the error position l to be obtained as it is. If the comparisons do not match, it is determined that the error was not a single error (step 43).

Although the counter is initialized to 0 in the above embodiment, if the counter is initialized to -1 in advance, the final value k of the counter will be the error position l as it is. Step 35 (Fig. 3) is no longer required.

According to the present embodiment, the error position can be obtained by the simple circuit as described above without using the calculation table corresponding to any element of GF (2 ⁸ ). Further, the error position l ≦ data length (symbol) ≦ 2 ⁸ −1 = 255 ...
Since (8), l + 1 ≦ 256 (9), and the error position is calculated by shifting at most 256 times.

 Further, this embodiment has the following features.

In the error correction method of F6420 described in the above-mentioned document, G (x) = (x + α ⁻¹ ) (x + 1) (x + α) (1
0) is used, and the data is divided by (x + α) (encoding and syndrome calculation). Where (x +
Since the division circuit according to α) is exactly the same as the multiplication circuit in FIG. 1, this division circuit can be used for error position calculation, and a position calculation circuit needs to be newly provided depending on the error correction processing procedure. There is no.

As described above, according to the present invention, the Galois field GF
The error position can be obtained by a simple circuit without using an operation table corresponding to any element of (2 ^m ), and as a result, the memory for the operation table can be saved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIGS.
The figure is a flow chart for explaining the operation of the circuit of FIG. 1 ... Multiplier circuit, 2 ... Register 3 ... OR gate, 4 ... Clock counter 5 ... EOR gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuji Kawamura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Microelectronics Equipment Development Laboratory (56) Reference JP 62-60319 (JP) , A) JP 63-131623 (JP, A) JP 58-219850 (JP, A) JP 61-6018 (JP, A) JP 57-60753 (JP, A) JP 58-219650 (JP, A)

Claims (1)

[Claims] 1. An error position in an error correction process using a Reed-Solomon code on a Galois field GF (2 ^m ) (m: positive integer) whose atomic element is α is defined as the error position of the Galois field GF (2 ^m ). In the error position calculating method using the three types of syndromes S ₀ , S ₁ , and S _-1 represented in the original, the count of the primitive polynomial on the Galois field GF (2 ^m ) is returned to the position of the term of 1. The syndrome S ₀ input as an initial value to the multiplication circuit is sequentially multiplied by α by the shift operation of the m-bit multiplication circuit that is composed of a feedback register including m delay elements multiplied by, and the result is obtained. The match between the pattern and the pattern of the syndrome S ₁ preset in the m-bit register is determined by the output of the k-th bit (k: 1, 2, ..., M) of the register and the k-th bit of the multiplication circuit. Exclusive logic that receives the output of Of the shift circuits of the multiplication circuit, which are detected by a match detection circuit including a gate and an OR gate that receives the outputs of the m exclusive OR gates, and are performed before the match is detected by the match detection circuit. A numerical value k ₁ is counted by a counter, an error position is obtained from the shift count value k ₁ , the syndrome S _-1 is newly input to the multiplication circuit as an initial value, and the syndrome is shifted by the multiplication circuit. The match detection circuit detects a match between the pattern obtained as a result of multiplying S ₋₁ by α and the pattern of the syndrome S ₀ newly set in the m-bit register, and detects the match. the shift count value k ₂ of the multiplier circuit made up matching the circuit is detected and counted by the counter, seek error position from the shift count value k ₂ , On whether the two shift count value k _1, k ₂ obtained match, error position calculation method which is characterized in that an error to determine whether a single symbol error.