JPS5815352A - Decoding system with three-error correction code - Google Patents

Abstract

PURPOSE:To simplify the constitution of a device and to decode a coded word in a short time, by obtaining the 1st, 2nd and 3rd syndrome through the use of a shift register from the coded word of 3-error correction BCH and correcting the error with the primitive element of the Galois field of the element. CONSTITUTION:The 1st, 2nd and 3rd syndromes A1, A2 and A3 are outputted from the 1st, 2nd and 3rd syndrome producing circuits 102, 104 and 106 by using a data buffer 101 consisting of shift registers for an input data (a). Further, a correction condition discriminating circuit 108 discriminates if A1<3>+A2 is zero and a bit number (t) taking S1=A1+alpha<n-t> as zero is applied to a selection circuit 117. The 1st and 2nd error detection circuits 115 and 116 discriminate if A1<3>+A2not equal to 0, bit trains S1, S2 and S3 are taken as equation 1, an input bit corresponding to values t1, t2, t3, up to three, of a bit number (t) giving EL(t) is inverted, the others are outputted as they are, and three errors are corrected at an error correction circuit 118.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for automatically detecting and correcting bit errors that occur during transmission and storage of digital data.

Error correction coding technology is used as a method for automatically correcting errors that occur during data transmission and storage. There are various error correction codes used for this, but among them, BCH
The (Bose-Chowdhury-Hockinggem) code has a high degree of freedom in selecting the code length and error correction ability, and is known as a code that has superior error correction ability relative to the number of added check bits. The present invention is a BCH code that can correct errors when one code word has three or less bit errors, that is, a 3-error correcting BCH code. The present invention relates to a decoding device, that is, a decoding device.

Here, the 3-error correction BCH code will be briefly explained.

In the 3-error correcting BCH code, the code word C consists of k information bits (αl, α2..., αk) and q check bits (α plus 1) calculated from these information bits.
.

(Zk+2. . . , α&+q). In other words, the code word C is C=(α1.α2..., α, αi+1, .
..., α becomes +9).

However, k is determined so that k=2-3m-1 q=8m where m is an integer of 4 or more. From now on, the code length will be 1q=2-1 as n.
It is expressed as That is, the code word C is C=(α1.α2..., α,, -11LLn
). The check bits are determined so that the code word satisfies HC=0. Here, C is the transposed vector of C. H is a parity check matrix and is expressed as using the primitive element α of GF(2''). Each element α' of H (w=o, 1.-, s-
1) is represented by a column vector of m elements.

Now suppose that an error occurs in C and it becomes C', C' = (
α'1, α'2, ..., α'n-1, α'n)
C' is expressed by C and error vector e as follows.

C'=C+e where e is 1 at the position of the error bit of C'. H in other positions
It is a vector consisting of elements o.

e=(el, e2..., en-1, en)C'
When C is given, decoding is to reproduce the original C, and the present invention provides a new device for realizing this.

Decoding of conventional 3-error correction codes is usually performed by the method described below.

First, the first one defined by the following equation. Calculate the second and third syndromes, A1, A2, and A3.

Syndromes A1, A2, and A3 are eg F, J.

“The Theory of Error-Correct” by MacWilliams, N. J. A., 51oane.
ingCodes, Part I” (North-Hol
land Publishing Company) pp,
270-272. In other words, the first syndrome A1 changes the bits of C' from α'1 to α to the feedback shift register corresponding to the minimum polynomial of α.
'n is input, and when α is input, it is completed in the shift register. In the second syndrome A2, C' is input to the feedback shift register corresponding to the minimum polynomial of α, and when the last bit is input, the bit string created in the shift register is converted using an exclusive OR circuit. can get. Similarly, the eighth syndrome A3 is
Input C' into the feedback shift register corresponding to the minimum polynomial of α.

It is obtained by converting the bit string created in the shift register when the last bit is input using an exclusive OR circuit. Next, the error locator polynomial σ(Z) is determined using this AI, A2, and A3.

Assign αt (t=1, 2..., n) to this σ(Z), assume that the value of t that makes σ(Z) = 0 indicates the error position, and invert the bit at that position. to correct errors.

The above is the decoding operation performed by the conventional decoding device. However, this method requires a relatively complicated device to determine each thread count of σ(Z).

it takes time.

Therefore, an object of the present invention is to provide a 3-error correction code decoding system that can be decoded in a short time using a relatively simple device.

Next, the decoding operation performed by the decoding device of the present invention will be explained.

Also in the decoding device of the present invention, the first, second and third syndromes Al, A2. Calculating A3 first is the same as the conventional method. Next, At'+A2 is calculated using the first syndrome AI and the second syndrome A2. A1
can be calculated by inputting Al to a cuber using a ROM table or the like. Addition of At and A2 can be easily realized using an exclusive OR circuit. Furthermore, αn-t, α3(n-1
) and α5(n-1) are generated sequentially from t=1 to n. αn-1 is represented by bit string 1, α3(n-1) is represented by bit string 2, and α5(n-1) is represented by bit string 3.

The generation of αn-1 is, for example, Miyayo et al. Coding Theory (Shodendo) p.
．． As shown in 119, by setting the initial value αn=1 in the feedback shift register corresponding to the minimum polynomial of α and shifting it t times, αn-1 can be obtained.

α3(n-1) is obtained by inputting αn-1 into a cuber using a ROM table, for example. α5(nt) is similarly obtained by inputting αn-1 to the fifth power. Alternatively, set the initial value α3n=α5n=1 in a shift register circuit that multiplies α-3 or α-5 with one shift, as described in Miyayo et al.'s Coding Theory (Shokodo), p. 120. It can be obtained by shifting t times. The first syndrome A for each value of t
z, second syndrome A2. Third syndrome A3, α
St, S2 and s3 defined by the following equations are calculated using n-1, α3(n-1) and α5(nt).

S1=A1+αn-1 S2=A2+α3(nt) S3=A3+α5(nt) S1 is represented by bit string 4, Szu bit string 5, and S3 is represented by bit string 6. Addition of A1 and αn-1, A2 and α
The addition of 3(n-1) and the addition of A3 and α5(n-1) are easily realized by an exclusive OR circuit. Next, EL(t) defined by the following equation is calculated.

EL(t)=SI×S2+SIS2+SI5aEL(t
) is a 6th power circuit made up of a ROM table, from SI to S.
Calculate t and use a square circuit made up of a ROM table to calculate 8
2 to 82, calculate s13S2 from Sl and S3 with a cube and product circuit configured with a ROM table, calculate S1S3 from S1 and S3 with a product circuit configured with the same <ROM table, and calculate S61 and S22, S13 and S1S
3 using an exclusive OR circuit. If said AI+A2 is 0.

Check the value of Sl for each t value and assume that at t when S1=0, the t-th bit α' in C' is an error, α;
If A13+A2 is not 0, the value of EL(t) is checked for each value of t, and at t when EL(t)=0, the t-th value in C' is calculated. The decoding operation performed by the decoding apparatus of the present invention is to correct the error by inverting bit a;, assuming that bit α: is an error.

In the decoding operation, a relatively simple operation is repeated for each bit of the code word, but since there is no complicated operation such as determining the error locator polynomial in the conventional decoding method, the device becomes simpler.

It will be shown below that by this operation, correct error correction is always performed when the number of error bits is 3 or less.

First, let's assume that there is not a single bit error. At this time AI=A
2=A3=0 Therefore.

Al+A2=0 Therefore, error correction is performed according to the value of 81. By the way, St=At+αn-1=αn-1 does not become 0 for any value of t. Therefore, no inversion is performed on any bits in C'.

Next, suppose that only the i-th bit α is erroneous. At this time, AI=αn-1 A2=α3(n-1) Therefore, Al+A2=0 Therefore, error correction is performed according to the value of S1.

At this time, S1=A1+αn-1=αn-1+αn-1S1 is t=
It becomes 0 only when i, and does not become 0 when rt\i. Correct error correction is therefore performed.

Next, suppose that the i-th and j-th bits, ie, α'i and α'j, are errors. At this time, Al=αn-1+αn-1 A2=α3(n-1)+α3(n-j)A13+A2=
α(n-1)+αn-1(αn-1+αn-1)i\i
Therefore, AI+A2\0 Therefore, error correction is performed according to the value of EL(t).

At this time.

EL(t) becomes 0 only when t matches i or j.

When t takes other values, it does not become 0. Correct error correction is therefore performed.

Next, suppose that the t-th, j-th, and 1-th bits, that is, α;, α;, and i, are errors. At this time, therefore EL, (
Error correction is performed according to the value of tl.

At this time, EL(t) becomes 0 only when t matches i, j, or l, and does not become 0 when t takes other values.

Therefore, correct error correction can be performed. As can be seen from the above (if the number of C error 9 bits is 3 or less, correct decoding is always performed.

Next, a decoding device according to the present invention will be explained with reference to drawings of embodiments. As described above, the decoding device of the present invention handles elements of a Galois field in its decoding procedure. G
Any element of F(2') is lt, α, α with α as a primitive element.
2. It is well known that it can be expressed as a linear combination of α and α.

In this embodiment, it is assumed that the elements of the Galois field are found using m bits, which is a series of the linear combinations.

Of course, it is not necessary to unify the representation of the original bit string of the Galois field in the entire decoding procedure; rather, the device may be slightly simpler by using partially different representations, but here we will provide a simple explanation. Therefore, the above expression will be unified.

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In FIG. 1, input data α is the data buffer 101
, a first syndrome generation circuit 102, a second syndrome generation circuit 104. and third syndrome generation circuit 1
Added to 06. The data buffer 101 is constructed of a shift register with a total of n+1 bits, which is n bits long for one code word and 1 bit for holding a signal for the time necessary to transfer the syndrome generated by the syndrome generation circuit to the syndrome buffer. configured. The first syndrome generation circuit 102 consists of a permanent feedback shift register corresponding to the minimum polynomial of the primitive element α of GF(2m). The second syndrome generation circuit 104 consists of a bit string conversion circuit composed of a permanent feedback shift register corresponding to the minimum polynomial of α3 and an exclusive OR circuit. The eighth syndrome generation circuit 106 consists of a bit string conversion circuit composed of a feedback shift register corresponding to the minimum polynomial of α5 and an exclusive OR circuit. When the last bit of the code word has been input into the data buffer 101, the first . Second. and the third syndrome are generated by each syndrome generation circuit.

The generated 1st. Second. and the third syndrome are destroyed when the next codeword is input to the syndrome generation circuit, and are therefore transferred to the first, second, and eighth syndrome buffers, respectively, before that. First syndrome (Al)
and the second syndrome (A2) are corrected by the correction condition determination circuit 108.
The correction condition determining circuit 108 determines whether A, 3+A2 is 0 or not.

When AI+A2 is 0, 0 is output; otherwise, 1 is output and given to the selection circuit 117. Correction condition determination circuit is ROM
, an 8th power circuit made up of a table, an addition circuit made up of an exclusive OR, and an OR circuit that determines whether the addition result is all bits 0 or not. The code word stored in the data buffer 101 is output bit by bit starting from the first bit, and is input to the error correction circuit 118. tth (t=1
,2. ... n) bits are output from the data buffer 101 and input to the error correction circuit 118, the power generation circuit 110 of α generates bit string 1, which is a bit string of m bits representing α, and generates the power of α3. The circuit 112 is α
The power generating circuit 114 of α5 generates bit string 2, which is an m-bit bit string representing 3(n-1).
A bit string 3 representing n-1) is generated. The power generation circuit 110 of α consists of a feedback shift register corresponding to the minimum polynomial of α. α3 power generation circuit 112
consists of a feedback shift register corresponding to the α3 minimum polynomial. The power generation circuit 114 of α5 is composed of a feedback shift register corresponding to the minimum polynomial of α2. Bit string 1 and the first syndrome are added by exclusive ORing for each corresponding bit by exclusive OR circuit 109.

Bit string 4 representing S1=At+αn-1 is generated.

Similarly, bit string 2 and the second syndrome are added using the exclusive OR circuit 111, and S2=A2+α3(+a, -
1) A bit string 5 representing ' is generated. Furthermore, bit string 3 and the third syndrome are added using exclusive OR circuit 118 to generate bit string 6 representing S3=A3+α5(n-1). Bit string 4 is supplied to the first error detection circuit 115 and second error detection circuit 116, and bit string 5 and bit string 6 are supplied to the second error detection circuit. The first error detection circuit 115 outputs l when S1 is 0, and otherwise outputs 0 and provides it to the selection circuit 117, and is composed of an OR circuit and a NOT circuit. The second error detection circuit 116 generates a bit string 4. Bit string representing S25. and input the bit string 6 representing Ss, and if S1+S2+513S2+StSs is 0, then l
otherwise, 0 is output and given to the selection circuit 117.

FIG. 2 shows an example of the configuration of the second error detection circuit 116.

In FIG. 2, bit string 4 is supplied to 6 East circuit 201.8 power and product circuit 203, and product circuit 204, bit string 5 is supplied to 2 East circuit 202, 8 power and product circuit 208, and bit string 6 is is supplied to circuit 204. 6 East circuit 201 generates a bit string 7 representing S and F.

2 East circuit 202 generates bit string 8 representing S2. The 8th power and product circuit 203 generates a bit string 9 representing 513S2. Product circuit 204 generates a bit string 10 representing 5IS3. 6th power circuit 201. 2nd power circuit 20
2.8 power and product circuit 203. and the product circuit 204 are all R
Consists of OM tables.

The exclusive OR circuit 205 performs addition by performing exclusive OR for each corresponding bit of the bit string 7 and the bit string 8, and creates a bit string 11 representing s, 6+S22. The exclusive OR circuit 206 performs addition by performing exclusive OR for each corresponding bit of bit string 9 and bit string 10, and creates bit string 12 representing 513S2+StSs. The exclusive OR circuit 207 performs addition by performing exclusive OR for each corresponding bit of the bit string 11 and the bit string 12 to create a bit string 13 representing S'l+S2+513Sz+5tS3. The OR circuit 208 performs the OR of all bits of the bit string 18 to obtain S2+5 in Sl.
IS2+S! If S3 is 0, it outputs 0, otherwise it outputs 1. The NOT circuit 209 inverts the polarity of the output of the OR circuit 208, and outputs 1 when St+S2+StSz"5tS3 is 0, and 0 in other cases. Returning to FIG. 1, the selection circuit 117 includes an AND circuit and an OR circuit. and a NOT circuit, and the correction condition determination circuit 108 is AH3+A2.
If it determines that =O and outputs 0, the output of the first error detection circuit 115 is omitted, and the correction condition determination circuit 108 determines that AH3+A2\0 and outputs 14. If so, the output of the second error detection circuit 116 is used as the output. The error correction circuit 118 is an exclusive OR circuit, and performs an exclusive OR of the output of the data buffer 101, the second bit α:, and the output of the selection circuit 117. Therefore, if the output of the correction condition determination circuit 108 is 0 and the output of the first error detection circuit 115 is 1, or the output of the correction condition determination circuit 108 is 1 and the output of the second error detection circuit 116 is 1. In this case, the output of the error correction circuit 118 is the inverted version of the output of the data buffer 101, the second bit α; otherwise, the output of the error correction circuit 118 is the output α of the data buffer 101.
It remains as it is. The output U of the error correction circuit 118 becomes output data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a decoding device according to the present invention.
FIG. 2 shows an example of the configuration of the second error detection circuit 116 in FIG. In the figure, 101 is a data buffer. 102 is a first syndrome generation circuit, 108 is a first syndrome buffer, 104 is a second syndrome generation circuit, 105 is a second syndrome buffer, 106 is a third syndrome generation circuit, 107 is a third syndrome buffer, and 108 is a correction condition determination circuit. 109 is an exclusive OR circuit, and 110 is an α power generation circuit. 111 is an exclusive OR circuit, 112 is a power generation circuit for α, 113 is an exclusive OR circuit, 114 is a power generation circuit for α5, 115 is a first error detection circuit, 116 is a second error detection circuit, and 117 is a power generation circuit for α5. selection circuit; 118 is an error correction circuit; 2
01 is a 6th power circuit, 202 is a 2nd power circuit, 203 is an 8th power and product circuit, 204 is a product circuit, 205 is an exclusive OR circuit,
206 is an exclusive OR circuit, 207 is an exclusive OR circuit, 208 is an OR circuit, and 209 is a NOT circuit. a is the input data, b is the fXl syndrome, C is the second
syndrome, d is the 8th syndrome, ε is bit string 1
．． / means bit string LQ is bit string 8. h is the bit string 'eF
is the bit string 5. r is bit string 6, ν is bit string 7, z is bit string 8. ν is a bit string 9.8 α is a bit string 10. c.
c is a bit string 12. dd is the bit string 18. f is the decoded output. Patent applicant International Telegraph and Telephone Co., Ltd. Patent application agent Megumi Yamamoto

Claims (1)

[Claims] Input sequence C′=(α active, α2.α1°·
. and the third syndrome A3; are obtained using a shift register, and then AI+A2=0
In other words, (α is a primitive element of the Galois field GF (2'') consisting of 2' elements, t is a natural number that specifies the bit to be determined as an error and does not exceed n) is t. If there is a value of , the corresponding input bit αt is treated as an error and inverted, the other input bits are output as they are, and up to three values of t (tx, '2+ '3) Invert the input bit (α'11.α't2.αt3) corresponding to
A three-error correction code decoding system characterized by correcting up to three errors by outputting other input bits as they are.