RU1810909C - Error corrector - Google Patents

Abstract

The invention relates to computer technology, in particular to devices for detecting and correcting errors that occur during the storage or transmission of digital information. The aim of the invention is to increase the speed of the device. This goal is achieved by eliminating excessive correction of control characters by introducing into the corrector of the error selection block control characters with information indicating where in the codeword an error occurred in the information field or in the control character field. The error corrector comprises a syndrome register, a feedback unit, an error detector, an error location fixation unit, a data buffer, an error correction unit, a control unit, and check symbol error selection unit. 2 ill. WITH/)

Description

The present invention relates to the field of computer technology, in particular, to devices for detecting and correcting errors that occur during the storage or transmission of digital information.

Currently, in computer technology, information encoding has gained widespread use of cyclic codes — Hamming, Fire, and other codes. The noise immunity of these codes is ensured by the introduction of redundancy achieved by adding so-called verification or control characters to the information symbols of the encoded message. In the encoding process, the original message is divided into information words UIFF with a fixed number of characters and for each information word, control characters are generated. VKOHTP - After the control characters are attached to the information word, the code word VKOR of the cyclic block systematic (n, k) code is obtained; where n is the total number of characters in the codeword, k is the number of information characters; m p - k - the number of control characters. In this case, they often use the full-nomic representation of code vectors, which allows one to define a cyclic code mathematically using the so-called generating polynomials. For example, the generating polynomial over the symbol field of the alphabet GF2 defines a (31.26) Hamming code that corrects one random error.

00

Ltd

45

The generation of control characters during the encoding is carried out by calculating the residual polynomial VKOHTP Winf. xmmodY using arithmetic of Galois fields. When a message is received, it is decoded to detect and correct errors that occur during storage or transmission. The received word can be represented as the sum of the transmitted VKOA codeword and the VLO error vector. When decoding the residual polynomial VKOHTP (VKOA + VLS) -xm mod Y, the control symbols of the error vector, called the syndrome, are obtained. Having the known meaning of the syndrome, it is possible, using special devices called decoders or error correctors, to form an error vector and recreate the transmitted code word in its original form.

A device for correcting independent errors is known (see Peterson W., Weldon E. Codes for Correcting Errors, Moscow: Mir, 1976, p. 191). This corrector is characterized by a lack of speed due to loss of time for the correction of code words for which control characters are distorted.

The same drawback is also inherent in the error corrector (see Portnoy S.A., Ankudinov D.R. Code and corrective block codes. - Foreign Radio Electronics,

1985. No7, p. 3-27).

A well-known error corrector with non-algebraic sequential decoding of a symbol of a cyclic systematic code, in particular a Hamming code (see Bleikhut R .. Theories and practice of error control codes. - M.: Mir,

1986. p. 174). This device is selected as a prototype.

The prototype diagram is shown in FIG. 1. It contains a syndrome register 1, a feedback unit 2, an error detector 3, an error location fixation unit 4, a data buffer 5, an error correction unit 6, and a control unit 7; the output of the feedback block 2 is connected to the information input of the register register 1. the outputs of which are connected to the corresponding information inputs of the error detector 3 and the block for fixing the location of the error 4, the output of which is connected to the correction inputs of the feedback block 2 and the error correction block 6, the output which is connected to the output 17 of the device and is an information output

0

5

0

5

0

5

0

5

0

5

error corrector, the output of the error detector 3 is connected to the output 16 of the device and is the control output of the error corrector, the information inputs of the feedback unit 2, the data buffer 5 and the first information input of the error correction unit 6 are combined and connected to the input 8 of the device, which is information input of the error corrector, the control inputs of the unit for fixing the location of the error 4, the error detector 3, the error correction unit 6 and the feedback unit 2 are connected to the control output of the syndrome 1 register, the reset and shift inputs which is connected respectively to the first and second outputs of the control unit 7, the third output of which is connected to the operation enable input of the error location fixing unit 4, the second information input of the error correction unit & connected to the output of the data buffer 5, address inputs and read inputs, records, the accesses of which are connected respectively to the fourth, fifth, sixth and seventh outputs of the control unit 7, the eighth, ninth and tenth outputs of which are connected to the outputs 14, 15, 13 devices and are respectively the synchronization output of the information source, the synchronization output of the information receiver and the output of the error corrector ready, the inputs of the initial installation, error reset, reading and correction of the control unit are connected to the inputs 9,10.11, 12 of the device and s.ootvetstvenno are input initial setting, the error reset input, and the input of the corrector vhodom.chteni error correction.

Syndrome register 1 when receiving messages provides the formation of control characters (syndrome) of the code word coming from the input 8 of the device to the information input of the feedback unit 2 and from the output of the latter to the information input of the register 1. The formation of the syndrome is carried out by symbolically dividing the code word into generating polynomial. Reception and division of a codeword by a generating polynomial begins with its oldest characters. Residues from the division of individual characters are accumulated in syndrome register 1. The final result is obtained after receiving the last (least significant) character of the codeword. When an error is detected and a message is received (the syndrome is not equal to zero), register 1 and the syndrome contained in it are used to construct the vector

mistakes. This is accomplished by modularly multiplying the syndrome, which is achieved by shifting the register of syndrome 1 to the right.

1 is produced by signals from the control unit 7 supplied to the inputs of the shift and reset of register 1.

The feedback unit 2 provides the formation of input signals for the syndrome register 1, using for this purpose the codeword symbols coming from the input 8 of the device, as well as the output signals (feedback signals) released when the high order of the syndrome register 1 is shifted. depending on the value of the signal at the output of the block fixing the location of the error 4, block

2 allows or prohibits the passage of feedback signals to the information input of register 1.

Error detector 3 generates signal 1 if the contents of syndrome register 1 is not 0. In read mode, this indicates the presence of detected errors, and in correction mode, unrecoverable errors in the received messages. The error location fixation unit 4 in the correction mode generates an output signal at the moment of completion of the formation of the error vector by the syndrome register 1. The correction signal from the output of block 4 enters blocks 6 and 2 to correct the detected error and the corresponding syndrome. . . .

Data buffer 5 is intended to temporarily store the received codeword in case error correction is required in the future.

In the error correction unit b, the errors of the received codeword are directly corrected by adding it symbolically (in the case of binary codes, modulo two) with the error vector,

The control unit 7 provides interaction and synchronization of the operation of the nodes of the device. Block 7 generates the reset and shift signals of the syndrome register 1, the control signal for the error location block 4, the write, read, access signals, as well as the address signals of the data buffer 5: readiness signals for the device, synchronization of the source and receiver of information.

The prototype device operates as follows. Before reading the information to the control unit of the receiver through the inputs 10 of the error corrector, the signals of the initial installation of the device and

5

error reset, resetting the syndrome register 1 and preparing the control unit for operation. Then, the information receiver submits a read signal 5 to the input 11 of the device and the control unit resets the ready signal at the output 13 of the device and generates a sequence of synchronization signals, which from the output 14 go to the source of encoded messages. For one read command, one codeword is received. In response to each clock, the message source transmits one character. These characters are eating. input 8 of the error corrector without changes through the error correction unit 6 are fed to the information output 17 and then to the information receiver, accompanied by synchronization signals to the output 15 of the device. Simultaneously received symbols are written to data buffer 5 and fed to feedback block 2 for division by a generating polynomial. After receiving the next character

5, the control unit 7 shifts to the right by one. Syndrome Register 1 is incremented and increments by 1 the address code on the address inputs of the data buffer 5. Thus, in the process of sequential character division

0 of the received codeword in register 1, partial residuals from the division of all the characters of the codeword are accumulated, which ultimately form the multiplications ((error syndrome S (Nursing + WOSH) xm-toyU.

5 After receiving all n symbols of the codeword, the control unit 7 stops and provides a ready signal to the output 13 of the device. If the contents of syndromic register 1 at this moment is not equal to O,

0 then the error detector 3 will generate an error signal, which will be output 16 of the device. Perceived in the error corrector ready signal, the information receiver analyzes the value of the error signal on

5 output 16 error corrector. If there is no error signal, then reading the codeword is completed, and the information receiver provides the above sequence of instructions for reading the next codeword. If there is an error signal, the operation of the device for decoding the received codeword should be continued in order to carry out the correction of erroneous characters. To do this, from the information receiver to the inputs 9 and 12 of the device signals of the initial installation and

correction. The control unit 7 thus enables the operation of the unit for fixing the location of the error 4. translates the data buffer 5

into read mode and resets the ready signal. Then, the control unit 7 generates signals to access the data buffer 5, shift the syndrome register 1, increment the address code on the address inputs of the data buffer. The distorted code word read from the data buffer 5 enters the error correction block 6 symbolically and, in the absence of a signal at the output of the location block of the error 4, is transmitted without changes through the block 6 to the output 17 of the device. The generated signals are accompanied by synchronization signals at the output 15 of the device. Simultaneously with the issuance of the next character, the syndromic register 1 dl is shifted one bit to the right. multiplying by x the syndrome contained therein. After an error vector is generated in the register 1 during sequential multiplication of the syndrome, block 4 generates an output signal that will be input to the correction input of block 2 and break the feedback of the syndrome register 1, thereby preserving the characters remaining in it during subsequent symbol shifts error vector. The same signal will be sent to the correction input of block 6 and will allow the transmission of the error vector from the control output of the syndrome register 1 to block 6. In block 6, the distorted code symbols and the words coming from the data buffer with the symbols of the error vector are added. The codeword symbols corrected in this way from output 17 and the synchronization signals accompanying them from output 15 of the error corrector are sent to the information receiver. After the transmission of the corrected message is completed, the control unit 7 stops and provides a ready signal to the output 13 of the device. If the error correction process was successful, then the output 16 of the device at this moment will be no error signal. Otherwise, and this happens when fatal errors are detected, the output 16 of the device will contain an error signal, and it is up to the information receiver to decide what to do in this case - to operate with distorted information, re-read the code word or stop further work altogether.

The prototype device has a disadvantage of insufficient speed, which is due to the time spent on the correction of control characters. In most cases, correction of these characters is not necessary,

0

5

0

5

0

5

0

5

0

5

since subsequently, when processing information in a computing device, they are still not used.

An object of the present invention is to improve the performance of an error corrector by eliminating redundant check character correction. Technically, this is achieved by introducing into the error corrector the Check symbol error selection block, the information inputs of which are connected to the outputs of the syndrome register, and the control input is connected to the output of the control unit; the output of the block entered in the error corrector is the control output of the device.

In known error correctors, an increase in speed is achieved through the use of a faster element base, which makes it possible to increase the transmission speed of information during correction. However, in this case, the performance of the corrector is limited by the bandwidth of the communication lines, as well as the time of information retrieval from the data buffer.

In contrast to the known technical solutions in the proposed device, due to the features indicated in the characterizing part of the formula, the device is given a qualitatively new property, namely: excessive correction of control characters is eliminated. Therefore, this feature is significant. O

The proposed device is shown in FIG. 2. It contains a syndrome register 1, including one-bit shift registers 2, coupled via modular two addition circuits 3, and keys 4 for setting coefficients of the generating polynomial, feedback block 5, error detector 9, error location fixation block 10, data buffer 11, error correction block 12, error selection block of check symbols 1 of control block 17; the output of the feedback unit 5 is connected to the information input of the synchronous register 1. the outputs of which are connected to the corresponding information inputs of the error detector 9, the error selection block of the check symbols 16 and the error location fixation unit 10, the output of which is connected to the correction input of the feedback unit 5 and error correction unit 12, the output of which is connected to the output 27 of the device and is the information output of the error corrector, the output of the error detector 9 is connected to the output 26 of the device and is the first control the output of the error corrector, information inputs of the feedback block 5. data buffer 11 and the first information input of the error correction block 12 are combined and connected to the input 18 of the device, which is the information input of the error corrector, the control inputs of the block for fixing the location of the error 10, the error detector 9, the error correction block 12 and the feedback block 5 are connected to the control output of the syndrome 1 register, the reset and shift inputs of which are connected respectively to the first and second outputs of the control block 17, the third output which is connected to the operation enable input of the error location unit 10, the second information input of the error correction unit 12 is connected to the output of the data buffer 11, address inputs and read, write entries, the accesses of which are connected respectively to the fourth, fifth, sixth and seventh outputs of the control unit 17, the eighth, ninth and tenth outputs of which are connected to the outputs 24, 25, 23 of the device and are respectively the synchronization output of the information source, the synchronization output of the information receiver and the availability readiness error corrector, inputs of the initial setting, error reset, reading and correction of the control unit 17 are connected to the inputs 19, 20, 21, 22 of the device and are respectively the initial setting input, error reset input, read input and error correction correction input, eleventh output the control unit 17 is connected to the control input of the check symbol error block 16, the output of which is connected to the output 28 of the device and is the second control output of the error corrector.

Shift registers 2, modulation two addition schemes 3, and 4 keys for setting coefficients of the polynomial generating the cyclic code form syndrome register 1. This register, when receiving messages, provides the formation of control characters (syndrome) of the code word coming from the output of block 5 to the register information input 1. Syndrome is formed by character-by-character deletion of the generative polynomial of the codeword, starting with its leading characters. Residues from the division of individual characters are accumulated in the syndrome register 1. The final result is obtained after receiving the last (least significant) character of the codeword. When an error is detected in the received message (the syndrome is not equal to zero), register 1 and the syndrome contained in it are used to construct the error vector, which is implemented by means of a modular

multiplication of the syndrome by shifting to the right of the register of syndrome 1. The shift and reset of register 1 is performed by signals coming from the control unit 17. In the case of binary cyclic codes for

polynomial representation of the generating polynomial and codeword as

2, - $ i x uses the alphabet of two

characters are O and 1. Accordingly, the coefficients ai of the polynomial can also take only two of the indicated values. For example, a syndrome register for decoding a cyclic code defined by a generating polynomial Y x + x 1

E | X -, 30, 34 0,

25

i 0

contains 5 one-bit shift registers, and in the closed position there are only two keys to the leftmost

defining the coefficients a0 and ai. If the coefficients ai are constant, then the keys 4 can be fixed (sealed) links. The outputs of syndrome register 1 are the outputs of its constituent

shift registers 2. The signal from the output of the highest - rightmost bit (control output) through block 5 is involved in generation. Syndrome Register Feedback Signals 1.

The feedback unit 5 contains a two-input I7 circuit, an inverter 6, and a two-input addition circuit modulo two 8. The unit has 3 inputs and 1 output. The inverter input. 6 is the correction input of block 5. One of

the inputs of circuit I7 is connected to the control output of the syndrome register 1 and is the control input of block 5. The information input of block 5 is the input of modulation two addition circuit 8, connected to

information input 18 of the device. The output of the addition circuit 8 modulo two - the same output of block 5 is connected to the information input of the syndrome register 1. Block 5 provides the formation of input information signals for the syndrome register 1, using input error signals from the error corrector received at the input 18 from the message source , as well as feedback signals coming from the control output of the syndrome register 1. In this case, depending on the value of the signal at the output of block 10, block 5 will allow or prohibit the passage of signals back communication to an information input of the syndrome register.

The error detector 9 is an NAND circuit with the number of inputs equal to the number of bits of the syndrome register 1. If there are errors in the received code layer, the contents of the syndrome 1 register will not be 0 and the error detector will generate 1 at its output, which is first control output of the device. Otherwise, the contents of the syndrome 1 register and the output of the error detector will be 0.

The error location block 10 is an AND circuit with the number of inputs ensuring its connection to all outputs of the syndrome 1 register, as well as to the output of the control unit 17, which allows the operation of block 10 in the correction mode. Block 10 generates a signal when the generation of the error vector by the syndrome register 1 is completed. This signal is supplied to blocks 5, 12 to correct the detected error and the corresponding syndrome.

Data buffer 11 is designed to temporarily store a received codeword in read mode in case errors are to be corrected in the future. It is most convenient to use a sequential shift register as the data buffer. However, in view of the fact that shifting registers of a higher bit size are not produced by industry, the most common use of one-bit memory with direct sampling is as a data buffer. Address signals, read, write, and data buffer access signals are generated in the control unit 17.

In the error correction block 12, the errors of the received codeword are directly corrected by adding it symbolically (in the case of binary codes, modulo two) with the error vector. Block 12 contains a two-input circuit And 13, a two-input modulation circuit two 14 and a two-input circuit OR 15. The first input of the circuit And 13 is connected to the output of the block 10 and is at the same time the correction input of the block 12. The second input of the circuit And 13, connected to the control output of the syndrome register 1 is the control input of block 12. The first information input of the block

5

12 is an input of an AND. Circuit 15. connected to the error correction information input 18. The second information input of block 12 forms the input of the addition circuit modulo two 14 connected to the output of the data buffer 11. The output of the OR circuit 15 is simultaneously the output of the block 12.

Control error selection block

About Symbols 16, which is a distinguishing feature of the device according to the invention, is intended to isolate control symbol errors from the entire set of codeword errors. The information inputs of block 16 are connected to the outputs of the syndrome 1 register, and the control input, which enables the operation of block 16 in the reading mode, is connected to the output of the control block 17.

Q The output of block 16 is simultaneously the second control output of the device. Signal 1 at this output is generated if check digits are erroneous in the received codeword; otherwise, signal O is generated.

The block of error control for check symbols can be implemented on combinational logic circuits, on the basis of an arithmetic logic device, or

0 ROM. The following is an example implementation of block 16 based on ROM. To present information about the errors of control characters in the ROM, one bit per error is sufficient: 1 can be used to

5 for coding check symbol errors, and O for coding all other errors. In the case of, for example, (31.26), a Hamming code with a generating polynomial Y x5 + x + 1 out of 25 - 32 possible values

There are only five of the following syndromes: x + 1, x2 + X, x3 + x, x4 + x3n x4 + x + .1 will be control character error syndromes that are smart with x. They correspond to 5-bit ROM addresses: 00011, 00110,

5 01100,11000,10011. It is necessary to write 1 to these addresses in the ROM, and to the others - O. If you use the syndrome register when reading the contents of the ROM before correction, you can get information about the nature of the error. If reading is received 1. then the error belongs to the control characters. Reading information from the ROM is triggered by a signal from the control unit, which is fed to the control input (access enable input) of the ROM.

Currently available LSI ROMs, in particular the 556 series with a capacity of 1K - 64 K bits in one package, allow

5

to develop error correctors operating with code words of any length.

The control unit 17 provides interaction and synchronization of the operation of the device nodes. The circuit of the control unit is shown in FIG. 3. It includes RS-triggers 12,13,29; clock generator 15: OR circuits 16, 24.41, 42; Schemes I 17.23, 31, 32, 37, 38; inverters 18, 33, 35; D-triggers 26.28; OR-NOT circuit 27, delay circuits 39, 40; clock counter 44, amplifiers 14, 25, 30. 34, 36, 43; the input of the amplifier 14 is connected to the input 19 of the initial installation of the device, and the output is connected to the reset inputs of the triggers 12, 13,, 26, 28, the clock counter 44, as well as the first input of the OR circuit 24; the input of amplifier 25 is connected to input 20 of the device error reset, and the output to output 1 of the control unit. The inputs of the installation of 1 triggers 12, 13 are connected respectively to the inputs 21, 22 of reading and correction of the device, the output of the trigger 12 is connected to the first inputs of the circuit OR 16 and circuits AND 23, 38-, as well as the output 6 of the control unit; the output of the trigger 13 is connected to the second input of the OR circuit 16 and to the first inputs of the circuits AND 17, 37, and also through the amplifiers 30, 36 to the outputs 5, 3 of the control unit, the output of the clock generator 15 is connected to the clock input of the D-trigger 26 and with the first inputs of AND circuits 31, 32, the information input of the D-trigger 26 is connected to the output of the OR circuit 16, and the output is connected to the second input of the And 31 circuit, the third input of which is connected to the output of the OR-NOT 27 circuit, the output of And circuit 17 is connected to the input of the inverter 18 and with the first input of the circuit OR NOT 27, the output of the circuit And 23 is connected to the information input of the D-trigger 28, and with the second inputs of the OR-NOT circuit 27 and the And 32 circuit, the third input of which is connected to the output of the D-flip-flop 28, and the output - to the clock input of the D-flip-flop 28, the input of the inverter 33 and the output 11 of the control unit, the output circuit And 31 is connected to the second inputs of circuits And 37, 38 and with the input of the inverter 35; the second and third inputs of the OR circuit 24 are connected to the outputs of the inverters 18, 33; the reset and reset inputs of the trigger 29 are connected to the outputs of the OR circuit 24 and the inverter 35, and the output through the amplifier 34 is connected to the output 10 of the control unit and to the standby output 23 of the device. The output of AND circuit 37 is connected to the first input of OR circuit 41 and through the delay circuit 40 to the first input of OR circuit 42; the output of AND circuit 38 is connected to the output 8 of the control unit and to the output

5

24 synchronization of the information source, device, as well as through the delay circuit 39 - with the second inputs of the circuits OR 41, 42; the output of the OR circuit 41 is connected to the counting 5 input of the counter 44, and to the output 7 of the control unit; the output of the OR circuit 42 is connected to the output 2 of the control unit, and also through an amplifier 43 to the output 9 of the control unit and to the synchronization output 25 of the device information receiver; / information inputs of the counter 44 are connected to the second inputs of the circuits AND 17, 23 and to the output 4 of the control unit.

The control unit operates as follows

5 way. The signals from the information receiver at the inputs 19, 20 reset the syndrome register 1 of the device, as well as the triggers 12,13, 26,28, 29 and the counter 44 of the control unit. As a result of this, output 10 from the output of flip-flop 29 through amplifier 34 will give a signal that the device is ready for operation, and output 4 will receive the initial (zero) address of data buffer 11; all other outputs of the control unit will have no signals. In reading mode, the signal from the receiver of information from input 21 sets 1 trigger 12, the output signal of which is output

 6 puts the data buffer 11 of the device into recording mode and, through the OR circuit 16, enters the information input of the D-trigger 26. The negative trailing edge of the first positive clock pulse of the generator 15 superimposed on the output signal of the OR circuit 16 affects the clock input of the D-trigger 26 , sets it to 1 and allows all subsequent positive clock pulses of generator 15 to pass through gate 31 to the inputs of gates 37, 38 and inverter 35. The first output signal of inverter 35 sets 1 trigger 29, resulting in an output e 10 of the control unit and at the output 23 of the device, the ready signal is removed. Passage through the valve 38 open by the output of the trigger 12, the clock pulses are fed to the output 8 of the synchronization of the information source and through the delay circuit 39,

0 circuit OR 41.42 - to outputs 7, 2, 9 of allowing access to the data buffer, shifting the syndrome register and synchronizing the information receiver. The increment of counter 44 occurs along the trailing edge of the enable signal to access the data buffer at output 7. After receiving the code word, counter 44 will contain a binary code of length n codewords. This code, together with the output signal of trigger 12, provides the operation of the valve 23. The output signal of the valve 23 through the OR-NOT circuit 27 closes the valve 31, as a result of which the output from the outputs 2, 7, 8, 9. stops. At the same time, the signal from the output of the circuit And 23 opens the valve 32 and allows the trigger to be set to 1. 28. N + 1 - and the clock pulse of the generator 15. Passing through the And 32 circuit, forms at the output 11 of the control unit an enable signal for the operation of the error selection block of the control symbols of the device. This signal through the inverter 33 and the circuit OR 24 resets the trigger 29 and thereby turns on the output signal 10 ready. On the trailing edge of the same signal, it is set to 1 trigger 28 and closes valve 32. This completes the reading mode. In correction mode, the operation of the control unit is very similar to its operation in read mode. The difference is as follows. After the initial installation, the information receiver supplies a correction signal to input 22 and sets the trigger 13 of the control unit to 1. The output signal of this trigger through amplifiers 30.36 generates at the outputs 5, 3 signals for reading information from the data buffer and for enabling the operation of the error location fixation unit. The output signals of the And 31 circuit, the passage through the valve 37 opened by the trigger 13 output signal, the delay circuit 40, the OR circuits 41, 42 generate at the outputs 7, 2, 9 signals for accessing the data buffer, shifting the syndrome register and synchronizing the information receiver. After transmitting all n characters of the code word., The And 17 circuit works, the output signal of which closes And 31 through the OR-NOT 27 circuit, which stops the output of signals from outputs 2,7, 9. At the same time, the output signal of And 17 circuit through inverter 18 , the OR circuit 24 resets the trigger 29 and a ready signal is set at the output 20.

The proposed device operates as follows. The information receiver checks for the availability of the Ready signal error corrector at the output 23. If the device is ready to work in conjunction with the information receiver, the latter, using the signals supplied to the inputs 19, 20 before reading the code word, resets the syndrome register 1 and restores the control unit 17. The code word is read directly after it arrives at an input 21 from a read signal information receiver. After this, a sequence is formed

0

5

0

5

0

5

0

5

0

5

synchronization signals that are output 24 come to the source of encoded messages. For one read command, one codeword is received and decoded. In response to each clock, the message source transmits one character. These symbols from the input 18 of the error corrector without changes through the block 12 compensation errors are sent to the information output 27 and then to the information receiver, accompanied by synchronization signals at the output 25 of the device. Simultaneously received symbols are written into the data buffer 11 and fed to the feedback unit 5 for division by the generating polynomial. After receiving the next character, the control unit 17 shifts to the right by one bit of the syndrome register 1 and increments by 1 code at the address inputs of the data buffer 11. Thus, during the sequential character-by-symbol division of the received code word, partial residues from the division of all symbols accumulate in the register T codeword, which ultimately form multiplications. on xm error syndrome S (UKOD + v0iu). After receiving all the symbols of the codeword, the control unit 17 generates a signal for enabling the operation of the error selection block of the check symbols 16. Upon completion of the reading mode, the device outputs a ready signal to output 23, to output 26 - a signal indicating the presence or absence of errors in the received codeword and to the output 28 - a signal of the presence or absence of detected errors, errors of control characters. After analyzing the above / signals, the information receiver can read the next codeword if no 3 reception errors have been detected or if the detected errors are related to check symbols. If the information symbols were distorted, then error correction is necessary. Before starting correction, the information receiver supplies a signal to input 19 and brings the control unit to its initial state; however, an error reset signal is not supplied to input 20 in order to save the error syndrome for correcting it. The direct implementation of the correction begins after the input to the input 22 by the information receiver, which was sent to the correction. In this case, the control unit 17 enables the operation of the fixation unit 10, generates read signals for the data buffer 11. shift the syndrome register 1, increments the code at the address inputs of the data buffer 11 The previously received codeword read from the data buffer 11 is transmitted symbolically through the error compensation unit 12, to the output 27 of the device and further to the information receiver. The output symbols are accompanied by synchronization signals at the output 25 of the device. Simultaneously with the generation of the next character, the syndrome register 1 is shifted by one bit to multiply by x the error syndrome it contains. After an error vector is generated in the process of sequential multiplication of the syndrome, block 10 generates a signal that will go to the input of the correction of block 5 and break the feedback of the syndrome register 1. The same signal will go to the correction input of the error compensation block 12 and enable vector transmission errors from the control output of the syndrome register 1 to the error compensation block 12. Block 12 corrects the distorted codeword arriving at it from the data buffer 11 and provides it to the output 27 of the device. The corrected information word from output 27 and the accompanying synchronization signals from output 25 of the error corrector are sent to the information receiver. After completion of the transmission of the corrected message, the error corrector generates a ready signal and outputs it to output 23.

The proposed technical solution eliminates the time spent on correcting control symbol errors and thereby increases the speed of the device.

To illustrate, consider a cyclic (n °, k, m) .- code, e.g., the Hamming code (7.4, 3), (15.11, 14), (31, 26, 5). Here p is the length of the code word, k is the length of the information field, m n - k is the number of control characters. If the distribution is evenly distributed, the probability of an error in the check symbol field for the three Hamming codes mentioned above will be 0.43, respectively; 0.27; 0.16. Thus, the proposed device will increase the speed during correction, respectively, by 43%, 27%, 16%.

Claims (1)

The claims An error corrector comprising a syndrome register, a feedback block, an error detector, a block. fixation 0 5 0 5 0 5 0 5 0 5 an error location, a data buffer, an error correction unit, and a control unit, wherein the output of the feedback unit is connected to the information input of the syndrome register, the outputs of which are connected to the corresponding information inputs of the error detector and the error location fixation unit, the output of which is connected to the inputs of the correction of the feedback unit error correction unit, the output of which is the information output of the device, the output of the error detector is the first control output of the device, information inputs the feedback unit, the data buffer, and the first information input of the error correction block 3Z are combined and are the information input of the device, the control inputs of the error location fixing unit, the error detector, the error correction unit, and the feedback unit are combined and connected to the control output the register of the syndrome, the reset and shift inputs of which are connected respectively to the first and second outputs of the control unit, the third output of which is connected to the enable input of the operation of the error location fixation unit, the second the information input of the error correction block is connected to the output of the data buffer, the address inputs and read inputs, of the access, the accesses of which are connected respectively to the fourth, fifth, sixth and seventh outputs of the control unit, the eighth, ninth and tenth outputs of which are respectively the synchronization output of the information source, the synchronization output of the information receiver and the readiness output of the device, the inputs of the initial installation, error reset, reading and correction of the control unit are respectively the inputs of the initial device device for error checking, reading, and correction of the device, characterized in that, in order to increase the speed of the device by eliminating excessive correction of control characters, a control block for selecting control character errors is introduced into it, the information inputs of which are connected to the outputs of the syndrome register, the eleventh output of the control unit connected to the control input of the check symbol error selection unit, the output of which is the second control output of the device. AND wsg