JPS6386925A - Galois body multiplying circuit - Google Patents

Abstract

PURPOSE:To execute multiplication by using a small ROM, by providing a second circuit means for outputted y.alpha<l> from a first circuit means, and outputting 'o', when xl is '0', and a third circuit means for outputting exclusive OR of its circuit output, in a circuit for processing a digital signal. CONSTITUTION:When inputs (x), (y) of a multiplying circuit such as a Galois body GF2<8> are set to x=x7-alpha<7>+x6.alpha<6>+x5.alpha<5>+x4.-alpha<4>+x3.alpha<3>+x2.alph a<2>+x1.+alphax0, and y=y7.alpha<7>+y6.yalpha<5>+y5.alpha<5>+y4.alpha<4>+y3.alpha<3>+y2.alph a<2>+y1.alpha+y0, z=x.y is expressed as follows: z=x7.(y.alpha<7>)+x6.(y.alpha<6>)+...-+x2.(y.alpha<2>)+x1.(y.alpha)+x0.y. Therefore, a value of (y) is multiplied in advance by 1-alpha<7>, its output makes an output of y.alpha<1> pass through, when xi(i=0...7), set to '0', when said xi is '0', and by taking EXOR of each output, (z) is generated. In this way, a multiplying circuit which can execute multiplecation on a Galois body can be formed by a small circuit quantity and by the one clock without using a ROM.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplication circuit on a field (Gauois field: a set of numbers on which four arithmetic operations such as addition, subtraction, multiplication, and division can be performed, and the number of elements is finite).

[Prior art]

There are two types of Galois field elements: vector representation and exponential representation. If we represent a Galois field whose number of elements is q by GF(q), then on GF (2♂), we have the primitive polynomial P (X )=
Taking an element generated from X'+X' +X3+X2+1 as an example, α8 is expressed as follows.

This vector representation represents a bit configuration, and since multiplication between the elements of the vector representation is complicated, calculations are usually converted to exponential representation.

Vector Expression Exponential Expression A ROM is used for this VE (vector-exponent) conversion and EV (exponent-vector) conversion.

(Problems with the prior art) Therefore, as shown in Figure 5, when performing multiplication with 1 cfLock, three ROMs are required, and as shown in Figure 6, one VE conversion ROM and one EV conversion ROM are required. To perform multiplication in steps of 1 c and 1 ock, use a register.
2 to latch and add 2c 1 och figure and b
cJ2ock is required.

Furthermore, when elements of vector representation are directly multiplied using ROM, a very large ROM is required if the number of elements of the Galois field is large.

[Means for solving problems]

The present invention has been made in view of the above circumstances, and it
The present invention provides a multiplication circuit that can perform multiplication of Galois field elements without using 1 cuoch and with a small amount of circuitry.

〔Example〕

The present invention will be explained in detail below.

For example, regarding the embodiment of the multiplication circuit on GF (2'), if the inputs x and y are expressed as follows, then XgX, I
Q' +xa 'Q' +xs T C!
'''+x4@α4+x3 conflict α3+x211
α2+X, ◆α+X.

y=yy ・α7 +y6 ・α8 +y, ・
α50y4°α4+y3°α'+)'z"α2+ y
＋・α＋'j.

Z=x−y can be expressed as follows.

Z=x7 ・ (y・α7)+xIS φ (y・α6
)+...+x2 ・(y・α2) 4x1・(
y・α)+x0・y Therefore, multiply each value of y by 1 to α7, and when xl (two...7) is 1, the output is y・α1
Z is generated by passing the outputs of , taking the EXOR of each output as 0 when it is 0.

A block circuit diagram thereof is shown in FIG.

The configuration of circuit O is shown in FIG. Multiply y by α sequentially to obtain (α
The circuit configuration is shown in FIG. 3, and this α circuit is well known.

) The output for each is x0・3/? Take ANS with the output of
By passing the outputs through an EXOR circuit Φ, two types of outputs are obtained. Here the leaves indicate the pass line.

In FIG. 4, the configuration has been changed in order to minimize the gate circuit delay caused by stacking seven stages of α circuits. This allows the maximum processing speed to be increased.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a multiplication circuit that can perform multiplication on a Galois field with a small circuit amount and 1 cfLock without using a ROM.

This allows the multiplication circuit to be used as a small partial circuit when forming a gate array.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a multiplication circuit according to the present invention, and FIG.
3 is a diagram showing the configuration of the α circuit in FIG. 1, FIG. 4 is a diagram showing an improvement of the multiplication circuit of the present invention, and FIGS. 5 and 6 are conventional FIG. 2 is a diagram showing a multiplication circuit of FIG. 0------------ A N D circuit, ■---
−−−−−−−−−−Exclusive published by ORC/+II Mentanuki Saya) ■ Pond

Claims (1)

[Claims] In the elements x and y on the Galois field GF(2^m), x=x
＿m＿−＿１・α＾m＾−＾1+x_m＿−＿２・α^
m^-^2+...+x_1・α+x_0 Z=x・y=x_m_-_1・(y・α^m^-^1)
+x_m_-_2・(y・α^m^-^2)+...+
A first circuit means that multiplies y by α (m-1) times by taking advantage of the fact that x_1(y・α)+x_0・y, and At this time, the first circuit means outputs y·α^l, and x_
A Galois field multiplication circuit comprising second circuit means that outputs 0 when l is 0, and third circuit means that outputs an exclusive OR of the circuit outputs.