SU656059A1

SU656059A1 - Arithmetic device

Info

Publication number: SU656059A1
Application number: SU762408654A
Authority: SU
Inventors: Сергей Васильевич Дрофа; Георгий Михайлович Луцкий; Виктор Николаевич Чинок
Priority date: 1976-09-27
Filing date: 1976-09-27
Publication date: 1979-04-05

Description

(54) АРИФМЕТИЧЕСКОЕ УСТРОЙСТВО(54) ARITHMETIC DEVICE

Изобретение относитс к области вычислительной техники и предназначено дл выполнени арифметически.х операций над массивами двоичных чисел по конвейерному принципу.The invention relates to the field of computer technology and is intended to perform arithmetic operations on arrays of binary numbers according to the conveyor principle.

Известны устройства дл выполнени арифметических операций над массивами чисел , работающие по конвейерному принципу 1. С помощью таких устройств возможно перемножение пар чисел, однако перемножение последовательности из t чисел осуществл етс в несколько последовательных этапов. Кроме того, недостатком таких устройств вл етс необходимость одновре .менной выборки из пам ти двух операндов и синхронной передачи этих операндов на первый уровень.Devices are known for performing arithmetic operations on arrays of numbers that work according to the conveyor principle 1. With the help of such devices it is possible to multiply pairs of numbers, however, the multiplication of a sequence of t numbers is carried out in several successive steps. In addition, the disadvantage of such devices is the need to simultaneously select from memory two operands and synchronous transfer of these operands to the first level.

Наиболее близким аналогом вл етс арифметическое устройство, состо щее из п блоков, каждьш из которых содержит первый и второй регистры, выходы которых соединены с первым и вторым входами узла формировани частичного произведени , два триггера, выходы которых соединены со входами первого элемента И, тактирующие входы регистров и триггеров соединены с тактовой щиной, выходы первого регистра и уза формировани частнчного произведени , первого э.1емснта И и первого триггера соединены соответственно со входами первого регистра, второго регистра, первым дополнительным входом второго регистра и нулевым входом первого регистра последующего блока, единичный вход второго триггера соединен первым лЮполнительным выходом блока формировани частичного произведени , входы регистров первого блока соединены с шинами ввода операндов, а нулевые входы триггеров первого.блока - с соответствующими управл ющими тинами 2.The closest analogue is an arithmetic unit consisting of n blocks, each of which contains the first and second registers, the outputs of which are connected to the first and second inputs of the partial product forming unit, two triggers, the outputs of which are connected to the inputs of the first And element, clock inputs registers and triggers are connected to a clock, the outputs of the first register and the formation of the private product, the first terminal and the first trigger are connected respectively to the inputs of the first register, the second About the register, the first additional input of the second register and the zero input of the first register of the subsequent block, the single input of the second trigger is connected to the first AUX output of the partial production block, the inputs of the registers of the first block are connected to the input buses of the operands, and the zero inputs of the first block triggers with the corresponding controls tiny 2.

В этом устройстве в каждом цикле умножени анализируетс только один разр д множител , что ограничивает быстродействие устройства.In this device, in each multiplication cycle, only one bit of the multiplier is analyzed, which limits the speed of the device.

Целью изобретени вл етс повыщение быстродействи .The aim of the invention is to increase the speed.

Дл достижени поставленной цели каждый блок устройства дополнительно содержит узел формировани управл ющих сигпалов , второй элемент И, третий и четвертый триггеры, единичный вход третьего триггера соединен со вторым дополнительным выходом узла формировани частичного произведени , тактирующие входы третьего иTo achieve this goal, each unit of the device additionally contains a control sigpal formation unit, a second AND element, third and fourth triggers, a single input of the third trigger connected to the second additional output of the partial production unit, the clock inputs of the third and

четвертого триггеров подключены к тактовой шине, входы узла формировани управл ющих сигналов подключены к выходам первого , второго и третьего триггеров, первый выход узла формировани управл ющих сигналов подключен к управл ющему входу узла формировани частичного произведени , а второй выход - к единичному, входу четвертого триггера последующего блока , входы второго элемента И подключены к выходам первого и третьего триггеров, а выход второго элемента И подключен ко второму дополнительному входу второго регистра последующего блока, нулевые входы третьего и четвертого триггеров первого блока подключены к соответствующим управл ющим щинам устройства.the fourth flip-flops are connected to the clock bus, the inputs of the control signal generation unit are connected to the outputs of the first, second and third flip-flops, the first output of the control signal generation unit is connected to the control input of the partial production unit, and the second output to the single output of the fourth trigger the subsequent block, the inputs of the second element And are connected to the outputs of the first and third triggers, and the output of the second element And is connected to the second auxiliary input of the second register of the subsequent b eye, zero inputs of the third and fourth flip-flops of the first block are connected to respective control schinam device.

На чертеже изображена функциональна схема арифметического устройства, содержащего п 3 блоков.The drawing shows a functional diagram of an arithmetic unit containing n 3 blocks.

Устройство содержит регистры 1-6, узлы формировани частичного произведени 7-9, триггеры 10-21, узлы формировани управл ющих сигналов 22-24, элементы И 25-30, тактовые щины 31, шины ввода операндов 32, 33, управл ющие шины 34-37. „ .1 - Тто+зк Тн+зк Tia.,.3K ;, + , -Тад-ьзкТм+зкТ ч-зк п T|o+3t T(.|-,.3if-T|2+3 и ак./ Т1о+зк-Т,ц.зи Ти+з и HK+I Т1о+з {Ти.зк V TIO где буквой Т с индексом обозначено состо ние соответствующего триггера, а К О, 1, 2. Индекс при наименовании сигнала пока- 35 зывает, в каком блоке генерируетс этот сигнал . Узлы формировани частичного произведени 7-9 формируют (п + 2) старших разр дов очередного частичного произведени в зависимости от управл ющих сигналов следующим образом. Если управл ющий сигнал «+ о, то на выходах узлов формировани частичных произведений 7-9 будут повтор тьс значени кодов регистров 2, 4, 6. Если управл ющий сигнал «+а, то на выходах узлов формировани частичных про 45 изведений 7-9 будет код суммы содержимого регистров 1 и 2, 3 и 4, 5 и 6 соответственно . Если управл ющий сигнал «+2а, то на выходах узлов 7-9 будет сумма содержимого регистров 2, 4, 6 и сдвинутого у на один разр д влево, содержимого регистров 1, 3, 5 соответственно. Если же управл ющим сигналом вл етс сигнал «- а, то на выходах узлов 7-9 будет разность содержимого регистров 2, 4, 6, и 1, 3, 5 соответственно. Сигнал переноса «П устанавливает триггеры 15, 18 запоминани переносов в следующих блоках в «1, если значение этого сигнала «1, и в «О, если значение его «О.The device contains registers 1-6, units of formation of a partial product 7-9, triggers 10-21, nodes of formation of control signals 22-24, elements I 25-30, clocks 31, input buses of operands 32, 33, control buses 34 -37. „.1 - Тто + зк Тн + зк Tia.,. 3K;, +, -Tad-ьккТм + ЗкТ ч-зк п T | o + 3t T (. | -,. 3if-T | 2 + 3 and ak ./ Т1о + зк-Т, Ц.з Ти + з and HK + И Т1о + з {Ти.кк V TIO where the letter T with the index indicates the state of the corresponding trigger, and К О, 1, 2. The index with the name of the signal shows which block this signal is generated in. The partial product formation nodes 7–9 form (n + 2) most significant bits of the next partial product, depending on the control signals, as follows. If the control signal is “+ o, then the outputs of the nodes of the formation of partial works 7-9 will be repeated The values of the codes of registers 2, 4, 6. If the control signal "+ a, then at the outputs of the nodes of the formation of partial productions 45 pieces of information 7-9 there will be the sum code of the contents of registers 1 and 2, 3 and 4, 5 and 6, respectively. If control The "+ 2a" signal, then the outputs of nodes 7-9 will be the sum of the contents of registers 2, 4, 6 and shifted one by one bit to the left, the contents of registers 1, 3, 5, respectively. If the control signal is the signal "- a, then at the outputs of nodes 7-9 there will be a difference in the contents of registers 2, 4, 6, and 1, 3, 5, respectively. The transfer signal "P sets the triggers 15, 18 of memory transfers in the following blocks to" 1, if the value of this signal is "1, and to" O, if its value is "O.

Регистры 1, 2, узлы 7, 22, триггеры 10, 11, 12, 19, элементы И 25, 26 устройства составл ют первый блок. Регистры 3, 4 узлы 8, 23, триггеры 13, 14, 15, 20, элементы И 27, 28 устройства составл ют его второй блок. Регистры 5, 6, узлы 3, 24, триггеры 16, 17, 18, 21, элементы И 29, 30 образуют третий блок устройства.Registers 1, 2, nodes 7, 22, triggers 10, 11, 12, 19, And devices 25, 26 of the device constitute the first block. The registers 3, 4, nodes 8, 23, triggers 13, 14, 15, 20, and the elements 27, 28 of the device constitute its second block. Registers 5, 6, nodes 3, 24, triggers 16, 17, 18, 21, elements And 29, 30 form the third block of the device.

Claims

For the case of multiplying numbers, registers 1, 3, 5 are multiplier registers, registers 2, 4, 6 are registers of the highest bits of partial products, triggers 12, 15, 18 are triggers of memory transfers, triggers 10, 11, 13, 14, 16, 17 — triggers of storing two lower-order bits of partial products; triggers 19-21 — triggers forming the final result. The forming units of the control signals 22-24 are designed to generate the signals + o, -f a, + 2a, -a, the control units of the formation of partial products 7-9 and the triggers 15, 18 of storing the transfer of subsequent blocks. These signals are produced depending on the states of the 10-18 triggers in accordance with the logical expressions: T + tcT-and + tc T o-tcTVi-fSttTia + SKVE -i .3KTm.3if% j + at T | o + t In the first cycle of operation of the device, the first multiplier of the sequence of binary numbers is received from the input bus of operand 32 to register 1, control signals 34, 35 receive signals that set triggers 10, 11 to the state “O and” 1, respectively. The signal on control bus 36 sets trigger 12 to "O. The control signal generation unit 22 generates the signal "+ a, and since the code O is recorded in register 2, a code appears at the outputs of the partial product generation unit 7. the repetition code recorded in register 1. In the second cycle of operation of the device from the outputs of the partial generation unit produced 7, which determine the magnitudes of the two low-order multipliers, the values of these bits will be written to triggers 10, 11, and from the high-order outputs the information will be rewritten into register 4 of the second block, and thus the factor is shifted by two digits to the right. In the same cycle, the code of the first factor will be rewritten into register 3 of the second block, and register 1 will contain 1 year of a new factor. Thus, in the second clock cycle at the outputs of the partial product generation unit 7, the first partial assignment of the multiplication of two factors is obtained, the lower two bits being the final bits of the total product of the two factors, and in the next cycle can be immediately used for multiplying the desired product to the next sequence multiplier. Therefore, in the third cycle of operation of the device, the third factor is taken into register 1. At the outputs of the partial product formation unit 7, the first partial product is multiplied by the multiplication of three factors, and the lower pair of bits of this product can be used in the next cycle to multiply by the next factor a sequence of numbers, etc. Based on the codes recorded in the trigger 13 and 14 and codes recorded in registers 3 and 4, at the outputs of the partial product formation unit 8, the second partial product occurs, the lower two bits of which are final and determine the second The first pair of numbers is the product of the first two factors, the code of which is written into triggers 13 and 14 and will be used to multiply by the third factor, etc. The accuracy of the representation is determined by the state of the triggers 19-21, which is set by the signal on the control bus 37 If, for example, the code "1" is written in the triggers 19-21, then the states of the triggers 10, 11, 13, 14 and 16, 17 are rewritten through the AND 25-30 elements into two high-order registers 4, 6 and so on. As noted earlier, the codes of these registers are shifted in each clock cycle by two bits to the right, and thus ohm, by the time the multiplication ends, the result code is at the desired position. In the (E + 1) -th cycle, a new sequence of numbers can be accepted for re-multiplication. Consequently, the main advantage of the conveyor principle of information processing, consisting in the effective use of multi-register device equipment, remains. The complete product of a sequence of E numbers is formed in E n ---- cycles, in contrast to the prototype, which performs the same operation in E + E n cycles, where n is the width of the multiplied numbers, i.e. device speed is higher in (1 - b + -0) rep. So, for numbers the bit is 32 and more bits, the speed increases about two times. With the help of such a device, along with the multiplication of a sequence of numbers, it is possible to perform the summation of a sequence of numbers, a shift of numbers, as well as a calculation of the value of the type ((X)..a,x.-fa and some other operations. Claims Arithmetic unit consisting of n blocks, each of which contains the first and second registers, the outputs of which are connected to the first and second inputs of the partial product forming unit, two triggers, the outputs of which are connected to the inputs of the first element, And the clock inputs of registers and triggers connected to the clock, the outputs of the first register and the node of the formation of a partial product, the first element And the first trigger are connected respectively to the inputs of the first register, the second register first The secondary input of the second register and the zero input of the first register of the subsequent block, the single input of the second trigger are connected to the first additional output of the partial generation unit, the inputs of the registers of the first block are connected to the input buses of operands, and the zero inputs of the first block triggers to the corresponding control buses, characterized in that, in order to increase speed, each unit of the device additionally contains a node for generating control signals, a second element AND, a third and a quarter the third trigger, the single input of the third trigger is connected to the second additional output of the partial generation unit, the clock inputs of the third and fourth triggers are connected to the clock, the inputs of the control signal generation node are connected to the outputs of the first, second, and third triggers, the first output of the control signal generation node The signals are connected to the control input of the partial product forming unit, and the second output is connected to the single input of the fourth trigger of the subsequent block, the inputs of the second power The elements AND are connected to the outputs of the first and third triggers, and the output of the second element I is connected to the second auxiliary input of the second register of the subsequent block, the zero inputs of the third and fourth triggers of the first block are connected to the corresponding control layers of the device. Sources of information taken into account in the examination: 1.Newborn Motsgo Propogation logic structures, Progress. Nat. Electron. Couf. Chicago, 1966, III, V. 22.

2. USSR author's certificate Xo 479111, cl. G 06 F 7/52, 1973.