SU758163A1 - Device for spectral conversion - Google Patents

Description

The invention relates to digital computing and can be used to create specialized computers for spectral analysis of processes and 5 signals, simulators of random processes with given (controlled) spectral characteristics, computational modeling complexes for testing electronic technology in ’θ

vibration, shock, electrical and other effects.

The known devices for spectral analysis of processes and signals allow to obtain a spectrum or spectrum of 15 power in one of the basic systems of the function VI ·

Closest to the invention is a two-dimensional spectrum analyzer that contains a generator of clock pulses of 20 ows, a modulo two adder, which is a unit of addition modulo two, a switch, which consists of two conjuncture blocks, a control unit, an adder-subtractor, which is a conventional binary adder, two Walsh function generators, which are the basic function setting unit, a conjunctor, a trigger, and a readout node £ 2].

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The device allows to calculate the power spectrum of Walsh P ^ Dg), g * 1,

2, ..., Ν / 2-1, process x (^), 9 “

= 0, 1,. .., Ν-1.

The main disadvantage of the known devices for spectral analysis, inherent in the full and the prototype, is the fundamental impossibility of obtaining the power spectrum of Walsh P ^ (r) directly from the power spectrum of Fourier.

The aim of the invention is to simplify the device and improve performance. , ''

For this purpose, a device for spectral transformations, containing an addition unit modulo 2, two groups of elements, a constant setting unit, an adder, a control unit, a clock generator, whose input is connected to the first output of the control unit, the output of the adder is the output of the device, and the block of the task of constants is connected to the first inputs of the elements AND of the first group, two registers are entered, three selection blocks, three OR elements, a Gray code generator, two groups of OR elements, a multiplication unit, a memory block, a cyclic shift register hectare counter

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^ tsva generator single pulses, code pulse converter, a group of reversible counters, shift register, and the output of the memory block is connected to the first inputs of elements AND of the first group, the outputs of which are connected respectively to the first inputs of the elements OR of the first group, the outputs of which are connected to the first input of the multiplication unit, and its output is connected to the input of the adder, the first output of the generator of the gray code is connected to the input of the first register, the output of which is connected to the first input of the addition unit modulo 2, and its output is connected to The first entrance of the first selection unit; the outputs of the selection unit are connected to the inputs of the first OR element, the output of which is connected to the second input of the constant setting unit and the first input of the second OR element, and its output is connected to the input of the first single pulse generator, the output of which is connected to the first input of the cyclic shift register, the first output of which connected to the second inputs of the elements of the first and second groups and the second input of the multiplication unit, and the second output of the cyclic shift register is connected to the first input of the second selection unit, the first input of the pulse-pulse about the transducer, the second input of the first selection unit and the first input of the third selection unit, the outputs of which are connected to the input of the third OR element, the output of which is connected to the second input of the constant setting unit, the second output of the Gray code generator is connected to the input

second register; the output of the second register is connected to the second input of the third selection unit and the second input of the addition unit via node 2, the second output of the control unit is connected to the input of the second single pulse generator, the output of which is connected to the second input of the cyclic shift register, the first input of the counter and the first inputs of the reversible group counters The outputs of which are connected to the second input of the second selection unit, the outputs of which are connected to the inputs of the OR elements of the second group, the outputs of which are connected to the first input of the shift register, the output of which It is connected to the third input of the block for specifying constants, the third output of the control unit is connected to the second input of the second element OR, the fourth output of the block. control is connected to the second inputs of the reversible group counters, the second input of the shift register, the first input of the gray code generator and the second input of the counter, the output of which is connected to the first input of the memory block, the second input of which is the first input of the device, the output of the clock generator connected to the second input

pulse-code converter, the output of which is connected to the third

the input of the shift register, while the second input of the generator of the gray code is the second input of the device ..

FIG. 1 shows a block diagram of a device for spectral transformations; in fig. 2 shows examples of circuit solutions of the first selection unit, the block of reversible counters and the group of elements OR; in fig. 3 shows an example of the schematic of the second ή third selection block.

The device contains the generator 1 of Gray code, the first 2 and second 3 registers, block 4 addition modulo 2, blocks selection 5, 6 and 7, the elements OR 8, 9 and 10, block 11 controls, block 12 job constants, Kodo-pulse Converter 13, a group of 14 reversible counters, a group of elements OR 15 and 16, a shift register 17, a group of elements AND 18 and 19, a memory block 20, a cyclic shift register 21, a counter 22, a generator 23 clock pulses, the first 24 and second 25 single generators pulses, block 26 multiplication and adder 27.

Consider the main functions performed by each of the structural components of the device.

The generator 1 of the gray code is designed to form a sequence of gray codes corresponding to the numbers of the components of the Walsh power spectrum g, the value of which must be calculated.

The first 2 and second 3 registers are used to store the pairs of Gray codes K (2g – 1) and B (2g), respectively, where ge (1, 2, ..., N / 2-1) is the number of the component of the Walsh power spectrum.

Block 2 addition modulo two performs the addition operation modulo two over pairs of gray codes.

The first block 5 of the selection, containing t, t = 1, 2, ..., 1od.M elements And 28 with a different number of inputs and outputs, selects and transfers to the output one of the basic codes of the numbers of constants; the selection is performed in accordance with the control code stored in the cyclic shift register 21.

The second 6 and third 7 blocks, containing in tons of elements, and 31 selections are intended to extract from the code supplied to the input, the values of one digit, the number of which is specified in the process of operation by the cyclic shift register 21.

. The elements OR 8 and 9 perform a logical disjunction operation on all bits of the converted K (2d – 1) and B (2d) codes, respectively, to control the operation of block 12 for specifying constants.

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The element OR 10 is designed to control the first generator 24 single pulses.

Unit 11 controls the formation of control signals in the operation of the device. five

Unit 12 of the task of constants is designed to form the values of the modules of trigonometric functions' β \ ηκπ / 2Ί) οθ5ΚΧ / 2Ί, ₁₀

The code-pulse converter 13 forms groups of pulse signals for conversion by shifting the code recorded in the shift register 17. ₁₅

Block 14 reversible counters contains t reversible counters 29 with. different conversion factors K _b ) = 2 °, 2 ' ⁴ . . .2 '- *, ί = 1, 2 ... t, where ΐ is the sequence number of the counter in the group of 14 reversible counters.

Group 14 of reversible counters forms a group of tons of base numbers of constants, the value of which is determined in the process of operation __ block 12 of the task of constants.

The group of 15 OR elements is intended for conversion by the logical addition of two 1-bit codes of Fourier power spectrum coefficients, one of which is zero, and 30 is one I-digit code.

The group of 16 elements OR, containing t-1 elements OR 30 with t inputs is used to convert base t, t = 1, 2, ..., 1 _{g of} M codes · 35 constant numbers, of which t-1 number codes are zero after the selection operations performed by the first block 5 of the selection, into one t-bit code of the base number of the constant required at this stage of the device calculations.

The shift register 17 converts the code of the base number. constants to a real number of a contant of the stationary by group shifts to the left according to the signals generated by the code-pulse converter 13.

Groups of elements And 18 and 19 predna-. are assigned to transmit codes through a group of 15 OR elements to the multiplication unit 25 by a control signal, Ods. Miracle cyclic shift register 21.

The memory unit 20 is designed to store the coefficients of the transformable Fourier power spectrum.

The cyclic shift register 21 controls, during the operation of the device, selection blocks 5, 6 and 7, converter No. 13, as well as groups of elements I 18>

19 and block 26 multiplication.

The counter 22 is designed to address the Fourier power spectrum coefficients stored in memory block 20, '65

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addressing is carried out in the natural order.

The clock generator 23 generates clock signals for the operation of the code-pulse converter 13.

The first 24 and second 25 single pulse generators generate control signals for the operation of the cyclic shift register 21.

The operating part of the device includes blocks 26 multiplication and adder 27 accumulating type.

Before the device starts working, two t-bit gray codes are recorded from the first input of the device to the local memory of the generator 1 of the gray code; K (2g-1), r = r ,, is the initial state of the generator 1 of the Gray code, from which the formation of a sequence of codes begins. The second code K (2 g), g = g _g , g _g >,

^r g ^e ί? ' 2, ..., Ν / 2-1) defines the end of generation. These source data of the device determine, respectively, the numbers of the first g and the last g _{g of} the Walsh power spectrum coefficients, which must be calculated from the known coefficients of the Fourier power spectrum.

In block 20, the memory is sequentially recorded from the second input of the device Ν / 2—1 of the coefficients of the Fourier power spectrum at the addresses formed in the natural sequence of the sequence by the counter 22. The procedure for entering the initial data ends with zeroing. all bits of the adder 26 accumulating type.

In order to simplify further consideration of the operation of the device, we conditionally select five cycles in its operation, which reflect the sequence of calculations and the interrelation of blocks.

The execution of the first preparatory cycle of operation of the device is provided by a signal from the second output of the control unit 11, according to which the initial state is set. Zero codes are recorded in all t counters of the group 14 of reversible counters, as well as in the shift register 17 and counter 22. According to this signal, the generator 1 of the gray code forms a pair of codes K (2g-1) and K (2g) corresponding to a given gy number (1, 2, .., H / 2—1) of the Walsh power spectrum coefficient, which are transmitted to the first 2 and the second 3 registers, respectively. Thus, for example, when r - the signal from the second output of the control block 11, the generator 1 of the gray code will generate the codes K (2g-1) and k (2g), which are gray codes from the numbers 2g ₄ - 1 and _{2 4} .

The second preparatory cycle of the device is provided by the signal

)

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with the first output of the control unit 11, but which is used to start the generator ρτοροΐο 25 single pulses and set the order number of the initial t + 1-digit code 00 ... 01 in the cyclic shift register 10, unit 1 in the first digits of all t counters groups 14 reversible counters, -a also write the starting address to counter 22, which stores the first power spectrum factor of the Fourier memory block 20.

The execution of the third cycle of operation of the device is provided by a signal from the output of the control unit 11. Due to the well-known property of modulo two two successive Gray codes, at the output of block 4 of addition modulo two, a t-bit code is always formed with a unit value in only one of the digits and the remaining zeros. The gray code K (2 g) and the sum code .8 (2 g-1) © K (2g) are fed to the inputs of the selection blocks 6 and 7, respectively controlled by the second inputs by the code written in cyclic shift register 21. Since in the second cycle of operation of the device in the cyclic register .21 shift, the unit was recorded in the first digit of 00 ... 01, then at the output of 7 selection blocks b and 7, the first digits of the K (2d) and K (2g-1 ) © 8 '(2g), respectively. After the operation of disjunction over the t-bit codes, performed by the elements OR 8 and 9, the signals are fed to the inputs of the block 12 of the task of constants. The voltage level corresponding to the logical unit at the input of the block 12 of the task of constants determines the mode of formation of the values of the function \ 51pcZS / 2 ’) (the first group of constants). The level of the logical unit at the output of the element OR 9 is a sign that the formation of the number of a constant should be blocked, it is considered that the constant is defined in advance and is equal to one ·, the device switches to repeating the third operation cycle at a new value of 1. The next value is generated by the signal from output element OR 9 (the level of logical units), which is fed to the input element OR 10 and starts the first generator 24 single pulses. A single pulse generated by the generator 24 single pulses, shifts the unit recorded in the cyclic register 10 shift one digit in the direction of the older ones. Thus, in the latter, a (t + 1) -bit code 00 ... 010 is written, which ensures switching of the second b and third 7 selection blocks to the selection of the second digit of the K (2d) and 8 {2g-1) code in K (2 d) respectively, i.e. transition to the repetition of the third cycle of the device.

The logical zero level at the output of the element OR 8 is a sign that it is necessary to proceed to the formation of a valid constant number for the base number of the constant specified in the group 14 of reversible counters, which is performed on the fourth cycle of the device operation.

The fourth cycle of operation of the device is provided with a signal from the fourth input of the control unit 11. The first block 5 of the selection transfers to the output a status code (code of the base number of the constant) only of that of the t-reversible counters of group 14 reversible counters, the number of which is indicated by one in the corresponding digit of the cyclic shift register 21. For example, if in the cyclic shift register 21 a (t + 1) -dimensional row code 00 ... 010 is written, then the first block 5 of the selection selects and outputs the state code of the second counter, which is 01. Thus, the highlighted code 1 th counter from the output of the first block 5 selection through a group of elements OR 16 is written to the shift register 17. The control unit 11 from the fourth output starts the pulse generator 23, which in turn turns on the code-pulse converter 13. The latter converts the code arriving at its second input from the cyclic shift register 21 into a sequence of pulse signals taken from its output to the third input register 17 shift. Kodo-pulse Converter 17 operates in accordance with the expression

ι

where R. is a transformation operator; g ¹ ' ⁴ - the code recorded in the cyclic shift register 10', t- (1-1) - the number of pulses at the output of the code-pulse converter 13.

The code generated in the register 17 is the actual constant number from the first or second group of constants of the constant setting block 12, the value of which is transmitted to the first input of a group of 18 elements And controlled by the second output of the cyclic shift register 21 to the inverse second input. With all possible code combinations

the latter, of the form 2 ⁴ , ϊ = 1,2, -, t, at its second output, a low voltage level is formed, which permits the transmission of a constant code to the input of a group of 15 elements OR through a group of 18 AND elements, blocks the operation of a group of 19 AND elements and defines 9

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The first mode of block 26 multiplies. Thus, the formation in the cyclic register of the shift shift sequence 1-L

Code Number 2

provides the calculation unit 26 multiplication in the first mode with

and storing this result in the local memory of the latter. When ΐ = m + 1, the state of the cyclic shift register 21 is defined by the code 2 ¹ ' ⁴ , i.e. up unit in the (m + 1) th digit than the generated logic high voltage level at its second output, which blocks on the inverted input of the AND group 18 includes a group of operation elements 19 and ¹³ and switching chaet multiplying unit 26 in the second mode. In this mode, multiplication of each coefficient B *., Stored in memory block 20 and transmitted through a group of 19 elements 20 AND and a group of 15 elements OR to the first input of multiplication unit 26, is provided with the number recorded in the local memory of the latter. For K = 1, the product В ^ Л-А? Is calculated, and transferred to the sum-25 is the matrix 27, which has a zero initial state, as the first partial sum k, | . This ends the first cycle of the device.

The second cycle of operation of the device starts at the signal of the end of the summation operation generated by the adder 27, which transfers the device to the second preparatory cycle, setting the initial state 00 ... 01 of the cyclic shift register 10 to 35, increasing the counter content unit groups of 14 reversible counters and counter 22 (K = 2). As a result of performing up to the second cycle of operation, the second partial sum is formed in the adder then THEN

'' Β -,. Λ + в.ти А? _g .

by measure r,, r ,, e {1, ..., / 2-1). Job . the device is finished if the condition was set to convert only one power spectrum coefficient of Walsh, i.e. = g _and Otherwise, when Gd /, g _l <g _g begins

the next stage, the calculations from the first preparatory cycle, as a result of which all blocks of the device are reset,

A new pair of gray codes K (2g-1) and K (2 g) is generated by the generator 1 of the gray code for the number of the Walsh power spectrum coefficient equal to r = + 1 and is rewritten into the first 2 and second 3 registers respectively (writing gray codes 8 (2g -1) and K (2g) in registers in a different sequence does not matter in principle, i.e., it is permissible that code 8 (2g-1) is copied to the second register 3, and code K (2g) to the first register 2). The subsequent operation of the device does not differ from that described above and the calculations continue until the relationship r = r ₂ is satisfied, where r _r is the number of the last component of the Walsh power spectrum stored in the Gray code in the local memory of the generator 1 of the Gray code. Thus, for r ^ - + 1 stages of functioning

the device ensures the formation of the output r _g - + 1 coefficients

Walsh power spectrum, where η and can define any interval of the sequence 1, 2, ..., N / 2—1.

Thus, the technical and economic efficiency of the proposed device for spectral conversion is determined by simplifying the calculation of the Walsh power spectrum with a known Fourier power spectrum, a reduction in the laboriousness of obtaining a Walsh power spectrum and an increase in the productivity of work.

When K = n-1 in the adder 27 will receive the value of the first coefficient of the power spectrum Fourier

П-А ТО 50

which is transmitted to the output of the device, and when the number is removed from the output 55 of the adder 27, multiplication is made by the scale factor p, proportional to the degree of two, by transferring the comma separating the integer and fractional parts

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p-1 then

U /. = & · Σ.-In LA? H K;

This concludes the first stage of the calculations, as a result of which the coefficient of the Walsh power spectrum with no less than 65

Claims (2)

Claim A device for spectral transformations containing an addition unit modulo 2, two groups of elements AND, a constant setting unit, an adder, a control unit, a clock pulse generator whose input is connected to the first output of the control unit, an output of the adder is the device output, and an output of the constant specifying unit connected to the first inputs of elements AND of the first group, characterized in that, in order to simplify the device and increase its speed, it contains two registers, three selection units, three elements OR, Gray code generator, d OR e group of elements, the multiplication unit, a memory, a cyclic shift register, a counter, two single-pulse generator, kodo11 758163 '12 a pulse converter, a group of reversible counters, a shift register, the output of the memory block is connected to the first outputs of elements AND of the first group, whose outputs are CONNECTED respectively to the first inputs of the elements OR of the first group whose outputs are connected to the first input of the multiplication unit, and its output is connected to the input of the adder, the first output of the generator of the gray code is connected to the input of the first register, the output of which is connected to the first input of the modulo addition unit 2, the output of which is connected to the first input of the first selection unit, the outputs of which are connected to the inputs of the first OR element, the output of which is connected to the second input of the constant setting unit and the first input of the second OR element, whose output is connected to the input of the first single pulse generator, the output of which is connected to the first input of the cyclic shift register, the first output of which is connected to the second inputs of the elements of the first and second groups and the second input of the multiplication unit, and the second output of the cyclic shift register is connected to the first input of the second selection block, the first input of the code-pulse the converter, the second input of the first selection unit and the first input of the third selection unit, the outputs of which are connected to the input of the third OR element, the output of which is connected to the second input of the constant setting unit, the second output of the Gray code generator connected to the input of the second register, the output of which is connected to the second the entrance of the third block ten 15 20 25 thirty 35 selection, and the second input of the adder modulo 2, the second output of the control unit is connected to the input of the second. generator of single pulses, the output of which is connected to the second input of the cyclic shift register, the first input of the counter and the first inputs of reversible counters of the group, the outputs of which are connected to the second input of the second selection unit, the outputs of which are connected to the inputs of the elements of the second group, the outputs of which are connected to the first input the shift register, the output of which is connected to the third input of the constant setting unit, the third output of the control unit is connected to the second input of the second OR element, the fourth output of the control unit is co inn with the second inputs of the reversible group counters, - the second input of the shift register, the first input of the gray code generator and the second input of the counter, the output of which is connected to the first input of the memory unit, the second input of which is the first input of the device, the output of the clock generator -pulse transducer, the output of which is connected to the third input of the shift register, while the second input of the generator of the gray code is the second input of the device. Source of information taken into account in the examination 1. USSR author's certificate No. 382091, cl. C 06 R 15/34, 1973. 2. USSR author's certificate. ”519642, cl. From 01 to 23/00, 1976 (prototype). 758163 1 758163 Φια.2 758163 TO benefits 'Output