SU525087A1 - Device for calculating the square root - Google Patents

Description

DEVICE FOR YOUR PRODUCT, AEN1-1I SQUARE

The invention relates to construction equipment and is intended for use in computational machines operating in real time.

Devices are known for calculating the square root J1. Containing registers, accumulators of accumulative type, counter cycles, log elements and shift schemes up to rp bits, inclusive. In these devices, an asynchronous algorithm is used, which allows for some code combinations of sub-expressions to achieve a significant increase in speed. However, for a whole range of e codes ({x | 77 1), the efficiency of this algorithm is significantly reduced and within the limits of the range of these devices can be equal to the speed of devices using synchronous (with fixed for the required accuracy, the number of calculation steps) al orrhythms .. Except Moreover, for this algorithm there is a need to analyze groups of residual bits, which leads to additional equipment consumption, and.

as follows, reducing the reliability and manufacturability of the device in the case.

HaH6ejiee close to the technical community of this invention is the EU L -. using a synchronous algorithm and co / jep / xaiuee accumulator, register, trigger, shift register, control unit, two elements and, the register output is connected to the primary.-:

the input of the accumulator, the output of which is connected to the trigger input, the output of which is connected to the first input of the control unit, the first input of the first element I, the first input of the second element I and the second input of the accumulator, the third input is connected to the output of the block control, the second input of which is connected to the output of the shift register of the result. The scheme of such a device is comparatively complex and, therefore, high hardware costs.

The invention is a simplification of the device.

This is achieved in that the device contains a correction unit, the first output of which is connected to the second input of the second element I, the output of which is connected to the fourth input of the accumulator, the fifth input of which is connected to the second output of the correction unit, and the sixth input of the accumulator-accumulator is connected to the third output of the correction unit and the second input of the first element I, whose output is connected to the input of the shift register of the result.

The drawing shows a diagram of the device.

The device contains register 1, accumulator 2, result shift register 3, control unit 4, trigger 5 and correction unit 6, elements 7, 8.

The accumulator 2 consists of the combinational adder 9 and the accumulator 10. The adder 9 is intended for operation, with the numbers in the additional code. The operation mode of the adder is determined by the state of the 5-digit trigger. The output of the trigger 5 is connected to the control inputs of the control unit 4 and the transfer circuit to the lower bit of the adder 9.

The zero state of flip-flop 5 for the combining adder 9 corresponds to the Subtract mode. In this case, the code of the deductible as it passes through the control unit 4 is inverted, and a transfer presence signal is generated in the transfer chain to the low-order bit of the combinational adder 9. If trigger 5 is in state 1, which corresponds to summation mode for combinational adder 9, then control unit 4 receives the second addend code directly to the combinational adder and the transfer signal is missing at the input of the lower bit of the combinational adder 9.

Before starting the calculation, the radic expression is in register 1. Drive 1O, register 3 shift the result and trigger 5 are zeroed out, and code 111 is entered into the correction block 6. Accordingly, in the first calculation step, the Subtraction mode is performed.

The two lower digits of the decrement are fed to the input of the combinational adder 9 of the two higher bits of register 1, the rest of the bits receive information from accumulator 1O with a shift of two digits to the left. The inverse code of the deductible is transmitted to the adder from the shift register of the results and from the low-order bit of the correction unit 6, information from its other two bits is fed to the adder without inverting. The result of the calculation fixes in the accumulator Y. At the end of the first step of the calculation, the contents of register 1 are shifted by two bits to the left, and the shift register of result 3 by one bits to the left, while in the lower part of register 3, the contents of the senior bit of correction block 6, after which this bit is zeroed and a fixed code box is stored in correction block 6 until the end of the calculations. In trigger 5, information is entered from the sign bit of the combinational adder 9. From this point on, the device is ready to execute the second computation step.

Further, the execution of the operation in each step is reduced to the following;

transferring the contents of accumulator 1O to the combinational adder 9 with a shift of two times to the left, information from the two most significant bits of register 1 is recorded in two bits, respectively;

transfer to the adder the contents of the shift register of the result 3 and the correction block 6;

summation (subtraction);

recording the result of the summation (subtraction) into the drive U, and the information from the sign bit of the combinational adder 9 per trigger 5;

the shift of the contents of register 1 and 3, while the next digit of the result is entered into the lower bit of register 3.

At the end of the last calculation step, the result of the calculation is found in the shift register of the result.

The use of this invention allows to simplify the circuit of the device and, therefore, the hardware costs in its production.

Claims (2)

1.Avt. St. No. 435522 Cl. & O6 F 7/38, O5, O7.74 2. Avt. St. No. 239665, cl. UO6F 7/38, 18.O3.69. BUT III