JPS6154722A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To simplify the whole circuit constitution by composing the arithmetic circuit of the 1st and the 2nd (n)-bit full-adders, supplying 1 to the carry input of the least significant digit bit in the 1st full-adder all the time, and adding the addition output of the 1st full-adder to a numeral whose (n) bits are all 1 by the 2nd full-adder. CONSTITUTION:When addition of mod3 is performed when n=1 in a Galois field GF(2<n>), an mod(2<n>-1) arithmetic circuit consists of the 1st and the 2nd full-adders ADD2 for two bits of A(A2, A1) and B(B2, B1). Then 1 is supplied to the carry input C0 of the least significant digit bit of the 1st full-adder ADD1 all the time and the carry output C2 of the most significant digit bit of the 1st full- adder ADD1 is supplied to the carry input C0' of the least significant digit bit of the 2nd (n)-bit full-adder as well; and the 2nd full-adder ADD2 adds the numeral consisting of bits which are all 1 to addition outputs SIGMA1 and SIGMA2 of the 1st full-adder ADD1 to obtain SIGMA1' and SIGMA2' as arithmetic results of mod3.

Description

[Detailed description of the invention] The present invention is a Galois field GF (2
'), especially mod (2') used for multiplication and division.
-1) Regarding arithmetic circuits.

Generally, Galois field GF (2) is used as an error correction code in encoding or decoding/correction devices, and multiplication and division in Galois field GF (2') are performed using Galois field GF. m that converts the element of (2”) into the power form of the primitive root α
It is determined by addition and subtraction of ad(2-1).

Conventionally 1 For example, in order to perform addition of mod 3 when n = 2, 44 mods were created as shown in Figure 3.
A d(2%-1) arithmetic circuit is used. That is,
That is A (A2 + AH), B (Bz + Bl)
It consists of a first full adder ADD1 for 2 bits and a second full adder ΔDD2 for 2 bits. For finger up input of full adder ADD 2. ' to -Ij and also the first full-width g device Al) A in DI, 13Q) j
olt n fB force Σ0. Xz wom 2 (7)
Full-width 'j: I R'aΔD D One bit of human power A, ', AX', and
The least significant bit 81' of the local input to the second full adder ADD2 is connected to the addition output Σ2. When Σλ is all 11171, l''' is given, and # is given to bit IJJ' of the pond.
Let OII be manually powered and its second full adder AD
The addition outputs Σ, ′, Σ2゛ in D2 are mad(2-1
) is used as the calculation result.

Note that Table 1 shows the addition table at that time.

As can be seen from this example, the conventional mod (2n-1
) The arithmetic circuit requires means for determining whether all the output bits of the first full adder ADDI are "1",
Particularly when the value of n is large, the circuit scale increases.

The present invention has been made in consideration of the above points, and it is possible to calculate the total sum without providing a means for determining whether the output binos 1- of the first total addition z:( are all II + II or not. mad(2
7L-1) Arithmetic circuit k Q (i") Ab.

In order to achieve the purpose of the present invention, the first
'
1, and connect the carry output terminal of the most significant bit in the first full adder to the H7 carry input terminal of the lowest bit 1- in the second full adder of the same < n bits,
The addition output of the first full adder and all n bits in the second full adder.

is 11111, and the result is m o
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

To simplify the explanation, we will now discuss in detail the case where addition of mod :l is performed when n=2 in the Galois field GF(2'').

Figure 1 shows the structure of the mod (24'-1) arithmetic circuit at that time, with A (A4. A+), B
The first full adder ADDI for 2 bits consists of (BJIB, ) and the second full adder ADD for 2 bits as well.
2, it always gives "bi' to the raised finger input C, of the lowest bit 1- in the first full adder ADr)l, and also gives the most significant bit (to the first full adder ΔDDI) The carry output C2 is manually carried to the lowest pitch 1 in the second full adder ADD2 of n pitch 1-.
', and in its second full-width $7 device ADD2, the first
The addition output Σ1 of the full adder A l) D I. Σ2 and the value of all pits'"1" (in this case B' = 1.8'
= 1 and n = 3), the result is Σ1', Σl is m
The calculation result of ad3 is used.

In such a configuration, each full adder ADD
1. Addition details in ADD2 are shown in Tables 2 to 5 below.
The explanation will be based on each truth table listed above.

In other words, the addition in the first full adder Ar) DI should be in the truth 1 direct table shown in Tables 2 and 3! It is carried out in seven days.

Table 2 Table: 3 From its removal 2.

Σ, = A, OB, ■l ... (1
, C,=A,+B,...
(2) Also, from Table 3, Σyu” A4 ■ B2 ■ C1... (3) c, =
A, B, + A, C, + B, C1... (4
).

However, ■ represents an exclusive OR, and + represents a logical OR. The same applies below.

Further, the addition in the second full adder ADD2 is performed according to the truth tables shown in Tables 4 and 5.

Table 4 Table 5 From its removal 4, Σ1'=Σ, ■l■C6... (5) C1'=Σ,
C1... ((8) Also, from Table 5, Σ□' = Σ2■l■C8' ・ (
7).

In this way, the mad3 addition results Σ, ', Σλ' obtained by the above equations (5) and (6), respectively, are calculated by −M with the adder shown in Table 1 above.

In addition, FIG. 2 shows the mod (2”-1) according to the present invention.
An example of circuit 11r# is shown when the arithmetic circuit is expanded to n bits.

Here, a 1-bit adder is connected to a first full adder (Ar) I in which 1 bit of adder is cascaded, and a second 1-bit adder is connected in cascade to n pits.
a first full adder ΔDD2, and a first full adder ADD
The carry power of the lowest pick 1 in l is always ``
I 11 and its first full adder ADD
The carry output (4) of the most significant bit 1- in I is applied to the carry input C0' of the least significant bit 1- which is input to the second full adder ADD2. The addition output Σ, ~Σ2 of the full adder ADD1 of 1 and the numerical value of all bits "1°" are added, and the result Σ1' ~ Σ- is m
The calculation result is od(2'-1).

In the mad(2'-1) arithmetic circuit according to the present invention, it is necessary to provide means for determining whether all the output bits of the first full adder circuit are 111Hg, as in the conventional case. This has the great advantage of simplifying the overall circuit layering, which is especially useful when the number of bits increases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a mod (2'-1) arithmetic circuit according to the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention. FIG. 3 is a block diagram showing a conventional mod (2''-1) function Q'' circuit. ADD L...First full adder At)D2...Second full adder

Claims (1)

[Claims] A first full adder of n bits and a second full adder also of n bits.
1 is always given to the carry input of the least significant bit of the first full adder, and the carry output terminal of the most significant bit of the first full adder and the carry input of the second full adder are Connect the carry input terminal of the least significant bit in the adder,
A mod (2^n-1) arithmetic circuit that causes the second full adder to add the addition output of the first full adder and a numerical value in which all n bits are "1".