JPS58201141A - Multiplier - Google Patents

Abstract

PURPOSE:To improve a multiplication speed and multiplication precision at the same time, by sending the outputs of arithmetic circuits to the output lines of two systems, and separating the multiplication output into the high-order and low-order digit bits. CONSTITUTION:Arithmetic circuits 4a-4b consist of a 1-bit multiplying circuit, 3-input adding circuit, and carry output holding circuit of the adding circuit, respectively. Signal processing circuits 18a-18d output signals from input terminals (a) when a control signal (c) is at a high level, or from input terminals (b) when at a low level. While the sums of the adding circuits are outputted to a low-order digit bit signal output line 20 by the signal processing circuits 18a- 18d and the control signal ''c'', propagation to trailing elements is canceled by AND circuits 19a-19d. Consequently, all outputs are obtained successively while the high-order and low-order digita bits of the arithmetic results are made independent of each other.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel multiplication device that can obtain all pits as a multiplication result without providing a guard time.

Conventionally, a pipeline type multiplication device, for example, outputs 2 pages of upper n bits by dropping the lower n bits of the 2n bits of the nXn bit multiplication result, or inserts a guard time of n bits between input signals. Insert and 2nl? It was intended to obtain the following output. That is, in the former case, multiplication accuracy was sacrificed, and in the latter case, multiplication speed was sacrificed.

Figure 1 shows the configuration of a pipeline multiplier that obtains the output of all bits by providing a card time. In the case of n = 4 bits ((X) is the multiplicand and (y) is the multiplier) Show about. In the same figure, 1 a-1
d and 2a-'-2d are delay circuits equivalent to 1 bit, 3a
-3d are latch circuits, each of which latches the (y) signal based on the output signal of the delay circuit 1. 4a to 4d are arithmetic circuits, 5 is the output of the delay circuit 1, and 6 is a signal input line (y).

Here, the arithmetic circuit arithmetic circuits 4a to 4d consist of a 1-bit multiplication circuit, a three-manual addition circuit, and a carry output holding circuit of the above-mentioned addition circuit. That is, the multiplication of the signals on the signal lines 7 and 8, the result of this multiplication, the signal on the signal line 9, and the output of the carry output holding circuit become inputs to the three-manpower adding circuit. The sum of the addition results of the arithmetic circuits 4a to 3 and page 4d is output to the signal line 9.

10 to 13 are calculation elements. 14 is a signal line to which the control signal (C) is input; 16 is a signal line to which the multiplier (yl signal is input; 16 is a signal line to which the multiplicand (,) signal is applied;
1 is a signal line that outputs an output (z) signal. In this way, a pipeline type 4×4 (bit) multiplication device is constructed.

Next, the operation of this configuration will be briefly explained. (X)=(xo
x1x2x3) (xo:MSB), (y)-(y.

y y y ) (y: MSB), (z)
-(zOzll 2 3.

---------z 7) (zo: MS B)
If we consider the multiplication (x)·(y)−(z)&, this multiplication can be expressed as follows.

xox1x2x3 ′cOy3x1y3x2y3x3y3 xOy2x1y2x2y2x3y2 xOy1x1y1x2y1x3y1 zo zl z2 z3 z4 z6 z6
z7 First, at time T1, y3 is latched by the latch circuit 3a, and x3 is output from the delay circuit 2a.

Therefore, x3y3 is output from the arithmetic circuit 4a, and awn x3y3 is output to the output signal line 17. Next, at time T2, y3 continues to be latched in the latch circuit 3a, and y2 is latched in the latch circuit 3b. At this time, x2 is output from the delay circuit 2a, and x3 is output from the delay circuit 2b.

Therefore, x2"3 is output from the arithmetic circuit 4a.

Also, put it in the arithmetic circuit 4b)? [Yo”2”3 and”3”
2 is added, the carry is held in the arithmetic circuit 4b, and the sum is output to the signal line 17 at the same time. Thereafter, at time T3, the latch circuits 3a and 3b are activated.

3C holds y3, y2, and yl, respectively, and xl and x2 are held from delay circuits 2a, 2b, and 2c, respectively.
The arithmetic circuit 4a outputs °x3 and performs the same calculation as above.

4b, 4c. Multiplication is performed in this manner.

By the way, according to the configuration in which the time series and column signals (x) and (y) are applied to the signal lines 16 and 16 as described above, all the pits (21 to Z7) of the multiplication 6 page calculation result can be obtained. However, for this purpose, a guard time of 4 pits or more is required from the end of the -th calculation to the start of the next calculation. Therefore, in this case, no improvement in multiplication speed can be expected.

On the other hand, in order to increase the multiplication speed, it is also considered to apply a time-series signal to the signal lines 16 and 16 without providing the guard time as described above by cutting off the lower bits. For example, a method has been proposed in which 24 to z7 of the 2°-27 multiplication results described above are separated. However, this method has the disadvantage that multiplication accuracy cannot be obtained because the lower bits are separated.

The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a multiplication device that can simultaneously increase both multiplication speed and multiplication accuracy. That is,
The present invention aims to provide a multiplication device in which the output of an arithmetic circuit is outputted to two output lines to separate the upper and lower bits of the multiplication result.

FIG. 2 on page 6 is a circuit diagram showing a multiplication device according to an embodiment of the present invention. The figure shows 8 bits for a 4 bit x 4 bit input.
In this figure, the same numbers as in FIG. 1 indicate the same parts, and 10' to 13' correspond to 10 to 13 in FIG. 1.

18a to 18d are signal processing circuits that output either one of the input terminals a and b in response to a control signal C, and 19a to C are signal processing circuits that output one of input terminals a and b.
ND circuit, 20 is a lower bit signal output line. The time series input/output signal (xHy) (c, ) (J, ) (ZH) is the third
Input and output are performed at the timing shown in the diagram.

Here, (zL) and (ZH) are lower and lower output signal sequences of the multiplication results, respectively. The signal processing circuits 18a to 18d output a signal from input terminal a when the control signal C is at a high level (hereinafter abbreviated as H), and output a signal from input terminal A when the control signal C is at a low level (abbreviated as above). .

Next, the operation of this configuration will be briefly explained.

Considering the case where the following multiplications (I) x (y) - (z) and (u) x (v) - (W) are successively performed, this multiplication is expressed as follows.

At time T1, y3 is latched by the latch circuit 3a, and x3 is output from the delay circuit 2a.

Therefore, x3y3 is output from the arithmetic circuit 4a, and "3y
3 is inputted to the input terminal of the signal processing circuit 18a, and outputted to the signal line 2° via the signal processing circuits 18b to 18d.

At this time, the output of the arithmetic circuit 4a is not transmitted to the arithmetic circuit 4b by the AND circuit 19a because the output C3 of the delay circuit 1a is "L".

Next, at time T2, y3 continues to be latched in the latch circuit 3a, and y2 is latched in the latch circuit 3b. At this time, each of the delay circuits 2a and 2b outputs X 2
+Xs is output, and C2 and C3 are output from delay circuits 1a and 1b, respectively. Therefore, x2''3 is output from the arithmetic circuit 4a. Also, in the arithmetic circuit 4b,
x213 and "3"2 are added, the carry is held in the arithmetic circuit 4b, and at the same time the sum is output, and the output signal C3 (P-L) level of the delay circuit 1b causes the input terminal of the signal processing circuit 18b to be input to 18c. ~18d to the signal line 2o.Afterwards, at time T3, the latch circuit 9 and the page paths 3a, 3b, and 3c are connected to the signal line 2o.
yl The power is held from the delay circuits 2a, 2b, and 2c, respectively! 1. X 2 and X 3 are output, C1, C2, and Cs are output from the delay circuits 1a, 1b, and 1c, respectively, and the same calculations as above are performed in the arithmetic circuits 4a, 4b, and 4c, and the inputs of the signal processing circuit 18C are The signal is output to the signal line 20 via the terminal. Similar calculations and signal processing are performed at time T4 as well, and the signal is output to the signal line 2o via the input terminal of the signal processing circuit 18d. In this way, at T1 to T4, the lower four pits 24 to z7 of the multiplication result are output from the signal line 2o.

At time T6, latch circuits 3a to 3b each have y
3 to yo continue to be latched, and the delay circuit 2a-2
cl, 0.0 from 1a-1d, respectively. xo.

X 1 + X 2 and C41'0ICI +'2 are output. Therefore, 0.y3-o is output from the arithmetic circuit 4a, 0 is added to the arithmetic circuit 4b via the AND circuit 19a, and the arithmetic circuit 4b, AND circuit 19b, arithmetic circuit 4c,
Arithmetic and signal processing are performed through the AND circuit 19C9 arithmetic circuit 4d and the AND circuit 19d, and z3107<-ji is output to the signal line 17.

Next, at time T6, y2 to yo are latched in the latch circuits 3b to 3d, and v3 is latched in the latch circuit 3a by the signal C3.

At this time, delay circuits 2a to 2d and 1a to 1j each receive u.
3, 0, 3C□, X 1 and ' 31 C4
1C01CI is output. Therefore, as in the case of time T1, u3V3 is output from the signal line 2o as W7, and the carry stored in the same arithmetic circuit at time T6 is output from the arithmetic circuit 4b to the arithmetic circuit 4C via the AND circuit 19b. and the AND circuit 19C2
Calculation and signal processing are performed through the path of the arithmetic circuit 4d and the AND circuit 19d, and z2 is output to the signal line 1. Thereafter, multiplication is performed in this manner, and at time T9, the output 2o
At the same time, the carry stored in the arithmetic circuit 4d at time T8 is output as 20 to the signal line 17 via the AND circuit 17.

In this way, the signal processing circuits 18a to 18d and the control signal (C) output the sum of the adder circuit to the lower bit 11 and the base signal output line 20, and at the same time, the AND circuit 19
By canceling the propagation to the next element by a to 19d, the entire output can be obtained continuously and independently from the upper and lower bits of the operation result at the timing shown in FIG.

As explained below, according to the present invention, by dividing the output signal of multiplication of two consecutive time-series signals into upper and lower two, all calculation results are added to the input signal as a guard corresponding to the length of the input signal. If time is included, the multiplication can be output rapidly and continuously.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional pipeline multiplication device that inserts a guard time into the input signal to obtain a total multiplication result.
FIG. 2 is a block diagram of a multiplication device according to the present invention, and FIG.
FIG. 3 is a time chart diagram of an input/output signal train having the configuration shown in the figure. 1a to 1d, 2a to 2d... Delay circuit, 3a to
3d...Latch circuit, 4a-4d...
Arithmetic circuit, 17-... Upper bit signal line, 18a
~18d...Signal processing circuit, 2o...
Lower bit signal line.

Claims (1)

[Claims] a plurality of latch circuits to which one time series signal is input; a plurality of delay circuits to which the other time series signal is input; a plurality of multiplier circuits that multiply the outputs of the latch circuits and the delay circuit; A plurality of signal processing circuits connected to each of the circuits and a control circuit for controlling the signal processing circuits are provided, the lower bits of the multiplication result are obtained from the signal processing circuit, and the upper bits of the multiplication result are obtained from the multiplication circuit. A multiplication device characterized by begging.