JPH03271931A - Multi-input adding circuit - Google Patents

Abstract

PURPOSE:To realize the quickness as well as the easiness of layout by constituting plural addition stages of one-bit full adders, four-input Wallace tree circuits, and six-input Wallace tree circuits. CONSTITUTION:Plural addition stages consists of one-bit full adders, four-input Wallace tree circuits, and six-input Wallace tree circuits. When the number of inputs to an adding circuit is '15', these 15 inputs are received by five on-bit full adders 14 to 18 of the high order addition stage, and 10 outputs from high order addition stages are received by six-input and four-input Wallace tree circuits 19 and 20 in respective middle-order addition stages, and the last outputs are received by one four-input Wallace tree circuit 21 of the low order addition stage. Thus, one-bit full adders and four-input and six-input Wallace tree circuits are only properly combined to cope with any number of inputs of the practical multiplication scale, and the quickness as well as the easiness of layout are realized.

Description

[Detailed Description of the Invention] [Summary] In particular, regarding a multi-input adder circuit applied to partial product addition of a digital parallel multiplier, the present invention aims to achieve both high speed and ease of layout, and uses multiple adder stages. It consists of a 1-bit full adder, a 4-input Wallace tree circuit, and a 6-input Wallace tree circuit.

[Industrial application field]

The present invention relates to a multi-input adder/adder circuit, and particularly to a multi-input adder circuit applied to partial product addition of a digital parallel multiplier.

In general, a parallel multiplier with a practical multiplication scale of 8 x 8 bits or more uses the carry save method (hereinafter referred to as C
5A method) and Wallestry one-way method are adopted.

The C3A method inputs a carry signal to an adder one digit above the other and processes it one bit at a time, which is similar to manual calculation, and although it has some drawbacks in terms of multiplication speed, it has the advantage of being easy to layout. . On the other hand, in the Wallestry one-way system, a 3-bit input signal is input to one adder (full adder), and the sum signal is input to the next stage full adder of the relevant digit.
The carry output is input to and added to the next-stage full adder located one digit higher than the other, and while it has the advantage of fast multiplication speed, it has the disadvantage that the circuit lacks regularity and is difficult to design.

[Conventional technology]

FIG. 13 is a diagram showing an example of a multiplier (C3A method) based on the conventional modified 13ooth algorithm. In this example, all partial products (P
po to PP, ) are added together in an adding section (b).

The partial product generation unit (a) consists of a block (PPi generator) that generates 0, ±X, ±2X, and a block (Y decoder) that generates a signal to select one of these as a partial product. , the adder (b) consists of an array configuration of adders.

According to this configuration, the partial product generation section (a) and the addition section (b)
Although this method is advantageous in that it can be designed separately and further subdivided into functional blocks, it is disadvantageous in that it cannot deal with the problem of an increase in the number of interconnections between blocks due to an increase in the number of multiplication bits.

Based on this point, Japanese Patent Application Laid-Open No. 105732/1983 discloses a technique in which one bit of a partial product generator and one full adder are combined to form a basic cell, and this basic cell and a Y decoder are used. is disclosed. FIG. 14 is a block diagram thereof, showing an 8×8 bit multiplier. 20 to 67 are basic cells, 68 to 71 are Y decoders, and the first stage Y decoder 68 and basic cells 20 to 28 generate a partial product PP, and the second stage Y decoder 69 and basic cells 35 to At step 43, a partial product PP is generated, and the partial products P P o are added together. In addition, the third stage Y decoder 70 and the basic cell 48
~56 to generate the partial product P P t and PPz and (pp
Similarly, the fourth stage Y decoder 71 and basic cells 59 to 67 generate a partial product PP and add (Ppo + PPI + ppz). FIG. 15 is a block diagram of one basic cell of FIG. 14.

According to this prior art, two basic cells and a Y decoder
A multiplier based on the modified Booth algorithm can be realized using only the different types of cells, and the inter-cell wiring can be provided with considerable regularity. Therefore, if a repeating unit of wiring is included in a cell, cell placement and intercell wiring can be simultaneously realized just by the cell layout, improving design ease.

FIG. 16 shows another example disclosed in the above publication, in which the basic cell 10
By making the connections 4 to 139 carry-save connections to increase speed, and by adding inverters to some of the cells, cells for code propagation are no longer required, achieving compactness. Note that FIG. 17 shows one block of the basic cell in FIG. 16.

18 is a block diagram of a basic cell common to FIGS. 14 and 16, and FIG. 19 is a block diagram of a Y decoder common to FIGS. 14 and 16.

[Problem to be solved by the invention]

However, in the former disclosed example (configuration example shown in FIG. 14) described in the above publication, the ripple carry one-type (59-
67 connection method), it has the drawback that it takes a long time to determine the product output signal. In addition, in the latter disclosed example (configuration example shown in FIG. 16), a carry select adder (Carry 5 select Adder) and a look-ahead carry adder (Carry Lookahea-d
Although the speed can be improved more than the former by using Adder), the number of signal transmission stages up to the CPA (adder) 144 is up to 4, and from the perspective of achieving even higher speed. It was inadequate.

Note that, as described above, if the multiplier is implemented in the Wallace tree configuration, the number of stages through which the adder passes can be reduced. For example, the second
In order to realize the calculation shown in FIG. 0, the maximum number of inputs to the Wallestry is "5", and it is sufficient to use the power of 5 of the 6-person Wallestry circuit (hereinafter referred to as 6W). As will be described in detail later, 6W is realized by combining two 1-bit full adders in the upper stage, one in the middle stage, and one in the lower stage. Therefore, the number of passing stages can be set to three, and the speed can be increased by one stage.

However, the Wallace tree configuration has the problem that there is no regularity in the layout, making it extremely difficult to design, especially when designing a multiplier that handles multi-bit data with a practical multiplication scale of 8 x 8 bits or more. The above-mentioned problems have a large impact on Figure 21 shows “1” for reference.
This is an example of a 8" input cute dolly circuit, in which the wiring between many 1-bit full adders and the wiring from other digits are irregularly laid out.

The present invention was made in view of these problems, and
The purpose is to achieve both high speed and ease of layout.

[Means to solve the problem]

The above object can be achieved by configuring the plurality of addition stages with a 1-bit full adder, a 4-input Wollestry circuit, and a 6-input Wollestry circuit.

[Effect]

For example, if the number of inputs to the adder circuit is "15", first,
These 15 human inputs are received by five (15 total 3 = 5) 1-bit full adders in the upper adder stage, and then the 1-bit full adders from the upper adder stage are
The 0 outputs (5 x 2 =10) are received by the 6-power and 4-input wallet trees, one each in the middle adder stage, and finally in the one 4-input wallet tree in the lower adder stage.

It is possible to handle any number of inputs on a practical multiplication scale simply by appropriately combining the 1-bit full adder, 4-man power, and 6-man power Wallacetry circuits.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 12 are diagrams showing an embodiment of a multi-input adder circuit according to the present invention.

First, the configuration of the "15" input adder circuit will be explained according to FIG. 1. This adder circuit IO has three adder stages 11 to 1.
3, and the upper adder stage 11 is composed of ``1'' from h to IIS.
5", five 1-bit full adders (hereinafter referred to as 3W) 14 to 18 each receiving 3 bits of input are provided.

The configuration of 3W is shown in FIGS. 2(a) and 2(b). Figure 2 (
A) is a block diagram thereof, and FIG. 6(b) is a circuit diagram thereof. A 1-bit full adder has a 3-bit input of the same digit (for example, I
+, z, Is), and ■ sum signal S (Sum) of the relevant digit and carry signal C0 (
Carry) is output.

The intermediate adder stages 12 each include one 6-input Wallacetree circuit 1.
9 (hereinafter referred to as 6W) and a 4-input Wallestry circuit 20 (
The lower addition stage 13 is composed of one 4W (21).

4W consists of two 1-bit full adders (3
Wx2), and 6W consists of four 1s as shown in Figure 4.
Consists of a bit full adder (3Wx4).

In addition, CI, ~C1, and □ in Figure 1 are carry signals from each addition stage for lower digits, GOI -coax is a carry signal to upper digits for each addition stage, and CO is a carry signal for the relevant digit. The signal S is the sum signal of the relevant digits.

In such a configuration, the upper adder stage 11 includes 11 to 11 . First, S1 to S from each 1-bit full adder 14 to 18 are transmitted to the intermediate adder stage 12 along with C1l to CL, and then 516s Sll from the intermediate adder stage 12
is CI+o~CIl! 4 W of the lower adder stage 13
(21), the CO and S of the relevant digit are output from the lower addition stage 13. That is, addition processing of the "15" input is performed using the Wallace tree configuration.

Now, focusing on the left half of FIG. 1, the three 1-bit full adders 14, 15, and 16 form a "9" input adding circuit together with one 6W (19). Figure 5 shows this part extracted.If this "9" input adder circuit (hereinafter referred to as 9W) is used as a basic cell, it can be applied to multi-input adder circuits with various numbers of inputs6. As shown,
An "18" input adder circuit can be realized by combining two 9Ws and one 4W. The number of stages through which the l-bit full adder in the "18" input adder circuit in FIG.
It has the same number of stages as the conventional Wallace tree configuration shown in Figure 1.

Therefore, it is possible to provide regularity to the arrangement of basic cells while ensuring high-speed operation of the Wallace tree configuration, and it is possible to improve the ease of layout.

FIG. 7 shows two examples of a "27" input adder circuit.

One example shown in the same figure (a) is three 9Ws and two 4Ws.
It has excellent regularity including wiring between blocks, and is preferable when layout is important. On the other hand, another example shown in the same figure (b) is composed of three 9Ws and one 6W. This allows the number of stages to pass to be reduced by one stage compared to the one shown in FIG.

As described above, according to each of the above embodiments, a 1-bit full adder (3W), a 4-input Wallace tree circuit (4W)
By simply combining the 6-input Wallestry circuit (6W), a multi-input adder circuit with various numbers of inputs can be realized, and the ease of layout can be improved while ensuring the high speed of the Wallestry configuration.

Next, considering applying the above idea to a multiplier,
For example, "18" input partial product generation/addition circuit (hereinafter referred to as 1
8D) can be realized by a combination of two "9" input partial product generation/addition circuits (hereinafter referred to as 9D) and one 4W, as shown in FIG. 8(b).

In addition, "9" input partial product generation/addition circuit (hereinafter referred to as 9D)
can be realized by a combination of three "3" input partial product generation/addition circuits (hereinafter referred to as 3D) and one 6W circuit, as shown in FIG. That is, 9D has three basic cells (3
D) and one 6W. FIG. 9 is a 3D block diagram, and FIG. 10 is a specific example thereof. 3D can be realized with three partial product generating circuits (hereinafter referred to as P) and one 1-bit full adder. Note that FIGS. 11(a) and 11(b) are a block diagram and a circuit diagram of the partial product generation circuit.

FIG. 12 shows two examples of the "27" input partial product generation/addition circuit. One example shown in FIG. 3A is composed of three 9Ds and two 4Ws, and has excellent regularity including wiring between blocks, and is preferable when layout is important.

On the other hand, another example shown in the same figure (b) is three 9D and one
The number of passing stages is as shown in the figure (a).
It can be done in one step less than the conventional method, and is preferable when speed of operation is important.

〔Effect of the invention〕

According to the present invention, the plurality of adder stages are comprised of a 1-bit full adder (3W), a 4-input Wallestry circuit (4W), and a 6-bit full adder (3W),
Since it is configured with an input Wallestry circuit (6W), the circuit can be configured with regularity while taking advantage of the features of the Wallestry circuit, and it is possible to achieve both high speed and ease of layout.

[Brief explanation of drawings]

1 to 12 are diagrams showing an embodiment of the multi-input adder circuit according to the present invention. FIG. 1 is a block diagram of the 15-manual adder circuit, and FIG. 2 is a block diagram of the 1-bit full adder. , Fig. 3 is a block diagram of the 4-input Wallestry circuit, Fig. 4 is a block diagram of the 6-input Wallestry circuit, and Fig. 5 is a block diagram of the 9-input adder circuit.
Figure 6 is a configuration diagram of the 18 human-powered addition circuit, Figure 7 is a configuration diagram of the 27-person addition circuit, Figure 8 is a configuration diagram of the multi-input partial product generation/addition circuit, and Figure 9 is the partial product A configuration diagram of the basic cell that performs generation and 1-bit full addition. Figure 1O is a configuration diagram of the basic cell in Figure 9. Figure 11 is a configuration diagram of its partial product generation circuit. Figure 12 is the 27 manual partial products. FIG. 2 is a configuration diagram of a generation/addition circuit. 13 to 21 are diagrams showing conventional examples. FIG. 13 is a configuration diagram of a conventional parallel multiplier circuit based on the modified Booth algorithm, and FIG. 14 is a diagram of the conventional PPi generator and adder array. Configuration diagram, Figure 15 is a diagram showing one of the basic cells in Figure 14, Figure 16 is a diagram showing one of the basic cells in Figure 14.
Figure 17 is a block diagram of another conventional PPi generator and adder array; Figure 17 is a diagram showing one of the basic cells in Figure 16;
FIG. 19 is a configuration diagram of a basic cell of the conventional example, FIG. 19 is a configuration diagram of a Y decoder of the conventional example, and FIG. 20 is a diagram showing the number of inputs to the multi-input adder circuit of each digit according to the one-way wallet system. FIG. 21 is a block diagram of the 18-input Wallace tree circuit. 11-13... Addition stage, 14-18... 1-bit full adder (3W), 2
0.21...4 input Wallace tree circuit (4W)
, 19... 6-input Wallestry circuit (6W). l3 12 If Fig. 4 Block diagram of input Wallace tree circuit Fig. 6 Block diagram of input Wallace tree circuit Fig. 1112I3 Fig. 1+I2b 9 (a) Block diagram of nail input addition circuit (b) 111shiIi Multi-input partial product Figure 1 Block diagram of the basic cell that performs partial product generation and 1-bit full addition Figure 1 Block diagram of the basic cell shown in Figure 9 Figure 0 Figure 13 Figure 13 (b) φ addition circuit Fig. 2 A block diagram of the basic cell of the conventional example Fig. 18 A block diagram of the Y decoder of the conventional example Fig. 19

Claims (1)

[Claims] A multi-input adder circuit characterized in that the plurality of adder stages are composed of a 1-bit full adder, a 4-input Wollestry circuit, and a 6-input Wollestry circuit.