JPS62254525A - Galois field multiplication circuit - Google Patents

Abstract

PURPOSE:To attain the multiplication of an optional element at a high speed by applying the expression of polynomial to the multiplication of elements of a Galois field and converting a term of overflow into a loworder digit and adding the result to each digit. CONSTITUTION:The titled circuit consists of the 1st register 10 set with a multiplier alpha<i>, the 2nd register 12 set with a multiplicand alpha<j>, and a gate group applying polynomial expression to the multiplier alpha<i> and the multiplicand alpha<j>, multiplying them in the form of polynomial, arranging terms of overflow to low-order corresponding digits and outputting each term as the result of multiplication obtained in this way, operation circuits 27, 26 for each term (X<7>, X<6>-X<0>) as the result of multiplication receiving the data of each digit of the multipliers and the multilicands of the 1st and 2nd registers and the 3rd register 14 having each digit location set with the outputs of the operation circuits and outputting the result of multiplication Thus, the result of multiplication is obtained by having only to input each digit of the multipliers and multiplicands to the corresponding operation circuit and the very high speed multiplication is attained.

Description

[Detailed Description of the Invention] [Summary] Multiplication of elements in a Galois field is performed using polynomial expression, and by converting overflow terms to lower digits and adding them to each digit, multiplication of arbitrary elements can be performed at high speed. circuit to perform.

[Industrial application field]

The present invention relates to a multiplication circuit for Galois field elements of error correction codes used in digital communication, digital signal processing, etc., and enables high-speed multiplication to speed up signal processing, thereby increasing performance and multiplicity. This is an attempt to make 1131 more efficient.

[Conventional technology]

For example, the element of the Galois field CF (2') is α (ooo in primitive light
It has the form of a power of α0~α
It is a cyclic code that goes around once at 254 and becomes α255=α0. The ROM method is often used for multiplication of numbers (elements). That is, with αl as the multiplier and αj as the multiplicand, first use a logarithmic conversion ROM in which the element is the address and the exponent is the stored data, read out the ROM using the elements αi and αj, and convert the exponents j and j to (q, i by the adder circuit). Finally, an inverse logarithm (exponential) conversion ROM with the exponent as the address and the element as the stored data is used, and the ROM is read out with the index i + j to obtain the element αi + j. Fig. 4 shows the diagram of this ROM system. A block diagram of the multiplication device and a calculation flowchart are shown in FIG.

[Problem that the invention seeks to solve]

In this conventional method, α'', αj are taken in, and the logarithmic transformation R
One multiplication requires about 10 steps of data manipulation, such as accessing the OM, performing the i+j operation, and accessing the anti-logarithm conversion ROM, making it unsuitable for high-speed multiplication of a large number of elements. be.

By building hardware (arithmetic circuits) to enable direct multiplication, calculations can be made faster. Furthermore, if the elements of the Galois field are treated as polynomials, the form of the calculation formula for multiplication can be easily generalized, and due to cyclicity, it can be simplified all at once. When the elements of the Galois field are treated as vector representations, the powers of α appear seemingly randomly (although since it is a Galois field, the calculation results are within the range of elements), making it difficult to generalize the form of the calculation formula. . The present invention focuses on this point,
The objective is to provide an arithmetic circuit that can perform multiplication of Galois field elements at high speed.

[Means for solving problems]

Taking the element of CF(2) as an example of the Galois field element, Part 2
Consider multiplication of two elements α′ and αj. αlαj is represented by equation (1) in vector representation, and equation (2) in polynomial representation.

Here, x=α, a, and b are O or 1.

Next, using polynomial expression, let's calculate δ by the product of α3 and αko. In the calculation formula below, + is addition modulo 2 (Exc
Represents lusive O.

αi. αj sea 7b? K” + (a7bv+avb7)xl3 + (a-, bz+abbb+astz)x12+ (
a7b++abbs+asb6+aat++)x”+
(a7bx+aaba+a5bs+a4b6+a3bt
)x”+ (aib2+aSb3+aSba+a4b5
+a3b6+a2b7)X'+ (a tb !+a
Cb2+a 5 b3+a a ba+a 3b5+a
2bt+a l bt)X8+ (atbo+a t
b 1+a5b2+a a bz+a 3ba +a
2b5+a l ba+a obt)x'+ (acb
a+a5b1+a4b=+a:+b3+a2ba+a+
t+s+a*b6)x'+ (asbn+aaffi+
asb2+a2bp+a+ ba+aobs)x'+
(aabo+a:+b++a2b2+a+b3+aob
a) x'+ (a:+ba+a2b++a+b2+aa
b3)x3+ (a2bo+a+b++aob2)x”
+ (a 1 bo+aob+)x la ob.

・・・・・・(3) It becomes. Here, the primitive polynomial (Primi
tive1'olync*ial) g(X)=x' +x4 +x3 +z2+1=0
li, x −x +x +x +l
・・・・・・
・A4) x9ji[Xa=x'+x'+X'' +X
・Strike (5)x10=x -x' =X6
+X' +X4 +X2
・Slap A 6) x"=x -x"=x7 +x'
+x'+x" 0.
”, ia)x −x−x ””x +X +X
+X=J'+X3+X2+ 1 +x7+x'+?
=x7+ ×6 +xJ +x2+ l
・Slap A8) xl3 = x,
xl 2 =x8+x'+x'+x3+x=X7+X2
+ X + 1 ,,,,,be9)
z+X+1・・・・・・
Therefore, by substituting these (overflow terms) into equation (3) and arranging them (combining terms of the same power of X), we get cx'-a'= (at(bo+bt+b5+bs)
+as (bl+b5+b6+bt) +as (b2
+b6+bt) +a4 (b3+bt) +a3ba
+a2bs+a+bt++aob7) x7 + (at(b3+ba+b5) +as (bo+b
t+b5+bb) +a5(b++bs+bs+bt)
+aa (b2+bs+bt) +a 3 (bx+
bt) +a 2ba+a+ba+aobs) x
'+ (at (b2+b3+bn) +aa (b3
+ba+b5) +as (bo+b4+ba+ba)
+84 (tz+bs+b6+bt)+a3(b2+b
6+bt) +a2(bx+bt) +a+ba+ao
ba)x'+ (at(tz+b2+bz+bt)+
as (b2+b3+ba) +a5(b3+ba+b
5) +a4 (bo+b4+b5+bs) +a3(
b++b5+ba+b7)+a2(b2 ten ba+bt)
+a+ (b3+bt) +aoba) x'+(at
(b++b2+ba+bs) +aa (b2+b
3+bs+ba)+a5 (bx+ba+bs+bt)
+aa (ba+b5+bt)+a3 (ba+b5+
b6)+a2 (b++ba+bt)+al (b2
+bt)+aab3)x” + (at (b++bx+ba+b6)+ab (b
2+b4+b6+tz)+as (bx+ba+bt
)+3m (ba+bs)+23 (b5+b7)+a
2(ba+bb)+3. (b++bt)+aub2)
x2+ (at(b2+b6+b7)+86 (b3+
bt)+a5ba+aab5+a:+bs+a2bt+
a+bo+aob+) x+a7(b++b, +b6+
bt)+86 (b2+b6+b7)+a5(b3+b
7)+aaba+a3b5+a2ha+a+bt+ao
b.

・・・・・・Ishun is obtained.

x in this equation (11)? , x6. ...--Prepare an arithmetic circuit for each term, and each circuit calculates αi. By calculating the value of each term from αj, the product αi+j can be immediately obtained.

The source of the Galois field is CF(2)1. The same goes for the case where m is an element of - and m is an arbitrary integer.It is expressed as a polynomial, the terms with overflow are obsolete by the corresponding lower digits, an expression equivalent to equation (11) is obtained, and then the arithmetic circuit All you have to do is configure.

[Effect]

In this way, the multiplication result can be obtained simply by inputting each digit of the multiplier and the multiplicand to the corresponding arithmetic circuit, and extremely high-speed multiplication becomes possible.

〔Example〕

FIG. 1 shows an original multiplication circuit for 0F(2), and FIG. 3 shows a multiplication circuit for a part of the x7 term.

In Fig. 1, 10.12 is a register in which the binary data of each digit of the multiplier αi and the multiplicand αj is set, 27°26,...
. . . 20 is an arithmetic circuit for the term x71 X′ l . According to equation (11), the term x7 is at (bo+b4+b5+bs)+aa(b++b
5+ba+bt) +-...+a (1b7, so if it is constructed as shown in FIG. 3, the term x7 can be calculated.

In FIG. 3, 31 to 34 are exclusive OR gates, and gate 31 receives inputs bg, ba, bs, and ba, and b o
+b a +b 5+b s is output (addition of Galois field elements is treated as exclusive OR logic). Also, the gate 32 is b
+, bs, b6. b7 is input, b 1 +bs+b
Output s+bt. The following shall apply accordingly. 41 to 48 are ant game 1, gate 41 is at and gate 31
The output of is input, and at(bo+ba+bs+bb) is output. 42゜43, . . . also follow this, and therefore, from the exclusive OR gate 51, The term is output.

x' in equation (11), x5. Regarding the terms .

In the present invention, as shown in FIG. 2, a Galois field multiplication circuit 62 as shown in FIG. 62 registers 10.
It is only necessary to set the value to 12 and take in the multiplication result of the register 14, and by repeating this, a large number of multiplications can be executed at high speed.

〔Effect of the invention〕

As explained above, according to the present invention, direct multiplication is performed without first converting the elements into logarithmic representation as in the ROM method, so that 1) high-speed multiplication is possible; 2) therefore, digital communication, digital signal processing, etc. The following effects can be obtained: (1) The number of program steps is reduced, making it possible to handle complex calculations and increase the functionality of the system. The present invention is effective when applied to equipment requiring Galois rest arithmetic, such as DAT (digital audio tape), CD (compact disc), digital communication systems, and equipment using Reed-Solomon codes.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing the overall configuration, Fig. 3 is a circuit diagram showing some details of Fig. 1, and Fig. 4 is a conventional example. The block diagram shown in FIG. 5 is a flowchart showing the operation procedure. In FIG. 1, 10 is a first register, 12 is a second register, 27, 26 . ...20 is an arithmetic circuit for each term,
14 is a third register. Figure 4 Figure 5

Claims (1)

[Claims] A first register (10) to which a multiplier α^i is set; a second register (12) to which a multiplicand α^j is set; a multiplier α^i and a multiplicand α^j It has a group of gates that express polynomials, multiply them in the form of the polynomials, combine overflow terms into corresponding lower digits, and output each term of the multiplication results obtained in this way, and the first and second registers Each term of the multiplication result (x^7, x^
6,...x^0) Separate calculation circuit (27, 26,...
...20), and a third register (14) that has each digit position to which the output of these arithmetic circuits is set and outputs the multiplication result. .