JPS6386620A - Detector for erroneous operation of decoder - Google Patents

Abstract

PURPOSE:To simplify the constitution and to contrive to improve the performance of the titled detector to detect an operational error of a decoder by comparing an N-bit code information that is an input to the decoder and an N-bit code information that is an output of an encoder, and outputting an error detection signal when prescribed agreement is not obtained from the comparison. CONSTITUTION:The output of the decoder is inputted to the encoder circuit 2 of the error detection circuit 4, and the decoder circuit 2 executes the opposite action of that of the decoder circuit 1. Accordingly, as far as the chip actions of the circuits 1 and 2 are normal, the 3-bit code information output of the circuit 2 is identical to the 3-bit code information input of the circuit 1. A data comparison circuit 3 compares these 3-bit code information input and 3-bit code information output, and outputs an error signal to its output terminal 0 in case of disagreement is obtained. In such a way, the titled detector can be constituted with less circuit elements, and can be made effectively detect many kinds of operational errors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an operation error detection device for a decoder that forms 2N exclusive outputs in one-to-one correspondence with N-bit code information.

[Prior Art] The operation of a decoder to form 2N exclusive output states in one-to-one correspondence with N-bit code information is a fundamental and important logical operation, and is used not only in decoder logic circuits but also in other fields. It is also widely adopted. Therefore, if the decoder makes a mistake in its operation, it will have a serious impact on the system.

FIG. 2 is a diagram showing a production error detection circuit of a conventional decoder circuit. In the figure, 1 is a typical decoder circuit, which manually inputs 3-bit code information, and its output terminals O to 7 have 23 exclusive output states (which are h ) Only one output forms a logic "1° state". Reference numeral 5 denotes a parity checker circuit, which constitutes an operation error detection circuit 6 of the decoder circuit 1.

That is, when the decoder circuit 1 malfunctions and an even number of logic "1" states are formed at its output, an operational error can be detected.

However, since the detection circuit 6 only performs an odd-even test on the decoder output, if other malfunctions occur, for example, when logic "1" states are formed on three output lines at the same time, or when a logic "1" state is formed on the original decode output line, ” is not output and instead a logic “1” is sent to the other output lines.
If this is the case, an operational error could not be found. For this reason, there is a method in which the same decoder circuit 1 is provided twice and the operation error is detected by checking whether the outputs of both decoder circuits match or do not match, but in this method, the number of elements in the decoder circuit and comparison circuit The disadvantage was that it increased.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned drawbacks of the prior art, and its purpose is to achieve a configuration with fewer elements and to improve the decoder's ability to detect operational errors. An object of the present invention is to provide a decoder operation error detection device that is further improved.

[Means for Solving the Problems] In order to achieve the above object, the decoder operation error detection device of the present invention includes an encoder that forms N-bit code information in one-to-one correspondence with each output of the decoder, and a decoder input. N of
Comparing means is provided which compares the bit code information and the N-bit code information output from the encoder and outputs error detection No. 12 when a predetermined match is not obtained.

[Operation] In such a configuration, the decoder forms any one of 2N corresponding exclusive outputs in response to an input of N-bit code information. The encoder forms corresponding N-bit code information in response to the exclusive output of the decoder. The comparing means compares the N-bit code information input to the decoder and the N-bit code information output from the encoder, and when a predetermined match is not obtained, outputs No. 8 for error detection.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing an operation error detection circuit of a decoder according to an actual example. In the figure, 1 is a decoder circuit which inputs, for example, a 3-bit code 1 report and sets any one of the corresponding 23 decode outputs to the logic "1" state, and 2 is a decoder circuit that outputs one of the 23 decode outputs. Any one of the logic “1”
3 is a data comparison circuit that compares the match/mismatch between the 3-bit code information output of the decoder circuit 1 and the encoder circuit 203 bit code information output. The decoder operation error detection circuit according to this embodiment is composed of an encoder circuit 2 and a data comparison circuit 3.

In this configuration, 3-bit code information is manually input to the decoder circuit 1 and the data comparison circuit 3. The 3-bit code information inputted to the decoder circuit 1 is decoded and outputted as a logic "1" level signal to any one of the output terminals 0-7.

As shown in the figure, the necessary decoding outputs are extracted to the outside and used in other logic circuits (not shown).

On the other hand, the decoded output is input to the encoder circuit 2 of the error detection circuit 4. Encoder circuit 2 is decoder circuit 1
It is designed to perform exactly the opposite operation. Therefore, as long as the chip operations of decoder circuit 1 and encoder circuit 2 are normal, the 3-bit code information output of encoder circuit 2 should be the same as the 3-bit code information input of decoder circuit 1. Therefore, the data comparison circuit 3 compares the 3-bit code information input and the 3-bit code information output, and outputs an error signal to its output terminal 0 if a mismatch is detected.

In this way, the error detection circuit 4 of the present embodiment not only detects when a logic "1" state is formed on two decode output lines simultaneously, but also when there are three or more, or when a logic "1" state is formed on the original decode output line. Even if a logic "1" is not outputted and instead a logic "1" is outputted to another output line, an operational error in the decoder can be reliably discovered.

Incidentally, in the above embodiment, decoding of 3-bit code information was explained, but the present invention is not limited to 3-bit code information.
The same applies to other arbitrary N bits.

Furthermore, the present invention is not limited to electrical decoder circuits as in the embodiments, but can be easily applied to other types of operation error detection devices, such as mechanical decoders.

[Effects of the Invention] As described above, according to the present invention, a decoder operation error detection device can be configured with fewer elements, and more types of operation errors can be effectively detected.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an operation error detection circuit of a decoder according to an embodiment, and FIG. 2 is a diagram showing an operation error detection circuit of a conventional decoder circuit. In the figure, 1: decoder circuit, 2: encoder circuit, 3: data comparison circuit, 4: error detection circuit. Patent Applicant: Canon Co., Ltd. Representative Patent Attorney: Yasushi Inuzuka Sa: IT”, 7.
Fig. 2

Claims (1)

[Claims] An operation error detection device for a decoder that forms 2^N exclusive outputs in one-to-one correspondence to N-bit code information, comprising: an encoder that forms N-bit code information in one-to-one correspondence to each output of the decoder; Detection of operational errors in a decoder, characterized in that it comprises a comparison means for comparing the N-bit code information input to the decoder and the N-bit code information output from the encoder and outputting an error detection signal when a predetermined match is not obtained. Device.