JPH0378346U - - Google Patents
Info
- Publication number
- JPH0378346U JPH0378346U JP13759789U JP13759789U JPH0378346U JP H0378346 U JPH0378346 U JP H0378346U JP 13759789 U JP13759789 U JP 13759789U JP 13759789 U JP13759789 U JP 13759789U JP H0378346 U JPH0378346 U JP H0378346U
- Authority
- JP
- Japan
- Prior art keywords
- address
- signal
- memory device
- encoder
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の原理ブロツク図、第２図は本
考案の一実施例の構成ブロツク図である。
１…メモリ素子部、２…アドレスデコーダ、３
…アドレスエンコーダ、４…アドレスエラー検出
部、５…アドレスバツフアレジスタ。
FIG. 1 is a block diagram of the principle of the present invention, and FIG. 2 is a block diagram of the configuration of an embodiment of the present invention. 1...Memory element section, 2...Address decoder, 3
...address encoder, 4...address error detection unit, 5...address buffer register.
Claims (1)
装置であつて、 アドレス信号を受け、これをデコードしてメモ
リ素子に与えるアドレスデコーダと、 アドレスデコードされた選択信号を入力し、こ
れをエンコードするアドレスエンコーダと、 アドレスエンコーダからのエンコード出力と入
力アドレスと比較し、比較結果に応じてアドレス
エラー信号を出力するアドレスエラー検出部とを
設け、 前記アドレスエコーダとアドレスエラー検出部
は、エンコードしたデータと入力アドレスとが不
一致の場合、あるいは、正常時単一の選択信号の
みアクテイブであるところ複数の選択信号がアク
テイブであつた時に、読みだしデータと同時にア
ドレスエラー信号をアクテイブにすることを特徴
とするメモリ装置。[Claims for Utility Model Registration] A memory device using memory elements with multiple bit widths, comprising an address decoder that receives an address signal, decodes it, and provides it to the memory element, and inputs an address decoded selection signal. and an address encoder that encodes this, and an address error detection section that compares the encoded output from the address encoder with the input address and outputs an address error signal according to the comparison result. When the encoded data and the input address do not match, or when multiple selection signals are active while only a single selection signal is active during normal operation, the address error signal is activated at the same time as the read data. A memory device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13759789U JPH0378346U (en) | 1989-11-28 | 1989-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13759789U JPH0378346U (en) | 1989-11-28 | 1989-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0378346U true JPH0378346U (en) | 1991-08-08 |
Family
ID=31684748
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13759789U Pending JPH0378346U (en) | 1989-11-28 | 1989-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0378346U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180134742A (en) * | 2017-06-09 | 2018-12-19 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Method of detecting address decoding error and address decoding error detection system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60224199A (en) * | 1984-04-20 | 1985-11-08 | Fujitsu Ltd | Semiconductor storage device |
| JPS6386620A (en) * | 1986-09-30 | 1988-04-18 | Canon Inc | Detector for erroneous operation of decoder |
| JPS63132342A (en) * | 1986-11-25 | 1988-06-04 | Hitachi Ltd | Fault detection circuit |
-
1989
- 1989-11-28 JP JP13759789U patent/JPH0378346U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60224199A (en) * | 1984-04-20 | 1985-11-08 | Fujitsu Ltd | Semiconductor storage device |
| JPS6386620A (en) * | 1986-09-30 | 1988-04-18 | Canon Inc | Detector for erroneous operation of decoder |
| JPS63132342A (en) * | 1986-11-25 | 1988-06-04 | Hitachi Ltd | Fault detection circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20180134742A (en) * | 2017-06-09 | 2018-12-19 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Method of detecting address decoding error and address decoding error detection system |
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