JPS57172481A - Video buffer circuit - Google Patents

Video buffer circuit

Info

Publication number
JPS57172481A
JPS57172481A JP56057558A JP5755881A JPS57172481A JP S57172481 A JPS57172481 A JP S57172481A JP 56057558 A JP56057558 A JP 56057558A JP 5755881 A JP5755881 A JP 5755881A JP S57172481 A JPS57172481 A JP S57172481A
Authority
JP
Japan
Prior art keywords
memory
chip
counters
accordance
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56057558A
Other languages
Japanese (ja)
Other versions
JPH0135383B2 (en
Inventor
Hidenori Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56057558A priority Critical patent/JPS57172481A/en
Publication of JPS57172481A publication Critical patent/JPS57172481A/en
Publication of JPH0135383B2 publication Critical patent/JPH0135383B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/10—Image acquisition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Image Input (AREA)
  • Facsimile Scanning Arrangements (AREA)
  • Character Input (AREA)

Abstract

PURPOSE:To ensure the highly efficient use of a buffer memory in accordance with the slip size and to increase the reading speed, by adding the hardware such as a control circuit, the address counters of X and Y directions, etc. CONSTITUTION:The video information given from a line sensor 11 is supplied to a video buffer memory 12 having plural memory chips. Boh X and Y direction address counters 13 and 16 are provided to the memory 12. The chip addresses of the memory 12 are applied to the counters 13 and 16 in accordance with the slip size, and at the same time the array conversion control information is applied to a status register 15 from a control part 19. The addresses on the memory 12 are decided by converting circuits 14 and 17 with the chip addresses given from the counters 13 and 16 plus the area status signal given from the register 15. Then the chip address signal is decoded by a decoder 18 to deliver the signal to select the chip within a memory 18. Thus the memory 18 is used in a highly efficient way in accordance with the slip size.
JP56057558A 1981-04-16 1981-04-16 Video buffer circuit Granted JPS57172481A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56057558A JPS57172481A (en) 1981-04-16 1981-04-16 Video buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56057558A JPS57172481A (en) 1981-04-16 1981-04-16 Video buffer circuit

Publications (2)

Publication Number Publication Date
JPS57172481A true JPS57172481A (en) 1982-10-23
JPH0135383B2 JPH0135383B2 (en) 1989-07-25

Family

ID=13059143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56057558A Granted JPS57172481A (en) 1981-04-16 1981-04-16 Video buffer circuit

Country Status (1)

Country Link
JP (1) JPS57172481A (en)

Also Published As

Publication number Publication date
JPH0135383B2 (en) 1989-07-25

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