JPS57167197A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS57167197A JPS57167197A JP56052224A JP5222481A JPS57167197A JP S57167197 A JPS57167197 A JP S57167197A JP 56052224 A JP56052224 A JP 56052224A JP 5222481 A JP5222481 A JP 5222481A JP S57167197 A JPS57167197 A JP S57167197A
- Authority
- JP
- Japan
- Prior art keywords
- noise
- trq12
- memory circuit
- bus lines
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Abstract
PURPOSE:To obtain a memory circuit which is not affected with noise causing erroneous motion, by using an MOSFET highly effectively. CONSTITUTION:A ratio circuit comprises transistors TRQ13 and Q14, and a TRQ12 is arranged between bus lines. The signal phiB which obtains an external driving signal through a buffer 10 and a delay circuit 11 is applied to the gate of the TRQ12. As a result, the potentials of data bus lines RB and RB' are reduced to a level lower than the potential of power supply. Thus the effect of noise is eliminated since the noise only affects the ratio circuit although the noise is caused in the lines RB and RB'.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56052224A JPS57167197A (en) | 1981-04-07 | 1981-04-07 | Memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56052224A JPS57167197A (en) | 1981-04-07 | 1981-04-07 | Memory circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57167197A true JPS57167197A (en) | 1982-10-14 |
JPS6218991B2 JPS6218991B2 (en) | 1987-04-25 |
Family
ID=12908767
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56052224A Granted JPS57167197A (en) | 1981-04-07 | 1981-04-07 | Memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57167197A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63183680A (en) * | 1987-01-26 | 1988-07-29 | Hitachi Ltd | Semiconductor storage device |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5467727A (en) * | 1977-10-31 | 1979-05-31 | Ibm | Ros memory circuit |
JPS5570993A (en) * | 1978-11-24 | 1980-05-28 | Hitachi Ltd | Memory circuit |
JPS55160387A (en) * | 1979-05-31 | 1980-12-13 | Toshiba Corp | Semiconductor memory |
JPS5693175A (en) * | 1979-12-25 | 1981-07-28 | Fujitsu Ltd | Semiconductor memory device |
-
1981
- 1981-04-07 JP JP56052224A patent/JPS57167197A/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5467727A (en) * | 1977-10-31 | 1979-05-31 | Ibm | Ros memory circuit |
JPS5570993A (en) * | 1978-11-24 | 1980-05-28 | Hitachi Ltd | Memory circuit |
JPS55160387A (en) * | 1979-05-31 | 1980-12-13 | Toshiba Corp | Semiconductor memory |
JPS5693175A (en) * | 1979-12-25 | 1981-07-28 | Fujitsu Ltd | Semiconductor memory device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63183680A (en) * | 1987-01-26 | 1988-07-29 | Hitachi Ltd | Semiconductor storage device |
Also Published As
Publication number | Publication date |
---|---|
JPS6218991B2 (en) | 1987-04-25 |
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