JPS57193125A - Ternary buffer circuit - Google Patents

Ternary buffer circuit

Info

Publication number
JPS57193125A
JPS57193125A JP56078055A JP7805581A JPS57193125A JP S57193125 A JPS57193125 A JP S57193125A JP 56078055 A JP56078055 A JP 56078055A JP 7805581 A JP7805581 A JP 7805581A JP S57193125 A JPS57193125 A JP S57193125A
Authority
JP
Japan
Prior art keywords
trg22
gate
signal
buffer circuit
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56078055A
Other languages
Japanese (ja)
Inventor
Hiroshi Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56078055A priority Critical patent/JPS57193125A/en
Publication of JPS57193125A publication Critical patent/JPS57193125A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Abstract

PURPOSE:To reduce patern occupying areas and to achieve high speed, by effectively using a transmission gate and decreasing the number of transistors. CONSTITUTION:When an enable signal E is 1, since 1 is given to a PMOS gate of a transmission gate TRG22 and 0 is applied to an NMOS gate, the TRG22 turns off and an output-0 is at high impedance state. When the signal E is 0, 0 is applied to the PMOS gate of the TRG22 and 1 is applied to the NMOS gate, the TRG22 turns on and an inverting signal of an input data signal D is outputted at the terminal O'. Thus, the number of transistors can remarkably be reduced, the occupying area can be reduced and a ternary buffer circuit having short delay time and high speed operation can be obtained.
JP56078055A 1981-05-25 1981-05-25 Ternary buffer circuit Pending JPS57193125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56078055A JPS57193125A (en) 1981-05-25 1981-05-25 Ternary buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56078055A JPS57193125A (en) 1981-05-25 1981-05-25 Ternary buffer circuit

Publications (1)

Publication Number Publication Date
JPS57193125A true JPS57193125A (en) 1982-11-27

Family

ID=13651162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56078055A Pending JPS57193125A (en) 1981-05-25 1981-05-25 Ternary buffer circuit

Country Status (1)

Country Link
JP (1) JPS57193125A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0219848A2 (en) * 1985-10-22 1987-04-29 Siemens Aktiengesellschaft Space switching device for broad-band signals
US4709173A (en) * 1985-05-17 1987-11-24 Matsushita Electric Industrial Co., Ltd. Integrated circuit having latch circuit with multiplexer selection function
US4940904A (en) * 1988-05-23 1990-07-10 Industrial Technology Research Institute Output circuit for producing positive and negative pulses at a single output terminal

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5087266A (en) * 1973-12-04 1975-07-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5087266A (en) * 1973-12-04 1975-07-14

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4709173A (en) * 1985-05-17 1987-11-24 Matsushita Electric Industrial Co., Ltd. Integrated circuit having latch circuit with multiplexer selection function
EP0219848A2 (en) * 1985-10-22 1987-04-29 Siemens Aktiengesellschaft Space switching device for broad-band signals
US5047766A (en) * 1985-10-22 1991-09-10 Siemens Aktiengesellschaft Broad band signal switching matrix
US4940904A (en) * 1988-05-23 1990-07-10 Industrial Technology Research Institute Output circuit for producing positive and negative pulses at a single output terminal

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