JPS54111745A - Static type logic circuit - Google Patents

Static type logic circuit

Info

Publication number
JPS54111745A
JPS54111745A JP1844278A JP1844278A JPS54111745A JP S54111745 A JPS54111745 A JP S54111745A JP 1844278 A JP1844278 A JP 1844278A JP 1844278 A JP1844278 A JP 1844278A JP S54111745 A JPS54111745 A JP S54111745A
Authority
JP
Japan
Prior art keywords
circuit
voltage
output
2vcc
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1844278A
Other languages
Japanese (ja)
Inventor
Takeshi Saito
Tsuneo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1844278A priority Critical patent/JPS54111745A/en
Publication of JPS54111745A publication Critical patent/JPS54111745A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent the lowering in the logic output level and the operation speed, by providing MISFET operated with the output of the booster circuit taking the pulse signal as input at the power supply side of the logic circuit. CONSTITUTION:In the address buffer for memory IC, MISFETQ32 to Q34 are used as the power switch to reduce power consumption at the power supply voltage Vcc, and each gate is connected to the booster circuit 3 via the bootstrap circuit 5. Further, when the chip selection signal CE is at low level, pulse signal is outputted from the oscillation circuit 2, the high voltage side voltage VCB1 of the capacitor CB1 of the booster circuit 3 is 2Vcc-2Vth (where: Vth is threshold voltage for each FET), and the voltage VCB1' fed to the gate of FETQ32 to Q34 is 2Vcc-3Vth. But, the delay in the output of the circuit 3 can be covered with the output voltage 2Vcc-Vth by the buffer amplifier 4 and the circuit 5. Accordingly, the power supply voltage for FETQ35 and Q36 can be increased to Vcc.
JP1844278A 1978-02-22 1978-02-22 Static type logic circuit Pending JPS54111745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1844278A JPS54111745A (en) 1978-02-22 1978-02-22 Static type logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1844278A JPS54111745A (en) 1978-02-22 1978-02-22 Static type logic circuit

Publications (1)

Publication Number Publication Date
JPS54111745A true JPS54111745A (en) 1979-09-01

Family

ID=11971742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1844278A Pending JPS54111745A (en) 1978-02-22 1978-02-22 Static type logic circuit

Country Status (1)

Country Link
JP (1) JPS54111745A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56122526A (en) * 1980-03-03 1981-09-26 Fujitsu Ltd Semiconductor integrated circuit
JPS57124938A (en) * 1981-01-26 1982-08-04 Nec Corp Semiconductor circuit
JPS589433A (en) * 1981-07-08 1983-01-19 Toshiba Corp Semiconductor integrated circuit
US4504746A (en) * 1981-04-16 1985-03-12 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor buffer circuit using enhancement-mode, depletion-mode and zero threshold mode transistors
JPS60227517A (en) * 1984-04-25 1985-11-12 Sharp Corp Pull-up circuit of mos semiconductor integrated circuit element

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56122526A (en) * 1980-03-03 1981-09-26 Fujitsu Ltd Semiconductor integrated circuit
JPH0449291B2 (en) * 1980-03-03 1992-08-11 Fujitsu Ltd
JPS57124938A (en) * 1981-01-26 1982-08-04 Nec Corp Semiconductor circuit
US4504746A (en) * 1981-04-16 1985-03-12 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor buffer circuit using enhancement-mode, depletion-mode and zero threshold mode transistors
JPS589433A (en) * 1981-07-08 1983-01-19 Toshiba Corp Semiconductor integrated circuit
JPH0413890B2 (en) * 1981-07-08 1992-03-11 Tokyo Shibaura Electric Co
JPS60227517A (en) * 1984-04-25 1985-11-12 Sharp Corp Pull-up circuit of mos semiconductor integrated circuit element
JPH0428178B2 (en) * 1984-04-25 1992-05-13 Sharp Kk

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