JPS55101179A - Information transfer system - Google Patents

Information transfer system

Info

Publication number
JPS55101179A
JPS55101179A JP825679A JP825679A JPS55101179A JP S55101179 A JPS55101179 A JP S55101179A JP 825679 A JP825679 A JP 825679A JP 825679 A JP825679 A JP 825679A JP S55101179 A JPS55101179 A JP S55101179A
Authority
JP
Japan
Prior art keywords
hierarchical memory
memory unit
information
scan
skip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP825679A
Other languages
Japanese (ja)
Other versions
JPS5827905B2 (en
Inventor
Koichi Miyauchi
Akira Matsumoto
Toshiaki Ito
Toshio Nishimori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP54008256A priority Critical patent/JPS5827905B2/en
Publication of JPS55101179A publication Critical patent/JPS55101179A/en
Publication of JPS5827905B2 publication Critical patent/JPS5827905B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To improve the use efficiency of a transfer bus by performing skip control according to presence and absence of information at a scanning time for information transfer from the second hierarchical memory units to the first hierarchical memory unit by using a scan skipping register.
CONSTITUTION: An address signal to scan the second hierarchical memory units is generated from scan address counter 201 of the first hierarchical memory unit for the purpose of transferring information from the second hierarchical memory units to the first hierarchical memory unit and is applied to AND circuits 203 through decoder circuit 202, and AND between the address signal above and a count value, which is set in scan skip register 200 and corresponds to the address of the second hierarchical memory unit of information absence, dependent upon AND circuits 203 is applied to transfer bus control circuit 206 through OR circuit 209 as a skip signal for transfer information absence. Therefore, counter 201 is updated through circuit 206 to skip scanning of the second hierarchical memory unit having no tranfer data. Consequently, the transfer bus is not used for needless scanning, so that the use efficiency can be improved.
COPYRIGHT: (C)1980,JPO&Japio
JP54008256A 1979-01-29 1979-01-29 Information transfer method Expired JPS5827905B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54008256A JPS5827905B2 (en) 1979-01-29 1979-01-29 Information transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54008256A JPS5827905B2 (en) 1979-01-29 1979-01-29 Information transfer method

Publications (2)

Publication Number Publication Date
JPS55101179A true JPS55101179A (en) 1980-08-01
JPS5827905B2 JPS5827905B2 (en) 1983-06-13

Family

ID=11688053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54008256A Expired JPS5827905B2 (en) 1979-01-29 1979-01-29 Information transfer method

Country Status (1)

Country Link
JP (1) JPS5827905B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48100030A (en) * 1972-03-29 1973-12-18
JPS4924332A (en) * 1972-06-28 1974-03-04
JPS4938059A (en) * 1972-08-23 1974-04-09
JPS5028704A (en) * 1973-07-13 1975-03-24

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS48100030A (en) * 1972-03-29 1973-12-18
JPS4924332A (en) * 1972-06-28 1974-03-04
JPS4938059A (en) * 1972-08-23 1974-04-09
JPS5028704A (en) * 1973-07-13 1975-03-24

Also Published As

Publication number Publication date
JPS5827905B2 (en) 1983-06-13

Similar Documents

Publication Publication Date Title
JPS57105879A (en) Control system for storage device
JPS57121746A (en) Information processing device
JPS55101179A (en) Information transfer system
JPS5373927A (en) Replacing system of intermediate buffer memory
JPS5537609A (en) Terminal equipment
JPS5371537A (en) Information processor
JPS5326632A (en) Common memory control unit
JPS5638631A (en) Data transfer apparatus
JPS5570998A (en) Block switching system for memory unit
JPS5275944A (en) Register system of interruption address
JPS5525820A (en) Buffer memory device
JPS52129241A (en) Memory control system
JPS5545169A (en) Memory unit
JPS5374856A (en) Data process system
JPS522237A (en) Data processing apparatus
JPS5478635A (en) Data transfer control circuit
JPS563486A (en) Magnetic bubble memory control system
JPS56162166A (en) Data transfer system
JPS54157444A (en) Memory control system
JPS5413228A (en) Interface circuit of auxiliary memory unit
JPS5674761A (en) Information processor
JPS52150944A (en) Information transfer control unit
JPS5597655A (en) Memory access system
JPS55150031A (en) Direct memory access unit
JPS5211835A (en) Buffer register control system