JPS63132342A - Fault detection circuit - Google Patents

Abstract

PURPOSE:To detect a fault produced in a decoding circuit, the increasing of the quantity of a hardware being suppressed by inputting the output data of the decoding circuit to a coding circuit, and comparing its output data with the input data of the decoding circuit. CONSTITUTION:The output signal 12 of the decoding circuit 1 to decode an input signal 11 is inputted to the coding circuit 2, and the input signal 11 of the decoding circuit 1 and the output signal 13 of the coding circuit 2 are inputted to a comparison circuit 3 and compared and checked, and a fault detection signal 14 is informed to an error processing circuit. When the decoding circuit 1 is of three inputs, the coding circuit 2 goes to eight inputs, but the comparison circuit 3 goes to a group of three inputs, and being compared with the comparison circuit 3, which goes to eight inputs if the decoding circuit 1 is simply duplexed, the hardware quantity can be remarkably reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for directly detecting failures occurring in decoding circuits and encoding circuits in information processing devices, etc. with high detection ability. .

[Conventional technology]

For information on conventional decoding circuit checking methods and their detection capabilities, see IBM Journal.

Research and Development, Volume 26
．． Number 1. (January 1982) page 73 (IBM
J, RES, DEVELOP, VOL26. A1゜JA
NUARY (1982) pp73).

For data processed by information processing equipment, etc.

In order to increase the reliability of the data, parity information is often applied and this is handled as a unit of data processing. Generally, the occurrence of a failure is discovered by checking such parity information with a detection circuit. However, there are control logics that are not suitable for parity checking.

A typical example of this is the decoding circuit.

In the conventional technology, focusing on the characteristic that only one signal line is 1ON in the output signal line of the decoding circuit as shown in Fig. 2, two or more signal lines are ``ON'' or all are 1OFF.
” We are checking the status.

In addition, the conventional conveyor check method is one of the methods that can be applied to failure detection in encoder circuits.
E.E., Computer, (October 1979) No. 4
Pages 9 to 1459 (IEi.

C0MPU'L'gR,,0CTOBER(1979)
pp. 49-59).

An example of application of this method to an encoding circuit is shown in FIG. That is, the method involved inputting common input data to two encoding circuits having the same function and comparing the outputs of the respective encoding circuits. This method assumes that the input data of the encoding circuit is normal.
No consideration was given to detecting failures transmitted to the encoding circuit.

[Problem that the invention seeks to solve]

In the conventional decoding circuit failure checking method.

It is known that the detection ability is about 70%. In addition, it is believed that the duplex check method shown in Figure 4 has the highest detection ability as a check method for control logic, but if the decoding circuit is simply duplicated and checked, the amount of hardware for the comparison circuit will be reduced. 2 for the number of inputs
There is a problem that increases in proportion to the X power of

A first object of the present invention is to provide a fault detection method that has high detection capability while suppressing an increase in the amount of hardware required for faults occurring in a decoding circuit.

Further, the above-mentioned conventional technology does not take into consideration the detection of failures transmitted to the encoding circuit, and there is a problem in that even if there is a failure in the input data of the encoding circuit, it is considered normal.

The second object of the present invention is to detect a failure in which multiple bits become 1'' and are input to the encoder circuit even though it is assumed that only one bit of the input data to the encoder circuit is 1''. The purpose is to improve the detection rate of the entire circuit by making it possible to

[Means for solving problems]

The first object is achieved by adding to the decoding circuit an encoding circuit which inputs the output data of the decoding circuit, and checking the input data of the decoding circuit and the output data of the encoding circuit with a comparison circuit.

The second object is achieved by adding a decoding circuit to the encoding circuit, which inputs the output data of the encoding circuit, and checking the input data of the encoding circuit and the output data of the decoding circuit in a comparison circuit.

[Effect]

The number of signals input to the decoding circuit, X, increases by 2 to the Returns to X. As a result, only X comparison circuits are required for comparing and checking the output signals of the decoding circuit.

Furthermore, in the output data of the decoding circuit which receives the output data of the encoding circuit as input, only one bit of the output data is always 1'', regardless of the value of the input data of the encoding circuit. When input data such that a plurality of bits are 1'' is input to the circuit, a failure can be detected by comparing the input data of the encode circuit and the output data of the decode circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. a decoding circuit 1 that decodes an input signal 111; an encoding circuit 2 that receives an output signal 12 of the decoding circuit 1;
It is comprised of a comparison circuit 3 that compares and checks the input signal 11 of the decoding circuit 1 and the output signal 13 of the encoding circuit 2, and reports a failure detection signal 14 to the error processing circuit.

In the case of the embodiment in which the decoding circuit l is powered by three people, the encoding circuit 2 is powered by eight people, but the comparison circuit is a group of three people powered.
This has the effect of greatly reducing the amount of hardware compared to the comparator circuit 3 which is made up of 8 people and is made by simply duplicating the decoding circuit 1.

A second embodiment of the present invention will be described with reference to FIG. an encoding circuit 10 that encodes input data 100;
A decoding circuit 20 that receives the output take 200 of the encoding circuit 10 as an input, and input data 1 of the encoding circuit 10.
00 and output data 300 of the decoding circuit 20, and reports a failure detection signal 400 to the error processing circuit.

For example, if the input data 100 of the encoder circuit 10 is 4 bits, of which 2 bits are "1", the output data 300 of the decode circuit 20 is such that 1 bit of the 4 bits is "1".
1'' and is input to the comparator 30 and compared with the input data 100, it becomes possible to easily detect a failure in the input data 100 of the encoder circuit 10.

In addition, regarding the failure of the encoding circuit 10 itself, the output data 300 of the decoding circuit 20 and the encoding circuit 1
By comparing the value of input data 100 of 0, it becomes possible to easily detect it.

〔Effect of the invention〕

According to the present invention, the check target signal once increased in the decoding circuit is returned to its original number in the encoding circuit, so that the hardware fie? It has the effect of increasing Ifc. Specifically, the decodes to be checked are 2.
In the case of manual operation, a comparison circuit (EXCLUSiVE OR
Below, 2 EOf (, omitted) can be deleted, 5EOR for 3-manpower, 1zgoa for 14-manpower, 27EOR for s input, and so on. It has the effect of reducing

Furthermore, according to the present invention, it is possible to detect not only failures in the second/code circuit itself but also failures transmitted to the encoder circuit, improving the ability to detect comparative failures in the conveyor check system. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 2 is a block diagram of a decoding check introduced in the literature. FIG. 3 is a conventional block diagram in which the encoding circuit is simply duplicated. FIG. 4 is a conventional block diagram in which the decoding circuit is simply duplicated. FIG. 5 is a block diagram showing a second embodiment of the present invention. 1...Decoding circuit, 2...Encoding circuit, 3.
...Comparison circuit, 4...OR circuit, 5...NOR circuit, 6...AND circuit, 7...decoding circuit, 8...
- Comparison circuit, 11... Decode input signal, 12...
Decode output signal, 13...Encode output signal, 1
4... Failure detection signal, 15... Part of decoded output signal, 16... Part of decoded output signal, 17...
Decode output signal. 10... Encoding circuit, 20... Decoding circuit,
30... Comparison circuit, 40... Encoding circuit, 10
0...Encode input data, 200...Encode output data, 300...Decode output data, 40
0... Failure detection signal, 500... Encoded output data. Agent Patent Attorney Katsuo Ogawa (',. ¥/ Mouth 3 Comparison Mouth pr 13-Sicoat F Kaiman No. 82
I! ] 3rd ward 4o kunfu Y''guchi k 4oO leaving (choden Nakamachi Kozuchigouri 4i!1

Claims (1)

[Claims] 1. In a logic circuit (decoding circuit) that restores a group of encoded signals, a logic circuit (encoding circuit) that re-encodes the output signal of the decoding circuit, and the output signal of the encoding circuit. What is claimed is: 1. A failure detection circuit comprising a failure detection circuit comprising a comparison circuit for comparing an exclusive state between a group of input signals and a group of input signals of the decoding circuit. 2. In a logic circuit (encoding circuit) that encodes a signal group, a logic circuit (decoding circuit) that restores the output signal of the encoding circuit, and a logic circuit (decoding circuit) that restores the output signal of the decoding circuit and the input signal group of the encoding circuit. and a comparator that compares exclusive states between the two, and is capable of detecting failures transmitted to the encoding circuit and malfunctions of the encoding circuit itself.