JPH0296697U - - Google Patents

Info

Publication number
JPH0296697U
JPH0296697U JP471789U JP471789U JPH0296697U JP H0296697 U JPH0296697 U JP H0296697U JP 471789 U JP471789 U JP 471789U JP 471789 U JP471789 U JP 471789U JP H0296697 U JPH0296697 U JP H0296697U
Authority
JP
Japan
Prior art keywords
controller
memory cell
read address
address counter
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP471789U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP471789U priority Critical patent/JPH0296697U/ja
Publication of JPH0296697U publication Critical patent/JPH0296697U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Communication Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のブロツク図、第2
図は本実施例の動作の流れを示すタイムチヤート
、第3図は従来のFIFOメモリのブロツク図で
ある。 1……アドレスコントローラ、2……読み出し
アドレスカウンタ、3……セレクタ、4……ロウ
アドレスデコーダ、5……カラムアドレスデコー
ダ、6……メモリセル、7……I/Oバツフア、
8……入力コントローラ、9……レジスタ、10
……出力バツフア、11……入力コントローラ、
12……レジスタコントローラ、13……出力コ
ントローラ。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a time chart showing the flow of operation of this embodiment, and FIG. 3 is a block diagram of a conventional FIFO memory. 1... Address controller, 2... Read address counter, 3... Selector, 4... Row address decoder, 5... Column address decoder, 6... Memory cell, 7... I/O buffer,
8...Input controller, 9...Register, 10
...Output buffer, 11...Input controller,
12...Register controller, 13...Output controller.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メモリセルと、プリセツト機能を有する読み出
しアドレスカウンタとを具備することを特徴とす
るFIFOメモリ。
A FIFO memory comprising a memory cell and a read address counter having a preset function.
JP471789U 1989-01-18 1989-01-18 Pending JPH0296697U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP471789U JPH0296697U (en) 1989-01-18 1989-01-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP471789U JPH0296697U (en) 1989-01-18 1989-01-18

Publications (1)

Publication Number Publication Date
JPH0296697U true JPH0296697U (en) 1990-08-01

Family

ID=31207475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP471789U Pending JPH0296697U (en) 1989-01-18 1989-01-18

Country Status (1)

Country Link
JP (1) JPH0296697U (en)

Similar Documents

Publication Publication Date Title
JPH0296697U (en)
JPH022751U (en)
JPS6294498U (en)
JPS6335147U (en)
JPH0246245U (en)
JPS61126500U (en)
JPS62121652U (en)
JPS63171850U (en)
JPS6381397U (en)
JPH01146400U (en)
JPS6316335U (en)
JPS5915148U (en) microcomputer
JPH0363246U (en)
JPS63179548U (en)
JPS6239384U (en)
JPS6170240U (en)
JPS6397148U (en)
JPS6452076U (en)
JPS63163541U (en)
JPS62179663U (en)
JPS6397149U (en)
JPH0168504U (en)
JPH0341349U (en)
JPH02113899U (en)
JPS63138699U (en)