JPS63138699U - - Google Patents

Info

Publication number
JPS63138699U
JPS63138699U JP2877387U JP2877387U JPS63138699U JP S63138699 U JPS63138699 U JP S63138699U JP 2877387 U JP2877387 U JP 2877387U JP 2877387 U JP2877387 U JP 2877387U JP S63138699 U JPS63138699 U JP S63138699U
Authority
JP
Japan
Prior art keywords
signal
processor
programming
signal line
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2877387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2877387U priority Critical patent/JPS63138699U/ja
Publication of JPS63138699U publication Critical patent/JPS63138699U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す装置のブロツ
ク図、第2図は本考案の他の実施例を示す装置の
ブロツク図である。 1……プログラミング装置、2……コントロー
ラ本体、3,7……アドレスバス、4……データ
バス、5……コントロールバス、6……メモリ、
8……スイツチ、9……アドレス信号線、10…
…内部レジスタ。
FIG. 1 is a block diagram of a device showing one embodiment of the present invention, and FIG. 2 is a block diagram of a device showing another embodiment of the present invention. 1... Programming device, 2... Controller body, 3, 7... Address bus, 4... Data bus, 5... Control bus, 6... Memory,
8...Switch, 9...Address signal line, 10...
...internal register.

Claims (1)

【実用新案登録請求の範囲】 着脱可能なプログラミング手段によつてプログ
ラムされたプログラムに基づき、制御を行うブロ
セツサに設けられ、 前記プログラミング手段と前記プロセツサ内部
のメモリとを接続するアドレスバスに付加する信
号線と、 該信号線の信号の値を切換えることにより前記
メモリの使用領域を変更する信号切換手段と を具えたことを特徴とするプログラミング容量拡
張装置。
[Claims for Utility Model Registration] A signal provided in a processor that performs control based on a program programmed by a removable programming means and added to an address bus connecting the programming means and a memory inside the processor. 1. A programming capacity expansion device comprising: a signal line; and a signal switching means for changing the memory usage area by switching the value of the signal on the signal line.
JP2877387U 1987-03-02 1987-03-02 Pending JPS63138699U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2877387U JPS63138699U (en) 1987-03-02 1987-03-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2877387U JPS63138699U (en) 1987-03-02 1987-03-02

Publications (1)

Publication Number Publication Date
JPS63138699U true JPS63138699U (en) 1988-09-13

Family

ID=30832044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2877387U Pending JPS63138699U (en) 1987-03-02 1987-03-02

Country Status (1)

Country Link
JP (1) JPS63138699U (en)

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