JPH0267433U - - Google Patents
Info
- Publication number
- JPH0267433U JPH0267433U JP14346188U JP14346188U JPH0267433U JP H0267433 U JPH0267433 U JP H0267433U JP 14346188 U JP14346188 U JP 14346188U JP 14346188 U JP14346188 U JP 14346188U JP H0267433 U JPH0267433 U JP H0267433U
- Authority
- JP
- Japan
- Prior art keywords
- program
- memory
- control program
- working memory
- storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 7
- 230000003936 working memory Effects 0.000 claims 6
- 238000010586 diagram Methods 0.000 description 6
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Description
第１図は本考案実施例の基本的な構成を示すブ
ロツク図、第２図は本考案実施例の具体的な回路
構成を示す回路図、第３図は第２図に示す選択回
路３０５の構成を示す回路図、第４図は第２図に
示すＲＯＭ３０２およびＲＡＭ３０３のメモリ構
成を示すメモリマツプ。第５図は第２図に示すマ
イクロプロセツサ３０１が実行する制御手順を示
すフローチヤート、第６図は本考案実施例の信号
発生タイミングを示すフローチヤート、第７図は
本考案他の実施例の回路構成を示す回路図、第８
図は従来例の回路構成を示す回路図、第９図は従
来例のアドレスの割り当てを示すアドレスマツプ
である。
１０１，３０１…マイクロプロセツサ、１０２
，３０２…ＲＯＭ、１０３，３０３…ＲＡＭ、１
０６，３０４…デコーダ、３０５…選択回路、３
１５…電源投入リセツト信号発生回路。
FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific circuit configuration of the embodiment of the present invention, and FIG. 3 is a block diagram of the selection circuit 305 shown in FIG. 4 is a circuit diagram showing the configuration, and FIG. 4 is a memory map showing the memory configuration of the ROM 302 and RAM 303 shown in FIG. 2. FIG. 5 is a flowchart showing the control procedure executed by the microprocessor 301 shown in FIG. 2, FIG. 6 is a flowchart showing signal generation timing in an embodiment of the present invention, and FIG. 7 is another embodiment of the present invention. Circuit diagram showing the circuit configuration of
The figure is a circuit diagram showing the circuit configuration of a conventional example, and FIG. 9 is an address map showing address assignment in the conventional example. 101, 301...Microprocessor, 102
, 302...ROM, 103, 303...RAM, 1
06,304...decoder, 305...selection circuit, 3
15...Power-on reset signal generation circuit.
Claims (1)
メモリと、 前記制御プログラムの演算処理で用いられる演
算データを記憶する作業用メモリと、 電源の投入に応じて前記プログラム専用メモリ
の前記制御プログラムを前記作業用メモリに転送
する転送手段と、 前記転送後は前記作業用メモリから前記制御プ
ログラムを読み出して演算実行する演算回路と を具えたことを特徴とする中央演算処理装置。 (2) 請求項１に記載の中央演算処理装置におい
て、 前記プログラム専用メモリおよび前記作業用メ
モリの前記制御プログラムの格納アドレスを予め
同一に設定し、前記転送手段は、前記制御プログ
ラムの転送後は前記作業用メモリのみを動作可能
状態とすることを特徴とする中央演算処理装置。[Claims for Utility Model Registration] (1) A program-dedicated memory for storing a control program, a working memory for storing arithmetic data used in the arithmetic processing of the control program, and a program-dedicated memory for storing the program-dedicated memory when power is turned on. A central processing unit comprising: a transfer means for transferring the control program to the working memory; and an arithmetic circuit that reads the control program from the working memory and executes an operation after the transfer. (2) In the central processing unit according to claim 1, storage addresses of the control program in the program-dedicated memory and the working memory are set to be the same in advance, and the transfer means is configured to control the storage address of the control program in the program-dedicated memory and the working memory to A central processing unit characterized in that only the working memory is enabled for operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14346188U JPH0267433U (en) | 1988-11-04 | 1988-11-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14346188U JPH0267433U (en) | 1988-11-04 | 1988-11-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0267433U true JPH0267433U (en) | 1990-05-22 |
Family
ID=31410310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14346188U Pending JPH0267433U (en) | 1988-11-04 | 1988-11-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0267433U (en) |
-
1988
- 1988-11-04 JP JP14346188U patent/JPH0267433U/ja active Pending
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