JPH0289556U - - Google Patents
Info
- Publication number
- JPH0289556U JPH0289556U JP16628388U JP16628388U JPH0289556U JP H0289556 U JPH0289556 U JP H0289556U JP 16628388 U JP16628388 U JP 16628388U JP 16628388 U JP16628388 U JP 16628388U JP H0289556 U JPH0289556 U JP H0289556U
- Authority
- JP
- Japan
- Prior art keywords
- reset
- power
- chip microcomputer
- register
- incorporating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Microcomputers (AREA)
Description
第１図は本考案の第１の実施例のブロツク図、
第２図は第１図の１チツプマイクロコンピユータ
に内蔵されるレジスタのブロツク図、第３図は本
考案の第２の実施例のブロツク図である。
１……１チツプマイクロコンピユータ、２……
外部回路、３……シリアルデータバス、４……シ
リアルクロツク、５……レジスタ、６……パワー
オン判別フラグ、７……１チツプマイクロコンピ
ユータ、８……ＰＲＯＭ、９……アドレス、１０
……データバス、１１……リード信号、１２……
リセツトアウト信号。
FIG. 1 is a block diagram of the first embodiment of the present invention;
FIG. 2 is a block diagram of a register built into the one-chip microcomputer shown in FIG. 1, and FIG. 3 is a block diagram of a second embodiment of the present invention. 1...1 chip microcomputer, 2...
External circuit, 3... Serial data bus, 4... Serial clock, 5... Register, 6... Power-on determination flag, 7... 1-chip microcomputer, 8... PROM, 9... Address, 10
...Data bus, 11...Read signal, 12...
Reset out signal.
Claims (1)
ブルと、パワーオンリセツトかシステムリセツト
かの判別を行いパワーオンリセツト時に書込みを
行うように制御するレジスタとを内蔵することを
特徴とする１チツプマイクロコンピユータ。 A one-chip microcomputer characterized by incorporating an interrupt vector table configured using a RAM and a register for determining whether a power-on reset or a system reset is being performed and controlling writing to be performed at the time of a power-on reset.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16628388U JPH0289556U (en) | 1988-12-21 | 1988-12-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16628388U JPH0289556U (en) | 1988-12-21 | 1988-12-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0289556U true JPH0289556U (en) | 1990-07-16 |
Family
ID=31453531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16628388U Pending JPH0289556U (en) | 1988-12-21 | 1988-12-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0289556U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6766448B2 (en) | 2000-01-13 | 2004-07-20 | Nec Corporation | Microcomputer for transferring program data to an internal memory from an external memory connected via a bus and a method therefor |
-
1988
- 1988-12-21 JP JP16628388U patent/JPH0289556U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6766448B2 (en) | 2000-01-13 | 2004-07-20 | Nec Corporation | Microcomputer for transferring program data to an internal memory from an external memory connected via a bus and a method therefor |
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