JPH0313504U - - Google Patents
Info
- Publication number
- JPH0313504U JPH0313504U JP7211189U JP7211189U JPH0313504U JP H0313504 U JPH0313504 U JP H0313504U JP 7211189 U JP7211189 U JP 7211189U JP 7211189 U JP7211189 U JP 7211189U JP H0313504 U JPH0313504 U JP H0313504U
- Authority
- JP
- Japan
- Prior art keywords
- data
- storage memory
- condition information
- data storage
- sampling circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 5
- 238000013500 data storage Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Numerical Control (AREA)
Description
第１図はこの考案の一実施例による数値制御装
置の構成図、第２図は従来の数値制御装置の構成
図である。
図において、１５……トレース条件設定回路、
１８……データサンプリング回路、１９……サン
プリング制御信号、２０……データ記憶メモリ、
２１……バツテリである。なお、図中同一符号は
同一、または相当部分を示す。
FIG. 1 is a block diagram of a numerical control device according to an embodiment of this invention, and FIG. 2 is a block diagram of a conventional numerical control device. In the figure, 15... trace condition setting circuit;
18...Data sampling circuit, 19...Sampling control signal, 20...Data storage memory,
21...I'm exhausted. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ング条件情報がトレース条件設定回路に入力され
ると、ＣＰＵのアドレス、データ、コントロール
信号などの状態をデータサンプリング回路に読み
込み、前記データサンプリング回路からのデータ
をバツテリバツクアツプされたデータ記憶メモリ
に格納し、必要に応じてデータ記憶メモリの内容
を表示器に表示させることを特徴とする数値制御
装置。 When trace condition information and sampling condition information are input to the trace condition setting circuit from the key input means, the states of the CPU address, data, control signals, etc. are read into the data sampling circuit, and the data from the data sampling circuit is battery-backed. A numerical control device characterized by storing data in an uploaded data storage memory and displaying the contents of the data storage memory on a display as necessary.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7211189U JPH0313504U (en) | 1989-06-20 | 1989-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7211189U JPH0313504U (en) | 1989-06-20 | 1989-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0313504U true JPH0313504U (en) | 1991-02-12 |
Family
ID=31609755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7211189U Pending JPH0313504U (en) | 1989-06-20 | 1989-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0313504U (en) |
-
1989
- 1989-06-20 JP JP7211189U patent/JPH0313504U/ja active Pending