JPS6335147U - - Google Patents

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Publication number
JPS6335147U
JPS6335147U JP12682686U JP12682686U JPS6335147U JP S6335147 U JPS6335147 U JP S6335147U JP 12682686 U JP12682686 U JP 12682686U JP 12682686 U JP12682686 U JP 12682686U JP S6335147 U JPS6335147 U JP S6335147U
Authority
JP
Japan
Prior art keywords
address signal
access port
parallel
selection means
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12682686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12682686U priority Critical patent/JPS6335147U/ja
Publication of JPS6335147U publication Critical patent/JPS6335147U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す構成ブロツク
図、第2図は第1図の装置の動作説明図、第3図
は従来装置の構成図である。 7……選択回路、8……メモリ回路、9……ア
クセス制御回路、12……S/P変換回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the device shown in FIG. 1, and FIG. 3 is a diagram showing the configuration of a conventional device. 7... Selection circuit, 8... Memory circuit, 9... Access control circuit, 12... S/P conversion circuit.

Claims (1)

【実用新案登録請求の範囲】 パラレルアクセスポートとシリアルアクセスポ
ートとを有する2ポートメモリにおいて、 前記シリアルアクセスポートから入力されるア
ドレス信号を受信してパラレルアドレス信号に変
換するS/P変換手段と、 このS/P変換手段で出力されるアドレス信号
と、前記パラレルアクセスポートから出力される
アドレス信号とを選択する選択手段と、 この選択手段で選択されたアドレス信号に対応
するデータの読出し/書込み動作の終了を検出し
、この終了を前記選択手段が選択したアドレス信
号の出力された側に知らせるアクセス制御手段 とを設けたことを特徴とする2ポートメモリ。
[Claims for Utility Model Registration] In a two-port memory having a parallel access port and a serial access port, S/P conversion means receives an address signal input from the serial access port and converts it into a parallel address signal; selection means for selecting an address signal output from the S/P conversion means and an address signal output from the parallel access port; read/write operations for data corresponding to the address signal selected by the selection means; and access control means for detecting the end of the address signal and notifying the end to the side to which the address signal selected by the selection means has been output.
JP12682686U 1986-08-20 1986-08-20 Pending JPS6335147U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12682686U JPS6335147U (en) 1986-08-20 1986-08-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12682686U JPS6335147U (en) 1986-08-20 1986-08-20

Publications (1)

Publication Number Publication Date
JPS6335147U true JPS6335147U (en) 1988-03-07

Family

ID=31021002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12682686U Pending JPS6335147U (en) 1986-08-20 1986-08-20

Country Status (1)

Country Link
JP (1) JPS6335147U (en)

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