JPS61115255U - - Google Patents

Info

Publication number
JPS61115255U
JPS61115255U JP20289885U JP20289885U JPS61115255U JP S61115255 U JPS61115255 U JP S61115255U JP 20289885 U JP20289885 U JP 20289885U JP 20289885 U JP20289885 U JP 20289885U JP S61115255 U JPS61115255 U JP S61115255U
Authority
JP
Japan
Prior art keywords
shift register
shift
data
counts
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20289885U
Other languages
Japanese (ja)
Other versions
JPS638983Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985202898U priority Critical patent/JPS638983Y2/ja
Publication of JPS61115255U publication Critical patent/JPS61115255U/ja
Application granted granted Critical
Publication of JPS638983Y2 publication Critical patent/JPS638983Y2/ja
Expired legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は本考案の実施例のブロツク図を示す。 図中、１はシフトレジスタ、２はアツプダウン
カウンタ、３はシフトレジスタからの読出しを行
なう回路である。 The drawing shows a block diagram of an embodiment of the invention. In the figure, 1 is a shift register, 2 is an up-down counter, and 3 is a circuit for reading from the shift register.

Claims (1)

【実用新案登録請求の範囲】 複数の入力データをシフトさせて蓄積できるシ
フトレジスタと、 このシフトレジスタへの書込み及び読出しを指
示するリードライト信号線と、 リードライト信号線の信号状態に応じて動作し
、このシフトレジスタへデータ入力される都度ア
ツプカウントし、入力データが出力される時アツ
プカウントしたカウント値をダウンカウントする
アツプダウンカウントと、 前記カウンタの内容をシフトレジスタのシフト
位置に対応するアドレス信号として受信し、前記
シフトレジスタから該アドレス信号が示すシフト
位置の蓄積データを選択的に読出す回路とを備え
ることを特徴とする入出力データの制御回路。[Claims for Utility Model Registration] A shift register that can shift and store multiple input data, a read/write signal line that instructs writing and reading to this shift register, and an operation according to the signal state of the read/write signal line. An up-down count that counts up each time data is input to this shift register, and down-counts the up-count value when input data is output, and an up-down count that counts down the up-count value when input data is output, and an address corresponding to the shift position of the shift register to set the contents of the counter. An input/output data control circuit comprising: a circuit that receives the address signal as a signal and selectively reads accumulated data at a shift position indicated by the address signal from the shift register.
JP1985202898U 1985-12-28 1985-12-28 Expired JPS638983Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985202898U JPS638983Y2 (en) 1985-12-28 1985-12-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985202898U JPS638983Y2 (en) 1985-12-28 1985-12-28

Publications (2)

Publication Number Publication Date
JPS61115255U true JPS61115255U (en) 1986-07-21
JPS638983Y2 JPS638983Y2 (en) 1988-03-17

Family

ID=30765326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985202898U Expired JPS638983Y2 (en) 1985-12-28 1985-12-28

Country Status (1)

Country Link
JP (1) JPS638983Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796392A (en) 1997-02-24 1998-08-18 Paradise Electronics, Inc. Method and apparatus for clock recovery in a digital display unit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112543A (en) * 1973-02-23 1974-10-26
JPS5082946A (en) * 1973-11-24 1975-07-04
JPS5157258A (en) * 1974-11-15 1976-05-19 Hitachi Ltd BATSUFUA MEMORIKAIRO
JPS5294040A (en) * 1976-02-03 1977-08-08 Nec Corp Data processing unit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112543A (en) * 1973-02-23 1974-10-26
JPS5082946A (en) * 1973-11-24 1975-07-04
JPS5157258A (en) * 1974-11-15 1976-05-19 Hitachi Ltd BATSUFUA MEMORIKAIRO
JPS5294040A (en) * 1976-02-03 1977-08-08 Nec Corp Data processing unit

Also Published As

Publication number Publication date
JPS638983Y2 (en) 1988-03-17

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