JPS6199991A - Digital memory device - Google Patents

Digital memory device

Info

Publication number
JPS6199991A
JPS6199991A JP21855184A JP21855184A JPS6199991A JP S6199991 A JPS6199991 A JP S6199991A JP 21855184 A JP21855184 A JP 21855184A JP 21855184 A JP21855184 A JP 21855184A JP S6199991 A JPS6199991 A JP S6199991A
Authority
JP
Japan
Prior art keywords
write
signal line
address
address signal
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21855184A
Other languages
Japanese (ja)
Inventor
Asao Yamanishi
山西 麻雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP21855184A priority Critical patent/JPS6199991A/en
Publication of JPS6199991A publication Critical patent/JPS6199991A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To write the same data in a lump and at the same time in case of writing the same data in continuous address areas, by providing a write start address signal line and a write end address signal line which have been connected to a memory body, so that an address for starting the write and an address for ending it can be designated. CONSTITUTION:Two kinds of a write start address and a write end address can be designated by a write start address signal line and a write end address signal line. That is to say, on case when write has been designated through a write signal line 2, designated data is written simultaneously through a data signal line 3 on all storage units belonging to the inside of continuous address areas designated through a write start address signal line 5 and a write end address signal line 6. In case when the same address has been designated to the write start address signal line 5 and the write end address signal line 6, data of the data signal line 3 is written on a single storage unit of a memory body 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ディジタル計算機などに用いられるディジ
タルメモリ装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital memory device used in a digital computer or the like.

〔従来の技術〕[Conventional technology]

第2図は従来のディジタルメモリ装置を示す構成図であ
り、図において1はメモリ本体、2は書込みあるいは読
出l−を区別するための書込み信号線、3は書込みある
いは読出しのためのデータ信号線、4は書込みあるいは
読出しを行なう対象を示すアドレス信号線である。
FIG. 2 is a configuration diagram showing a conventional digital memory device. In the figure, 1 is a memory main body, 2 is a write signal line for distinguishing between writing or reading l-, and 3 is a data signal line for writing or reading. , 4 are address signal lines indicating the target to be written or read.

従来のディジタルメモリ装置は上記のように構成されて
おり、アドレス信号線4によってメモリ本体1の中に格
納された特定の記憶単位が選択され、このとき書込み信
号線2を通して読出しが指定されていると、上記の記憶
単位の内容がデータ信号線3から読出される。また、上
記の書込み信号線2を通して書込みを指定しておくと、
データ信号線3のデータがメモリ本体1の上記した記憶
単位へ書込まれるようになっている。
A conventional digital memory device is configured as described above, in which a specific storage unit stored in the memory body 1 is selected by the address signal line 4, and reading is specified through the write signal line 2. Then, the contents of the above storage unit are read out from the data signal line 3. Also, if you specify writing through the write signal line 2 above,
The data on the data signal line 3 is written into the above-mentioned storage unit of the memory main body 1.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来のディジタルメモリ装置では、読出し
および書込み動作において単一の記憶単位ごとにアドレ
スを指定しなければならず、特に同一データを連続した
アドレス領域内へ書込む場合においては、アドレスを順
次加算して指定する必要があり、このために同一データ
の書込み動作が遅くなるとともに外部でのアドレス制御
も繁雑となるという問題点があった。
In conventional digital memory devices such as those described above, an address must be specified for each single storage unit during read and write operations, and especially when writing the same data into consecutive address areas, the address must be specified. It is necessary to sequentially add and specify the data, which causes problems in that the writing operation of the same data becomes slow and external address control becomes complicated.

この発明は、かかる問題点を解決するためになされたも
ので、連続したアドレス領域内に同一データを書込む場
合は、一括して同時に同一データを書込むことができる
ようにしたディジタルメモリ装置を得ることを目的とす
る。
This invention was made in order to solve this problem, and when writing the same data in consecutive address areas, a digital memory device that can write the same data at the same time is used. The purpose is to obtain.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係るディジタルメモリ装置は、書込みを開始
するアドレスと終了するアドレスを指定できるように、
メモリ本体に接続された書込み開始アドレス信号線と、
書込み終了アドレス信号線を設けたものである。
The digital memory device according to the present invention allows specifying an address to start writing and an address to end writing.
A write start address signal line connected to the memory main body,
A write end address signal line is provided.

〔作用〕[Effect]

この発明においては、書込み開始アドレス信号線と書込
み終了アドレス信号線とにより、書込み開始アドレスと
書込み終・了アドレスの2種類を指定することができる
から、アドレス範囲の指定が可能となり、同一データの
連続したアドレス領域内への同時書込みが可能となる。
In this invention, two types of write start address and write end/end address can be specified using the write start address signal line and the write end address signal line, so it is possible to specify an address range, and it is possible to specify the write start address and the write end/end address. Simultaneous writing into consecutive address areas becomes possible.

〔実施例〕〔Example〕

第1図はこの発明の一実施例を示す構成図であり、1〜
3は上記従来装置と全く同一のものである。図において
、5は書込み開始アドレス信号線、6は書込み終了アド
レス信号線である。
FIG. 1 is a block diagram showing one embodiment of the present invention, and 1 to 1 are block diagrams showing one embodiment of the present invention.
3 is exactly the same as the conventional device described above. In the figure, 5 is a write start address signal line, and 6 is a write end address signal line.

上記のように構成されたディジタルメモリ装置において
、書込み信号線2を通して読出しが指定されている場合
は、書込み終了アドレス信号線6は効力をもたずメモリ
本体1、データ信号ffJ3、書込み開始アドレス信号
線5においては従来装置で説明したと同一の動作が行な
われる。一方、書込み信号線2を通して書込みが指定さ
れている場合は、上記の書込み開始アドレス信号線5ど
書込み終了アドレス信号線6を通して指定される連続し
たアドレス領域内に属するすべての記憶単位へ、データ
信号線3を通して指定されたデータが同時に書込まれる
。なお、上記の書込み開始アドレス信号線5と■:込み
終了アドレス信号線6に、同一アドレスが指定された場
合は、従来装置で説明したと同様にデータ信号線3のデ
ータがメモリ本体1の単一の記憶単位へ書込まれる。
In the digital memory device configured as described above, when reading is specified through the write signal line 2, the write end address signal line 6 has no effect and the memory main body 1, data signal ffJ3, and write start address signal In line 5, the same operation as described for the prior art device takes place. On the other hand, when writing is specified through the write signal line 2, data signals are sent to all storage units belonging to the continuous address area specified through the write start address signal line 5 and write end address signal line 6. The data specified through line 3 are written at the same time. Note that if the same address is specified to the write start address signal line 5 and the write end address signal line 6, the data on the data signal line 3 will be transferred to a single unit of the memory main body 1, as described for the conventional device. written to one storage unit.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおり、メモリ本体に書込み開
始アドレス信号線と書込み終了アドレス信号線を接続す
る構成としたので、書込み開始アドレスと書込み終了ア
ドレスを指定することができるため、同一データの連続
したアドレス領域内への同時書込みができ、書込み動作
を高速で行なえる効果がある。
As explained above, this invention has a structure in which the write start address signal line and the write end address signal line are connected to the memory main body, so that the write start address and write end address can be specified. Simultaneous writing within the address area is possible, and the writing operation can be performed at high speed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示すディジタルメモリ装
置の構成図、第2図は従来のディジタルメモリ装置の構
成図である。 図において、5は書込み開始アドレス信号線、6は書込
み終了アドレス信号線である。 なお、各図中同一符号は同一または相当部分を示す。 第1図 5: 書込6人 関す台汀しス信号糸泉2G:書込り終
了アト瞭信号練 第2図
FIG. 1 is a block diagram of a digital memory device showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional digital memory device. In the figure, 5 is a write start address signal line, and 6 is a write end address signal line. Note that the same reference numerals in each figure indicate the same or corresponding parts. Fig. 1 5: 6 people who wrote the signal at the station Itoizumi 2G: Finished writing A clear signal training Fig. 2

Claims (1)

【特許請求の範囲】[Claims]  書込み開始アドレスと書込み終了アドレスを指定でき
るようにしたデイジタルメモリ装置において、上記メモ
リ装置のメモリ本体に接続された書込み開始アドレス信
号線と、書込み終了アドレス信号線とを備え、上記書込
み開始アドレス信号線から上記書込み開始アドレスを指
定するとともに、上記書込み終了アドレス信号線から上
記書込み終了アドレスを指定することにより、上記メモ
リ本体の連続したアドレス領域内への同一データの同時
書込みを可能としたことを特徴とするディジタルメモリ
装置。
A digital memory device capable of specifying a write start address and a write end address, comprising a write start address signal line and a write end address signal line connected to a memory main body of the memory device, the write start address signal line By specifying the write start address from , and specifying the write end address from the write end address signal line, it is possible to simultaneously write the same data into consecutive address areas of the memory body. Digital memory device.
JP21855184A 1984-10-19 1984-10-19 Digital memory device Pending JPS6199991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21855184A JPS6199991A (en) 1984-10-19 1984-10-19 Digital memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21855184A JPS6199991A (en) 1984-10-19 1984-10-19 Digital memory device

Publications (1)

Publication Number Publication Date
JPS6199991A true JPS6199991A (en) 1986-05-19

Family

ID=16721707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21855184A Pending JPS6199991A (en) 1984-10-19 1984-10-19 Digital memory device

Country Status (1)

Country Link
JP (1) JPS6199991A (en)

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