JPS58144958U - memory controller - Google Patents
memory controllerInfo
- Publication number
- JPS58144958U JPS58144958U JP4065882U JP4065882U JPS58144958U JP S58144958 U JPS58144958 U JP S58144958U JP 4065882 U JP4065882 U JP 4065882U JP 4065882 U JP4065882 U JP 4065882U JP S58144958 U JPS58144958 U JP S58144958U
- Authority
- JP
- Japan
- Prior art keywords
- field
- information
- memory
- twice
- writing speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Television Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のフィールド周波数が２倍の表示がなされ
るようにされたテレビジョン受像機の例を示す構成図、
第２図は本考案によるメモリ制御装置が適用されたテレ
ビジョン受像機の例を示す構成図、第３図及び第４図は
夫々本考案の説明に供する線図である。
１１はフィールドメモリ、１２はメモリ制御回路である
。FIG. 1 is a configuration diagram showing an example of a television receiver capable of displaying a display with twice the conventional field frequency;
FIG. 2 is a block diagram showing an example of a television receiver to which a memory control device according to the present invention is applied, and FIGS. 3 and 4 are diagrams for explaining the present invention, respectively. 11 is a field memory, and 12 is a memory control circuit.
Claims (1)
ドレス制御及び読み出し／書き込み制御をするメモリ制
御回路とよりなり、あるフィールドでは、上記フィール
ドメモリに上記あるフィールドの情報が半分書き込まれ
た時点から上記フィールドメモリより上記フィールドの
情報が書き込み速度の２倍の速度で読み出され、上記あ
るフィールドの情報が全部書き込まれる時点において上
記あるフィールドの情報が全部読み出され、上記あるフ
ィールドの次にフィールドでは、上記フィールドメモリ
より上記あるフィールドの情報が書き込みの２倍の速度
で再度読み出されると共に、上記フィールドメモリに上
記法のフィールドの情報が書き込まれるようにしたメモ
リ制御装置。It consists of one field memory and a memory control circuit that controls the address and read/write of this field memory. Therefore, the information in the above field is read out at twice the writing speed, and at the time when all the information in the above certain field is written, all the information in the above certain field is read out, and in the next field after the above certain field, the above information is read out at twice the writing speed. The memory control device is configured such that the information of the certain field is read again from the field memory at twice the writing speed, and the information of the modal field is written to the field memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4065882U JPS58144958U (en) | 1982-03-23 | 1982-03-23 | memory controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4065882U JPS58144958U (en) | 1982-03-23 | 1982-03-23 | memory controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58144958U true JPS58144958U (en) | 1983-09-29 |
| JPS6327504Y2 JPS6327504Y2 (en) | 1988-07-25 |
Family
ID=30051870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4065882U Granted JPS58144958U (en) | 1982-03-23 | 1982-03-23 | memory controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58144958U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5379421A (en) * | 1976-12-24 | 1978-07-13 | Hitachi Ltd | Television signal conversion circuit |
-
1982
- 1982-03-23 JP JP4065882U patent/JPS58144958U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5379421A (en) * | 1976-12-24 | 1978-07-13 | Hitachi Ltd | Television signal conversion circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6327504Y2 (en) | 1988-07-25 |
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